MPC5606BK Microcontroller
Reference Manual
Devices Supported:
MPC5606BKRM
Rev. 2
05/2014
MPC5606BK
MPC5605BK
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MPC5606BK Microcontroller Reference Manual, Rev. 2
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Chapter 1
Preface
1.1 Overview .........................................................................................................................................21
1.2 Audience ..........................................................................................................................................21
1.3 Guide to this reference manual ........................................................................................................21
1.4 Register description conventions ....................................................................................................25
1.5 References .......................................................................................................................................26
1.6 How to use the MPC5606BK documents .......................................................................................26
1.6.1 The MPC5606BK document set .....................................................................................26
1.6.2 Reference manual content ..............................................................................................27
1.7 Using the MPC5606BK ..................................................................................................................28
1.7.1 Hardware design .............................................................................................................28
1.7.2 Input/output pins .............................................................................................................29
1.7.3 Software design ..............................................................................................................29
1.7.4 Other features .................................................................................................................30
Chapter 2
Introduction
2.1 The MPC5606BK microcontroller family ......................................................................................31
2.2 MPC5606BK device comparison ....................................................................................................31
2.3 Device block diagram ......................................................................................................................32
2.4 Feature details .................................................................................................................................35
2.4.1 e200z0h core processor ..................................................................................................35
2.4.2 Crossbar switch (XBAR) ................................................................................................35
2.4.3 Interrupt Controller (INTC) ............................................................................................35
2.4.4 System Integration Unit Lite (SIUL) ..............................................................................36
2.4.5 Flash memory .................................................................................................................36
2.4.6 SRAM .............................................................................................................................38
2.4.7 Memory Protection Unit (MPU) ....................................................................................38
2.4.8 Boot Assist Module (BAM) ...........................................................................................38
2.4.9 Enhanced Modular Input Output System (eMIOS) ........................................................39
2.4.10 Deserial Serial Peripheral Interface Module (DSPI) ......................................................40
2.4.11 Controller Area Network module (FlexCAN) ................................................................40
2.4.12 System clocks and clock generation ...............................................................................41
2.4.13 System timers .................................................................................................................42
2.4.14 System watchdog timer ..................................................................................................43
2.4.15 Inter-Integrated Circuit (I2C) module ............................................................................43
2.4.16 On-chip voltage regulator (VREG) ................................................................................43
2.4.17 Analog-to-Digital Converter (ADC) ..............................................................................44
2.4.18 Enhanced Direct Memory Access controller (eDMA) ...................................................45
2.4.19 Cross Trigger Unit (CTU) ..............................................................................................45
2.4.20 Serial communication interface module (LINFlex) .......................................................46
2.4.21 JTAG Controller (JTAGC) .............................................................................................47
2.5 Developer support ..........................................................................................................................47
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Chapter 3
Memory Map
Chapter 4
Signal description
4.1 Package pinouts ...............................................................................................................................53
4.2 Pin muxing ......................................................................................................................................55
Chapter 5
Microcontroller Boot
5.1 Boot mechanism ..............................................................................................................................75
5.1.1 Flash memory boot .........................................................................................................76
5.1.2 Serial boot mode .............................................................................................................78
5.1.3 Censorship ......................................................................................................................78
5.2 Boot Assist Module (BAM) ............................................................................................................83
5.2.1 BAM software flow ........................................................................................................83
5.2.2 LINFlex (RS232) boot ....................................................................................................91
5.2.3 FlexCAN boot ................................................................................................................92
5.3 System Status and Configuration Module (SSCM) ........................................................................94
5.3.1 Introduction ....................................................................................................................94
5.3.2 Features ...........................................................................................................................94
5.3.3 Modes of operation .........................................................................................................95
5.3.4 Memory map and register description ............................................................................95
Chapter 6
Clock Description
6.1 Clock architecture .........................................................................................................................105
6.2 Clock gating ..................................................................................................................................106
6.3 Fast external crystal oscillator (FXOSC) digital interface ............................................................107
6.3.1 Main features ................................................................................................................107
6.3.2 Functional description ..................................................................................................107
6.3.3 Register description ......................................................................................................108
6.4 Slow external crystal oscillator (SXOSC) digital interface ..........................................................109
6.4.1 Introduction ..................................................................................................................109
6.4.2 Main features ................................................................................................................109
6.4.3 Functional description ..................................................................................................109
6.4.4 Register description ......................................................................................................110
6.5 Slow internal RC oscillator (SIRC) digital interface ....................................................................111
6.5.1 Introduction ..................................................................................................................111
6.5.2 Functional description ..................................................................................................112
6.5.3 Register description ......................................................................................................112
6.6 Fast internal RC oscillator (FIRC) digital interface ......................................................................113
6.6.1 Introduction ..................................................................................................................113
6.6.2 Functional description ..................................................................................................113
6.6.3 Register description ......................................................................................................114
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6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................115
6.7.1 Introduction ..................................................................................................................115
6.7.2 Overview ......................................................................................................................115
6.7.3 Features .........................................................................................................................115
6.7.4 Memory map ................................................................................................................116
6.7.5 Register description ......................................................................................................116
6.7.6 Functional description ..................................................................................................120
6.7.7 Recommendations ........................................................................................................122
6.8 Clock monitor unit (CMU) ............................................................................................................123
6.8.1 Introduction ..................................................................................................................123
6.8.2 Main features ................................................................................................................123
6.8.3 Block diagram ..............................................................................................................124
6.8.4 Functional description ..................................................................................................124
6.8.5 Memory map and register description ..........................................................................126
Chapter 7
Clock Generation Module (MC_CGM)
7.1 Overview .......................................................................................................................................131
7.2 Features .........................................................................................................................................132
7.3 Modes of operation ........................................................................................................................133
7.3.1 Normal and reset modes of operation ...........................................................................133
7.4 External signal description ............................................................................................................133
7.5 Memory map and register definition .............................................................................................133
7.5.1 Register descriptions ....................................................................................................137
7.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................138
7.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................139
7.6 Functional Description ..................................................................................................................142
7.6.1 System Clock Generation .............................................................................................142
7.6.2 Output Clock Multiplexing ...........................................................................................143
7.6.3 Output Clock Division Selection ..................................................................................144
Chapter 8
Mode Entry Module (MC_ME)
8.1 Overview .......................................................................................................................................145
8.1.1 Features .........................................................................................................................145
8.1.2 Modes of operation .......................................................................................................146
8.2 External signal description ............................................................................................................147
8.3 Memory map and register definition .............................................................................................147
8.3.1 Register descriptions ....................................................................................................150
8.4 Functional description ...................................................................................................................163
8.4.1 Mode transition request ................................................................................................163
8.4.2 Modes details ................................................................................................................164
8.4.3 Mode transition process ................................................................................................167
8.4.4 Protection of mode configuration registers ..................................................................175
8.4.5 Mode transition interrupts ............................................................................................175
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8.4.6 Application example .....................................................................................................177
Chapter 9
Reset Generation Module (MC_RGM)
9.1 Introduction ...................................................................................................................................179
9.1.1 Overview ......................................................................................................................179
9.1.2 Features .........................................................................................................................180
9.1.3 Modes of operation .......................................................................................................181
9.2 External signal description ............................................................................................................181
9.3 Memory map and register definition .............................................................................................182
9.3.1 Register descriptions ....................................................................................................183
9.4 Functional description ...................................................................................................................188
9.4.1 Reset state machine ......................................................................................................188
9.4.2 Destructive resets ..........................................................................................................191
9.4.3 External reset ................................................................................................................192
9.4.4 Functional resets ...........................................................................................................192
9.4.5 Alternate event generation ............................................................................................192
9.4.6 Boot mode capturing ....................................................................................................193
Chapter 10
Power Control Unit (MC_PCU)
10.1 Introduction ...................................................................................................................................195
10.1.1 Overview ......................................................................................................................195
10.1.2 Features .........................................................................................................................196
10.1.3 Modes of operation .......................................................................................................196
10.2 External signal description ............................................................................................................197
10.3 Memory map and register definition .............................................................................................197
10.3.1 Register descriptions ....................................................................................................199
10.4 Functional description ...................................................................................................................202
10.4.1 General .........................................................................................................................202
10.4.2 Reset / Power-On Reset ................................................................................................203
10.4.3 MC_PCU configuration ................................................................................................203
10.4.4 Mode transitions ...........................................................................................................203
10.5 Initialization information ...............................................................................................................205
10.6 Application information ................................................................................................................206
10.6.1 STANDBY Mode Considerations ................................................................................206
Chapter 11
Voltage Regulators and Power Supplies
11.1 Voltage regulators ..........................................................................................................................207
11.1.1 High power regulator (HPREG) ...................................................................................207
11.1.2 Low power regulator (LPREG) ....................................................................................207
11.1.3 Ultra low power regulator (ULPREG) .........................................................................208
11.1.4 LVDs and POR .............................................................................................................208
11.1.5 VREG digital interface .................................................................................................208
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11.1.6 Register description ......................................................................................................209
11.2 Power supply strategy ...................................................................................................................209
11.3 Power domain organization ...........................................................................................................210
Chapter 12
Wakeup Unit (WKPU)
12.1 Overview .......................................................................................................................................213
12.2 Features .........................................................................................................................................215
12.3 External signal description ............................................................................................................216
12.4 Memory map and register description ...........................................................................................216
12.4.1 Memory map ................................................................................................................216
12.4.2 NMI Status Flag Register (NSR) ..................................................................................217
12.4.3 NMI Configuration Register (NCR) .............................................................................218
12.4.4 Wakeup/Interrupt Status Flag Register (WISR) ...........................................................219
12.4.5 Interrupt Request Enable Register (IRER) ...................................................................219
12.4.6 Wakeup Request Enable Register (WRER) ..................................................................220
12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................220
12.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................221
12.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................221
12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................222
12.5 Functional description ...................................................................................................................222
12.5.1 General .........................................................................................................................222
12.5.2 Non-maskable interrupts ..............................................................................................223
12.5.3 External wakeups/interrupts .........................................................................................224
12.5.4 On-chip wakeups ..........................................................................................................226
Chapter 13
Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.1 Overview .......................................................................................................................................227
13.2 Features .........................................................................................................................................227
13.3 Device-specific information ..........................................................................................................229
13.4 Modes of operation ........................................................................................................................229
13.4.1 Functional mode ...........................................................................................................229
13.4.2 Debug mode ..................................................................................................................230
13.5 Register descriptions .....................................................................................................................230
13.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................230
13.5.2 RTC Control Register (RTCC) .....................................................................................231
13.5.3 RTC Status Register (RTCS) ........................................................................................233
13.5.4 RTC Counter Register (RTCCNT) ...............................................................................234
13.6 RTC functional description ...........................................................................................................234
13.7 API functional description ............................................................................................................235
Chapter 14
CAN Sampler
14.1 Introduction ...................................................................................................................................237
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14.2 Main features .................................................................................................................................237
14.3 Memory map and register description ...........................................................................................238
14.3.1 Control Register (CR) ...................................................................................................238
14.3.2 CAN Sampler Sample Registers 0–11 ..........................................................................239
14.4 Functional description ...................................................................................................................239
14.4.1 Enabling/disabling the CAN sampler ...........................................................................240
14.4.2 Selecting the Rx port ....................................................................................................240
14.4.3 Baud rate generation .....................................................................................................241
Chapter 15
e200z0h Core
15.1 Overview .......................................................................................................................................245
15.2 Microarchitecture summary ..........................................................................................................245
15.3 Block diagram ...............................................................................................................................247
15.4 Features .........................................................................................................................................247
15.4.1 Instruction unit features ................................................................................................248
15.4.2 Integer unit features ......................................................................................................248
15.4.3 Load/Store unit features ...............................................................................................249
15.4.4 e200z0h system bus features ........................................................................................249
15.5 Core registers and programmer’s model .......................................................................................249
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Device-specific features ................................................................................................................253
16.2 Introduction ...................................................................................................................................253
16.2.1 Features .........................................................................................................................254
16.3 Memory map and register definition .............................................................................................255
16.3.1 Memory map ................................................................................................................255
16.3.2 Register descriptions ....................................................................................................257
16.4 Functional description ...................................................................................................................278
16.4.1 eDMA basic data flow ..................................................................................................280
16.5 Initialization / application information ..........................................................................................283
16.5.1 eDMA initialization ......................................................................................................283
16.5.2 DMA programming errors ............................................................................................285
16.5.3 DMA request assignments ............................................................................................286
16.5.4 DMA arbitration mode considerations .........................................................................286
16.5.5 DMA transfer ................................................................................................................287
16.5.6 TCD status ....................................................................................................................290
16.5.7 Channel linking ............................................................................................................291
16.5.8 Dynamic programming .................................................................................................292
Chapter 17
eDMA Channel Multiplexer (DMA_MUX)
17.1 Introduction ...................................................................................................................................295
17.2 Features .........................................................................................................................................295
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17.3 Modes of operation ........................................................................................................................296
17.4 External signal description ............................................................................................................296
17.5 Memory map and register definition .............................................................................................296
17.5.1 Channel configuration registers (CHCONFIGn) ..........................................................297
17.6 DMA_MUX inputs .......................................................................................................................298
17.6.1 DMA_MUX peripheral sources ...................................................................................298
17.6.2 DMA_MUX periodic trigger inputs .............................................................................300
17.7 Functional description ...................................................................................................................300
17.7.1 eDMA channels with periodic triggering capability ....................................................300
17.7.2 eDMA channels with no triggering capability .............................................................302
17.8 Initialization/Application information ...........................................................................................303
17.8.1 Reset .............................................................................................................................303
17.8.2 Enabling and configuring sources ................................................................................303
Chapter 18
Interrupt Controller (INTC)
18.1 Introduction ...................................................................................................................................307
18.2 Features .........................................................................................................................................307
18.3 Block diagram ...............................................................................................................................309
18.4 Modes of operation ........................................................................................................................309
18.4.1 Normal mode ................................................................................................................309
18.5 Memory map and register description ...........................................................................................311
18.5.1 Module memory map ...................................................................................................311
18.5.2 Register description ......................................................................................................311
18.6 Functional description ...................................................................................................................319
18.6.1 Interrupt request sources ...............................................................................................327
18.6.2 Priority management ....................................................................................................328
18.6.3 Handshaking with processor .........................................................................................330
18.7 Initialization/application information ............................................................................................332
18.7.1 Initialization flow .........................................................................................................332
18.7.2 Interrupt exception handler ...........................................................................................332
18.7.3 ISR, RTOS, and task hierarchy .....................................................................................334
18.7.4 Order of execution ........................................................................................................335
18.7.5 Priority ceiling protocol ................................................................................................336
18.7.6 Selecting priorities according to request rates and deadlines .......................................336
18.7.7 Software configurable interrupt requests ......................................................................337
18.7.8 Lowering priority within an ISR ..................................................................................338
18.7.9 Negating an interrupt request outside of its ISR ..........................................................338
18.7.10 Examining LIFO contents ............................................................................................339
Chapter 19
Crossbar Switch (XBAR)
19.1 Introduction ...................................................................................................................................341
19.2 Block diagram ...............................................................................................................................341
19.3 Overview .......................................................................................................................................342
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19.4 Features .........................................................................................................................................342
19.5 Modes of operation ........................................................................................................................342
19.5.1 Normal mode ................................................................................................................342
19.5.2 Debug mode ..................................................................................................................342
19.6 Functional description ...................................................................................................................342
19.6.1 Overview ......................................................................................................................342
19.6.2 General operation .........................................................................................................343
19.6.3 Master ports ..................................................................................................................343
19.6.4 Slave ports ....................................................................................................................344
19.6.5 Priority assignment .......................................................................................................344
19.6.6 Arbitration ....................................................................................................................344
Chapter 20
System Integration Unit Lite (SIUL)
20.1 Introduction ...................................................................................................................................347
20.2 Overview .......................................................................................................................................347
20.3 Features .........................................................................................................................................349
20.4 External signal description ............................................................................................................349
20.4.1 Detailed signal descriptions ..........................................................................................350
20.5 Memory map and register description ...........................................................................................351
20.5.1 SIUL memory map .......................................................................................................351
20.5.2 Register protection ........................................................................................................352
20.5.3 Register descriptions ....................................................................................................353
20.6 Functional description ...................................................................................................................372
20.6.1 Pad control ....................................................................................................................372
20.6.2 General purpose input and output pads (GPIO) ...........................................................372
20.6.3 External interrupts ........................................................................................................373
20.7 Pin muxing ....................................................................................................................................374
Chapter 21
Memory Protection Unit (MPU)
21.1 Introduction ...................................................................................................................................375
21.2 Features .........................................................................................................................................376
21.3 Modes of operation ........................................................................................................................377
21.4 External signal description ............................................................................................................377
21.5 Memory map and register description ...........................................................................................377
21.5.1 Memory map ................................................................................................................378
21.5.2 Register description ......................................................................................................379
21.6 Functional description ...................................................................................................................390
21.6.1 Access evaluation macro ..............................................................................................390
21.6.2 Putting it all together and AHB error terminations ......................................................391
21.7 Initialization information ...............................................................................................................392
21.8 Application information ................................................................................................................392
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Chapter 22
Inter-Integrated Circuit Bus Controller Module (I
2
C)
22.1 Introduction ...................................................................................................................................397
22.1.1 Overview ......................................................................................................................397
22.1.2 Features .........................................................................................................................397
22.1.3 Block diagram ..............................................................................................................398
22.2 External signal description ............................................................................................................398
22.2.1 SCL ...............................................................................................................................398
22.2.2 SDA ..............................................................................................................................398
22.3 Memory map and register description ...........................................................................................398
22.3.1 Module memory map ...................................................................................................398
22.3.2 I
2
C Bus Address Register (IBAD) ...............................................................................399
22.3.3 I
2
C Bus Frequency Divider Register (IBFD) ...............................................................400
22.3.4 I
2
C Bus Control Register (IBCR) .................................................................................406
22.3.5 I
2
C Bus Status Register (IBSR) ....................................................................................407
22.3.6 I
2
C Bus Data I/O Register (IBDR) ...............................................................................408
22.3.7 I
2
C Bus Interrupt Configuration Register (IBIC) .........................................................409
22.4 DMA Interface ..............................................................................................................................409
22.5 Functional description ...................................................................................................................411
22.5.1 I-Bus protocol ...............................................................................................................411
22.5.2 Interrupts .......................................................................................................................414
22.6 Initialization/application information ............................................................................................415
22.6.1 I
2
C programming examples ..........................................................................................415
Chapter 23
LIN Controller (LINFlex)
23.1 Introduction ...................................................................................................................................421
23.2 Main features .................................................................................................................................421
23.2.1 LIN mode features ........................................................................................................421
23.2.2 UART mode features ....................................................................................................421
23.2.3 Features common to LIN and UART ...........................................................................421
23.3 General description .......................................................................................................................422
23.4 Fractional baud rate generation .....................................................................................................423
23.5 Operating modes ...........................................................................................................................425
23.5.1 Initialization mode ........................................................................................................426
23.5.2 Normal mode ................................................................................................................426
23.5.3 Low power mode (Sleep) .............................................................................................426
23.6 Test modes .....................................................................................................................................426
23.6.1 Loop Back mode ...........................................................................................................426
23.6.2 Self Test mode ..............................................................................................................427
23.7 Memory map and registers description .........................................................................................427
23.7.1 Memory map ................................................................................................................427
23.8 Functional description ...................................................................................................................453
23.8.1 UART mode ..................................................................................................................453
23.8.2 LIN mode ......................................................................................................................455
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23.8.3 8-bit timeout counter ....................................................................................................463
23.8.4 Interrupts .......................................................................................................................465
Chapter 24
LIN Controller (LINFlexD)
24.1 Introduction ...................................................................................................................................467
24.2 Main features .................................................................................................................................467
24.2.1 LIN mode features ........................................................................................................468
24.2.2 UART mode features ....................................................................................................468
24.3 The LIN protocol ...........................................................................................................................469
24.3.1 Dominant and recessive logic levels ............................................................................469
24.3.2 LIN frames ....................................................................................................................469
24.3.3 LIN header ....................................................................................................................470
24.3.4 Response .......................................................................................................................471
24.4 LINFlexD and software intervention ............................................................................................472
24.5 Summary of operating modes .......................................................................................................472
24.6 Controller-level operating modes ..................................................................................................473
24.6.1 Initialization mode ........................................................................................................473
24.6.2 Normal mode ................................................................................................................474
24.6.3 Sleep (low-power) mode ..............................................................................................474
24.7 LIN modes .....................................................................................................................................474
24.7.1 Master mode .................................................................................................................474
24.7.2 Slave mode ...................................................................................................................476
24.7.3 Slave mode with identifier filtering ..............................................................................478
24.7.4 Slave mode with automatic resynchronization .............................................................481
24.8 Test modes .....................................................................................................................................482
24.8.1 Loop Back mode ...........................................................................................................482
24.8.2 Self Test mode ..............................................................................................................483
24.9 UART mode ..................................................................................................................................483
24.9.1 Data frame structure .....................................................................................................483
24.9.2 Buffer ............................................................................................................................485
24.9.3 UART transmitter .........................................................................................................485
24.9.4 UART receiver ..............................................................................................................486
24.10Memory map and register description ...........................................................................................488
24.10.1 LIN control register 1 (LINCR1) .................................................................................488
24.10.2 LIN interrupt enable register (LINIER) .......................................................................491
24.10.3 LIN status register (LINSR) .........................................................................................493
24.10.4 LIN error status register (LINESR) ..............................................................................496
24.10.5 UART mode control register (UARTCR) .....................................................................497
24.10.6 UART mode status register (UARTSR) .......................................................................500
24.10.7 LIN timeout control status register (LINTCSR) ..........................................................502
24.10.8 LIN output compare register (LINOCR) ......................................................................503
24.10.9 LIN timeout control register (LINTOCR) ....................................................................504
24.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................505
24.10.11 LIN integer baud rate register (LINIBRR) ...................................................................505
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24.10.12 LIN checksum field register (LINCFR) .......................................................................506
24.10.13 LIN control register 2 (LINCR2) .................................................................................507
24.10.14 Buffer identifier register (BIDR) ..................................................................................508
24.10.15 Buffer data register least significant (BDRL) ..............................................................509
24.10.16 Buffer data register most significant (BDRM) .............................................................510
24.10.17 Identifier filter enable register (IFER) ..........................................................................511
24.10.18 Identifier filter match index (IFMI) ..............................................................................512
24.10.19 Identifier filter mode register (IFMR) ..........................................................................513
24.10.20 Identifier filter control registers (IFCR0–IFCR15) ......................................................513
24.10.21 Global control register (GCR) ......................................................................................514
24.10.22 UART preset timeout register (UARTPTO) .................................................................516
24.10.23 UART current timeout register (UARTCTO) ...............................................................516
24.10.24 DMA Tx enable register (DMATXE) ...........................................................................517
24.10.25 DMA Rx enable register (DMARXE) ..........................................................................518
24.11 DMA interface ...............................................................................................................................518
24.11.1 Master node, TX mode .................................................................................................519
24.11.2 Master node, RX mode .................................................................................................522
24.11.3 Slave node, TX mode ...................................................................................................524
24.11.4 Slave node, RX mode ...................................................................................................527
24.11.5 UART node, TX mode .................................................................................................530
24.11.6 UART node, RX mode .................................................................................................532
24.11.7 Use cases and limitations ..............................................................................................535
24.12Functional description ...................................................................................................................536
24.12.1 8-bit timeout counter ....................................................................................................536
24.12.2 Interrupts .......................................................................................................................537
24.12.3 Fractional baud rate generation ....................................................................................539
24.13Programming considerations .........................................................................................................540
24.13.1 Master node ..................................................................................................................540
24.13.2 Slave node ....................................................................................................................541
24.13.3 Extended frames ...........................................................................................................545
24.13.4 Timeout .........................................................................................................................545
24.13.5 UART mode ..................................................................................................................546
Chapter 25
FlexCAN
25.1 Information specific to this device ................................................................................................547
25.1.1 Device-specific features ...............................................................................................547
25.2 Introduction ...................................................................................................................................547
25.2.1 Overview ......................................................................................................................548
25.2.2 FlexCAN module features ............................................................................................549
25.2.3 Modes of operation .......................................................................................................549
25.3 External signal description ............................................................................................................550
25.3.1 Overview ......................................................................................................................550
25.3.2 Signal descriptions ........................................................................................................551
25.4 Memory map/register definition ....................................................................................................551
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25.4.1 FlexCAN memory mapping .........................................................................................551
25.4.2 Message Buffer Structure .............................................................................................553
25.4.3 Rx FIFO structure .........................................................................................................556
25.4.4 Register descriptions ....................................................................................................557
25.5 Functional description ...................................................................................................................576
25.5.1 Overview ......................................................................................................................576
25.5.2 Local priority transmission ...........................................................................................577
25.5.3 Transmit process ...........................................................................................................577
25.5.4 Arbitration process .......................................................................................................578
25.5.5 Receive process ............................................................................................................579
25.5.6 Matching process ..........................................................................................................580
25.5.7 Data coherence .............................................................................................................581
25.5.8 Rx FIFO ........................................................................................................................584
25.5.9 CAN protocol related features ......................................................................................584
25.5.10 Modes of operation details ...........................................................................................588
25.5.11 Interrupts .......................................................................................................................589
25.5.12 Bus interface .................................................................................................................590
25.6 Initialization/application information ............................................................................................591
25.6.1 FlexCAN initialization sequence ..................................................................................591
25.6.2 FlexCAN addressing and RAM size configurations ....................................................592
Chapter 26
Deserial Serial Peripheral Interface (DSPI)
26.1 Introduction ...................................................................................................................................593
26.2 Features .........................................................................................................................................594
26.3 Modes of operation ........................................................................................................................595
26.3.1 Master mode .................................................................................................................595
26.3.2 Slave mode ...................................................................................................................595
26.3.3 Module Disable mode ...................................................................................................595
26.3.4 Debug mode ..................................................................................................................596
26.4 External signal description ............................................................................................................596
26.4.1 Signal overview ............................................................................................................596
26.4.2 Signal names and descriptions ......................................................................................596
26.5 Memory map and register description ...........................................................................................597
26.5.1 Memory map ................................................................................................................597
26.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................598
26.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................601
26.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................602
26.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................610
26.5.6 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) ..............612
26.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................614
26.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................616
26.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) .................................................617
26.6 Functional description ...................................................................................................................618
26.6.1 Modes of operation .......................................................................................................619
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26.6.2 Start and stop of DSPI transfers ...................................................................................620
26.6.3 Serial peripheral interface (SPI) configuration .............................................................621
26.6.4 DSPI baud rate and clock delay generation ..................................................................624
26.6.5 Transfer formats ...........................................................................................................627
26.6.6 Continuous serial communications clock .....................................................................634
26.6.7 Interrupt/DMA requests ................................................................................................635
26.6.8 Power saving features ...................................................................................................637
26.7 Initialization and application information .....................................................................................638
26.7.1 How to change queues ..................................................................................................638
26.7.2 Baud rate settings .........................................................................................................638
26.7.3 Delay settings ...............................................................................................................640
26.7.4 Calculation of FIFO pointer addresses .........................................................................640
Chapter 27
Timers
27.1 Introduction ...................................................................................................................................645
27.2 Technical overview ........................................................................................................................645
27.2.1 Overview of the STM ...................................................................................................647
27.2.2 Overview of the eMIOS ...............................................................................................647
27.2.3 Overview of the PIT .....................................................................................................649
27.3 System Timer Module (STM) .......................................................................................................649
27.3.1 Introduction ..................................................................................................................649
27.3.2 External signal description ...........................................................................................650
27.3.3 Memory map and register definition ............................................................................650
27.3.4 Functional description ..................................................................................................654
27.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................655
27.4.1 Introduction ..................................................................................................................655
27.4.2 External signal description ...........................................................................................658
27.4.3 Memory map and register description ..........................................................................658
27.4.4 Functional description ..................................................................................................670
27.4.5 Initialization/Application information ..........................................................................700
27.5 Periodic Interrupt Timer (PIT) ......................................................................................................704
27.5.1 Introduction ..................................................................................................................704
27.5.2 Features .........................................................................................................................704
27.5.3 Signal description .........................................................................................................705
27.5.4 Memory map and register description ..........................................................................705
27.5.5 Functional description ..................................................................................................709
27.5.6 Initialization and application information ....................................................................710
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Overview .......................................................................................................................................715
28.1.1 Device-specific features ...............................................................................................715
28.1.2 Device-specific implementation ...................................................................................716
28.2 Introduction ...................................................................................................................................717
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28.3 Functional description ...................................................................................................................717
28.3.1 Analog channel conversion ..........................................................................................717
28.3.2 Analog clock generator and conversion timings ..........................................................720
28.3.3 ADC sampling and conversion timing .........................................................................720
28.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................725
28.3.5 Presampling ..................................................................................................................726
28.3.6 Programmable analog watchdog ..................................................................................727
28.3.7 DMA functionality .......................................................................................................728
28.3.8 Interrupts .......................................................................................................................728
28.3.9 External decode signals delay ......................................................................................729
28.3.10 Power-down mode ........................................................................................................729
28.3.11 Auto-clock-off mode ....................................................................................................729
28.4 Register descriptions .....................................................................................................................730
28.4.1 Introduction ..................................................................................................................730
28.4.2 Control logic registers ..................................................................................................737
28.4.3 Interrupt registers ..........................................................................................................740
28.4.4 DMA registers ..............................................................................................................748
28.4.5 Threshold registers .......................................................................................................752
28.4.6 Presampling registers ....................................................................................................753
28.4.7 Conversion timing registers CTR[0..2] ........................................................................756
28.4.8 Mask registers ...............................................................................................................757
28.4.9 Delay registers ..............................................................................................................761
28.4.10 Data registers ................................................................................................................763
28.4.11 Watchdog register .........................................................................................................765
Chapter 29
Cross Triggering Unit (CTU)
29.1 Introduction ...................................................................................................................................779
29.2 Main features .................................................................................................................................779
29.3 Block diagram ...............................................................................................................................779
29.4 Memory map and register descriptions .........................................................................................779
29.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................780
29.5 Functional description ...................................................................................................................781
29.5.1 Channel value ...............................................................................................................783
Chapter 30
Flash Memory
30.1 Introduction ...................................................................................................................................789
30.2 Main features .................................................................................................................................790
30.3 Block diagram ...............................................................................................................................790
30.4 Functional description ...................................................................................................................791
30.4.1 Module structure ...........................................................................................................791
30.4.2 Flash memory module sectorization .............................................................................792
30.4.3 TestFlash block .............................................................................................................793
30.4.4 Shadow sector ...............................................................................................................795
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Freescale Semiconductor 17
30.4.5 User mode operation .....................................................................................................795
30.4.6 Reset .............................................................................................................................796
30.4.7 Power-down mode ........................................................................................................797
30.4.8 Low power mode ..........................................................................................................797
30.5 Register description .......................................................................................................................798
30.5.1 CFlash register description ...........................................................................................799
30.5.2 DFlash register description ...........................................................................................834
30.6 Programming considerations .........................................................................................................857
30.6.1 Modify operation ..........................................................................................................857
30.6.2 Double word program ...................................................................................................858
30.6.3 Sector erase ...................................................................................................................860
30.7 Platform flash memory controller .................................................................................................868
30.7.1 Introduction ..................................................................................................................868
30.7.2 Memory map and register description ..........................................................................871
30.8 Functional description ...................................................................................................................880
30.8.1 Access protections ........................................................................................................880
30.8.2 Read cycles – Buffer miss ............................................................................................880
30.8.3 Read cycles – Buffer hit ...............................................................................................881
30.8.4 Write cycles ..................................................................................................................881
30.8.5 Error termination ..........................................................................................................881
30.8.6 Access pipelining ..........................................................................................................881
30.8.7 Flash error response operation ......................................................................................882
30.8.8 Bank0 page read buffers and prefetch operation ..........................................................882
30.8.9 Bank1 Temporary Holding Register .............................................................................884
30.8.10 Read-while-write functionality .....................................................................................885
30.8.11 Wait-state emulation .....................................................................................................886
Chapter 31
Static RAM (SRAM)
31.1 Introduction ...................................................................................................................................889
31.2 Low power configuration ..............................................................................................................889
31.3 Register memory map ...................................................................................................................889
31.4 SRAM ECC mechanism ................................................................................................................890
31.4.1 Access timing ...............................................................................................................890
31.4.2 Reset effects on SRAM accesses ..................................................................................891
31.5 Functional description ...................................................................................................................891
31.6 Initialization and application information .....................................................................................891
Chapter 32
Register Protection
32.1 Introduction ...................................................................................................................................895
32.2 Features .........................................................................................................................................895
32.3 Modes of operation ........................................................................................................................896
32.4 External signal description ............................................................................................................896
32.5 Memory map and register description ...........................................................................................896
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32.5.1 Memory map ................................................................................................................897
32.5.2 Register description ......................................................................................................898
32.6 Functional description ...................................................................................................................900
32.6.1 General .........................................................................................................................900
32.6.2 Change lock settings .....................................................................................................900
32.6.3 Access errors ................................................................................................................904
32.7 Reset ..............................................................................................................................................904
32.8 Protected registers .........................................................................................................................904
Chapter 33
Software Watchdog Timer (SWT)
33.1 Overview .......................................................................................................................................913
33.2 Features .........................................................................................................................................913
33.3 Modes of operation ........................................................................................................................913
33.4 External signal description ............................................................................................................914
33.5 Memory map and register description ...........................................................................................914
33.5.1 Memory map ................................................................................................................914
33.5.2 Register description ......................................................................................................915
33.6 Functional description ...................................................................................................................919
Chapter 34
Error Correction Status Module (ECSM)
34.1 Introduction ...................................................................................................................................923
34.2 Overview .......................................................................................................................................923
34.3 Features .........................................................................................................................................923
34.4 Memory map and register description ...........................................................................................923
34.4.1 Memory map ................................................................................................................923
34.4.2 Register description ......................................................................................................924
34.4.3 Register protection ........................................................................................................942
Chapter 35
IEEE 1149.1 Test Access Port Controller (JTAGC)
35.1 Introduction ...................................................................................................................................945
35.2 Block diagram ...............................................................................................................................945
35.3 Overview .......................................................................................................................................945
35.4 Features .........................................................................................................................................946
35.5 Modes of operation ........................................................................................................................946
35.5.1 Reset .............................................................................................................................946
35.5.2 IEEE 1149.1-2001 defined test modes .........................................................................946
35.6 External signal description ............................................................................................................947
35.7 Memory map and register description ...........................................................................................947
35.7.1 Instruction register ........................................................................................................947
35.7.2 Bypass register ..............................................................................................................948
35.7.3 Device identification register .......................................................................................948
35.7.4 Boundary scan register .................................................................................................949
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35.8 Functional description ...................................................................................................................949
35.8.1 JTAGC reset configuration ...........................................................................................949
35.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................949
35.8.3 TAP controller state machine .......................................................................................949
35.8.4 JTAGC instructions ......................................................................................................951
35.8.5 Boundary scan ..............................................................................................................953
35.9 e200z0 OnCE controller ................................................................................................................953
35.9.1 e200z0 OnCE controller block diagram .......................................................................953
35.9.2 e200z0 OnCE controller functional description ...........................................................954
35.9.3 e200z0 OnCE controller register description ...............................................................954
35.10Initialization/application information ............................................................................................956
Appendix A
Revision History
A.1 Changes between revisions 1 and 2 ............................................................................................957
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