NXP MPC560xB Reference guide

Freescale Semiconductor

MPC5602DRM

Rev 4.2, 12/2013

MPC5602D Microcontroller

Reference Manual

This is the MPC5602D Reference Manual set, consisting of the following files:

• MPC5602D Reference Manual Addendum (MPC5602DRMAD), Rev. 2

• MPC5602D Reference Manual (MPC5602DRM), Rev. 4.1

Freescale Semiconductor

Reference Manual Addendum

MPC5602DRMAD

Rev. 2, 12/2013

Table of Contents

This addendum document describes corrections to the

MPC5602D Microcontroller Reference Manual, order

number MPC5602DRM. For convenience, the addenda

items are grouped by revision. Please check our website

at http://www.freescale.com/powerarchitecture for the

latest updates.

The current version available of the MPC5602D

Microcontroller Reference Manual is Revision 4.1.

MPC5602D Reference Manual

Addendum

1 Addendum List for Revision 4.1 . . . . . . . . . . . . . . 2

2 Addendum List for Revision 4. . . . . . . . . . . . . . . . 3

3 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 11

Addendum List for Revision 4.1

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor2

1 Addendum List for Revision 4.1

Table 1. MPC5602D RM Rev 4.1 Addenda

Location Description

Chapter 27, “Flash Memory”

page 725

Below Table 27-4, “CFlash TestFlash Structure”.

NOTE

Unique Device ID – Memory location. This device now includes a 128-bit Unique

Identification number (UID) which is programmed during device fabrication.

Start – Stop Address Size (Bytes) Content:

• 0x00403C10 0x00403C17 8 UID 1

• 0x00403C18 0x00403C1F 8 UID 2

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor 3

2 Addendum List for Revision 4

Table 2. MPC5602DRM Rev 4 Addenda

Location Description

Chapter 6, Clock Description,

page 97

Add Note: to Section 6.8.4.1, Crystal clock monitor:

Note: Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is

greater than (FIRC / 2

RCDIV

)+0.5MHz.

Add Note: to Section 6.8.4.2, FMPLL clock monitor:

Note: Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is

greater than (FIRC / 4) + 0.5 MHz.

Chapter 8, Mode Entry

Module (MC_ME), page

125

In Table 8-3 (MC_ME memory map), change DFLAON and CFLAON bits in ME_DRUN_MC and

ME_RUN0…3_MC rows from read-only to read/write.

Chapter 8, Mode Entry

Module (MC_ME), page

125

In Figure 8-12 (DRUN Mode Configuration Register (ME_DRUN_MC)), change DFLAON and

CFLAON bits from read-only to read/write.

In Figure 8-13 (RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)), change DFLAON

and CFLAON bits from read-only to read/write.

Chapter 9, Reset Generation

Module (MC_RGM), page

191

Replace Section 9.4.7, Boot Mode Capturing, with the following:

The MC_RGM samples PA[9:8] whenever RESET is asserted until five FIRC (16 MHz internal

RC oscillator) clock cycles before its deassertion edge. The result of the sampling is used at

the beginning of reset PHASE3 for boot mode selection and is retained after RESET has been

deasserted for subsequent boots after reset sequences during which RESET is not asserted.

Note: In order to ensure that the boot mode is correctly captured, the application needs to

apply the valid boot mode value the entire time that RESET is asserted.

RESET can be asserted as a consequence of the internal reset generation. This will force

re-sampling of the boot mode pins. (See Table 9- 11 for details.)

Chapter 13, Real Time Clock /

Autonomous Periodic

Interrupt (RTC/API), page

226

In Table 13-3 (RTCC field descriptions), update the Note in RTCC[APIVAL] field description:

Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two

more cycles because of synchronization of APIVAL to the RTC clock, and APIVAL + 1 cycles

for subsequent occurrences. After that, interrupts are periodic in nature. Because of

synchronization issues, the minimum supported value of APIVAL is 4.

Chapter 15, Enhanced Direct

Memory Access (eDMA),

page 280

Replace Section 15.5.8, Dynamic programming, with the following:

15.5.8 Dynamic programming

15.5.8.1

Dynamic channel linking

Dynamic channel linking is the process of setting the TCD.major.e_link bit

during channel execution. This bit is read from the TCD local memory at the

end of channel execution, thus allowing the user to enable the feature during

channel execution.

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor4

Chapter 15, Enhanced Direct

Memory Access (eDMA),

page 280 (cont.)

Because the user is allowed to change the configuration during execution, a

coherency model is needed. Consider the scenario where the user attempts to

execute a dynamic channel link by enabling the TCD.major.e_link bit at the

same time the eDMA engine is retiring the channel. The TCD.major.e_link

would be set in the programmer’s model, but it would be unclear whether the

actual link was made before the channel retired.

The coherency model in Table 15-24 is recommended when executing a

dynamic channel link request.

For this request, the TCD local memory controller forces the TCD.major.e_link

bit to zero on any writes to a channel’s TCD.word7 after that channel’s

TCD.done bit is set, indicating the major loop is complete.

NOTE

The user must clear the TCD.done bit before

writing the TCD.major.e_link bit. The TCD.done

bit is cleared automatically by the eDMA engine

after a channel begins execution.

15.5.8.2 Dynamic scatter/gather

Dynamic scatter/gather is the process of setting the TCD.e_sg bit during

channel execution. This bit is read from the TCD local memory at the end of

channel execution, thus allowing the user to enable the feature during channel

execution.

Because the user is allowed to change the configuration during execution, a

coherency model is needed. Consider the scenario where the user attempts to

execute a dynamic scatter/gather operation by enabling the TCD.e_sg bit at the

same time the eDMA engine is retiring the channel. The TCD.e_sg would be

set in the programmer’s model, but it would be unclear whether the actual

scatter/gather request was honored before the channel retired.

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Table 15-24. Coherency model for a dynamic channel link request

Step Action

1 Write 1b to the TCD.major.e_link bit.

2 Read back the TCD.major.e_link bit.

3 Test the TCD.major.e_link request status:

• If TCD.major.e_link = 1b, the dynamic link attempt was successful.

• If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel

was already retiring).

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor 5

Chapter 15, Enhanced Direct

Memory Access (eDMA),

page 280 (cont.)

Two methods for this coherency model are shown in the following subsections.

Method 1 has the advantage of reading the major.linkch field and the e_sg bit

with a single read. For both dynamic channel linking and scatter/gather

requests, the TCD local memory controller forces the TCD.major.e_link and

TCD.e_sg bits to zero on any writes to a channel’s TCD.word7 if that channel’s

TCD.done bit is set indicating the major loop is complete.

NOTE

The user must clear the TCD.done bit before

writing the TCD.major.e_link or TCD.e_sg bits.

The TCD.done bit is cleared automatically by the

eDMA engine after a channel begins execution.

15.5.8.2.1 Method 1 (channel not using major loop channel

linking)

For a channel not using major loop channel linking, the coherency model in

Table 16-25 may be used for a dynamic scatter/gather request.

When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used

by the eDMA. In this case, the TCD.major.linkch bits may be used for other

purposes. This method uses the TCD.major.linkch field as a TCD identification

(ID).

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Table 15-25. Coherency model for method 1

Step Action

1 When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for

each TCD associated with a channel using dynamic scatter/gather.

2 Write 1b to theTCD.d_req bit.

Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a

future hardware activation of this channel. This stops the channel from executing

with a destination address (daddr) that was calculated using a scatter/gather

address (written in the next step) instead of a dlast final offset value.

3 Write theTCD.dlast_sga field with the scatter/gather address.

4 Write 1b to the TCD.e_sg bit.

5 Read back the 16 bit TCD control/status field.

6 Test the TCD.e_sg request status and TCD.major.linkch value:

• If e_sg = 1b, the dynamic link attempt was successful.

• If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did

not succeed (the channel was already retiring).

• If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was

successful (the new TCD’s e_sg value cleared the e_sg bit).

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor6

Chapter 15, Enhanced Direct

Memory Access (eDMA),

page 280 (cont.)

15.5.8.2.2 Method 2 (channel using major loop linking)

For a channel using major loop channel linking, the coherency model in

Table 15-26 may be used for a dynamic scatter/gather request. This method

uses the TCD.dlast_sga field as a TCD identification (ID).

For a channel using major loop channel linking, the coherency model in

Table 15-26 may be used for a dynamic scatter/gather request. This method

uses the TCD.dlast_sga field as a TCD identification (ID).

Chapter 15, Enhanced Direct

Memory Access (eDMA),

page 280 (cont.)

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Table 15-26.Coherency model for method 2

Step Action

1 Write 1b to theTCD.d_req bit.

Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a

future hardware activation of this channel. This stops the channel from executing

with a destination address (daddr) that was calculated using a scatter/gather

address (written in the next step) instead of a dlast final offset value.

2 Write theTCD.dlast_sga field with the scatter/gather address.

3 Write 1b to the TCD.e_sg bit.

4 Read back the TCD.e_sg bit.

5 Test the TCD.e_sg request status:

• If e_sg = 1b, the dynamic link attempt was successful.

• If e_sg = 0b, read the 32 bit TCD dlast_sga field.

• If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not

succeed (the channel was already retiring).

• If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful

(the new TCD’s e_sg value cleared the e_sg bit).

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor 7

Chapter 18, Crossbar Switch

(XBAR), page 325

Replace Figure 18-1 (XBAR block diagram), with the following:

Replace Table 18-1 (XBAR switch ports for MPC5602D), with the following:

Chapter 18, Crossbar Switch

(XBAR), throughout

chapter

Correct “two master ports” to “three master ports” as necessary.

Chapter 18, Crossbar Switch

(XBAR), page 326

In Section 18.4, Features, add a bullet item for eDMA.

Chapter 18, Crossbar Switch

(XBAR), page 328

Replace Table 18-2 (Hardwired bus master priorities) with the following.

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

CPU

Crossbar Switch

Flash

Master modules

Slave modules

CPU data

Internal

Peripheral

bridges

instructions

memory

SRAM

eDMA

Table 18-1. XBAR switch ports for MPC5602D

Module

Port

Physical master ID

Type Logical number

e200z0 core–CPU instructions Master 0 0

e200z0 core–CPU data / Nexus Master 0 1

eDMA Master 2 2

Flash memory Slave — —

Internal SRAM Slave — —

Peripheral bridges Slave — —

Table 18-2. Hardwired bus master priorities

Module

Port

Priority level

Type Master #

e200z0 core–CPU instructions Master 0 7

e200z0 core–CPU data Master 1 6

eDMA Master 2 5

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor8

Chapter 20, LINFlex, p. 394 Insert the following after Section 20.8.2.1.6, Error handling:

20.8.2.1.7 Overrun

Once the message buffer is full, the next valid message reception leads to an

overrun and a message is lost. The hardware sets the BOF bit in the LINSR to

signal the overrun condition. Which message is lost depends on the

configuration of the RX message buffer:

• If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last

message stored in the buffer is overwritten by the new incoming

message. In this case the latest message is always available to the

application.

• If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most

recent message is discarded and the previous message is available in the

buffer.

Chapter 21, LINFlexD, p. 414 Insert the following after Section 21.7.1.5, Error handling and detection:

21.7.1.6 Overrun

Once the message buffer is full, the next valid message reception leads to an

overrun and a message is lost. The hardware sets the BOF bit in the LINSR to

signal the overrun condition. Which message is lost depends on the

configuration of the RX message buffer:

• If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last

message stored in the buffer is overwritten by the new incoming

message. In this case the latest message is always available to the

application.

• If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most

recent message is discarded and the previous message is available in

the buffer.

Chapter 22, FlexCAN,

throughout chapter

Remove references throughout the chapter to “low-cost MCUs.”

Chapter 22, FlexCAN, page

491

Remove Note: at end of Section 22.2.2, FlexCAN module features:

Note: The individual Rx Mask per Message Buffer feature may not be available in low cost

MCUs. Please consult the specific MCU documentation to find out if this feature is supported.

Chapter 22, FlexCAN, page

494

Remove Note: above Ta bl e 22 -2:

Note: The individual Rx Mask per Message Buffer feature may not be available in low cost

MCUs. Please consult the specific MCU documentation to find out if this feature is supported.

If not supported, the address range 0x0880-0x097F is considered reserved space,

independent of the value of the BCC bit.

Chapter 22, FlexCAN, page

495

Added this Note in the RTR field description of Table 22-4 (Message Buffer Structure field

description):

Note: Do not configure the last Message Buffer to be the RTR frame.

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor 9

Chapter 22, FlexCAN, page

523

Remove Note: at end of Section 25.5.6, Matching process:

Note: The individual Rx Mask per Message Buffer feature may not be available in low cost

MCUs. Please consult the specific MCU documentation to find out if this feature is supported.

If not supported, the RXGMASK, RX14MASK, and RX15MASK registers are available,

regardless of the value of the BCC bit.

Chapter 22, FlexCAN, page

527

In Section 22.5.9.4, Protocol timing, update the Note following Figure 22-15 (CAN Engine

Clocking Scheme) to read: “This clock selection feature may not be available in all MCUs. A

particular MCU may not have a PLL, in which case it would have only the oscillator clock, or

it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit

in the CTRL Register has no effect on the module operation.”

Chapter 22, FlexCAN, page

529

Update the table title of Table 22-21 from “CAN Standard Compliant Bit Time Segment Settings”

to “Bosch CAN 2.0B standard compliant bit time segment settings.”

Chapter 22, FlexCAN, page

529

In Section 22.5.9.4, Protocol timing, update the Note following Table 22-21 to read: “Other

combinations of Time Segment 1 and Time Segment 2 can be valid. It is the user’s

responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit

time calculations, use an IPT (Information Processing Time) of 2, which is the value

implemented in the FlexCAN module.”

Chapter 25, Analog-to-Digital

Converter (ADC), page 662

In Section 25.3.2, Analog clock generator and conversion timings, remove the paragraph:

The direct clock should basically be used only in low power mode when the device is using

only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock

(an 8 MHz clock is not fast enough). In all other cases, the ADC should use the clock divided

by two internally.

Chapter 25, Analog-to-Digital

Converter (ADC), p. 665

In Section 25.3.4.2, CTU in trigger mode, replace the sentence:

If another CTU conversion is triggered before the end of the conversion, that request is

discarded.

with:

If another CTU conversion is triggered before the end of the conversion, that request is

discarded. However, if the CTU has triggered a conversion that is still ongoing on a channel,

it will buffer a second request for the channel and wait for the end of the first conversion before

requesting another conversion. Thus, two conversion requests close together will both be

serviced.

Chapter 25, Analog-to-Digital

Converter (ADC), page 666

In Section 25.3.5.2, Presampling channel enable signals, in Table 25-5, Presampling voltage

selection based on PREVALx fields, in the 01 row, change the “Presampling voltage” field to:

V1 = V

DD_HV_ADC0

or V

DD_HV_ADC1

.

Chapter 25, Analog-to-Digital

Converter (ADC), page 676

Add Note to Section 25.3.11, Auto-clock-off mode:

Note: The auto-clock-off feature cannot operate when the digital interface runs at the same

rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock

will not shut down in IDLE mode.

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Addendum List for Revision 4

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor10

Chapter 25, Analog-to-Digital

Converter (ADC), page 676

In Section 25.4.2.2, Main Status Register (MSR), replace the ADCSTATUS field description with

the following:

The value of this parameter depends on ADC status:

000 IDLE — The ADC is powered up but idle.

001 Power-down — The ADC is powered down.

010 Wait state — The ADC is waiting for an external multiplexer. This occurs only when the

DSDR register is nonzero.

011 Reserved

100 Sample — The ADC is sampling the analog signal.

101 Reserved

110 Conversion — The ADC is converting the sampled signal.

111 Reserved

Chapter 26, Cross Triggering

Unit (CTU), page 703

At the end of Section 26.4.1, Event Configuration Registers (CTU_EVTCFGRx) (x = 0...31), add

the following Note:

NOTE

The CTU tracks issued conversion requests to the ADC. When the ADC

is being triggered by the CTU and there is a need to shut down the ADC,

the ADC must be allowed to complete conversions before being shut

down. This ensures that the CTU is notified of completion; if the ADC

is shut down while performing a CTU-triggered conversion, the CTU is

not notified and will not be able to trigger further conversions until the

device is reset.

Chapter 30, Software

Watchdog Timer (SWT),

page 827

In Figure 30-1 (SWT Control Register (SWT_CR)), correct the reset value of SWT_CR from

0x4000_011B to 0x800_0011B.

In Section 30.5.2.1, SWT Control Register (SWT_CR), remove the following sentence:

Default value for SWT_CR_RST is 0x4000_011B, corresponding to MAP1 = 1 (only data bus

access allowed), RIA = 1 (reset on invalid SWT access), SLK = 1 (soft lock), CSL = 1 (IRC

clock source for counter), FRZ = 1 (freeze on debug), WEN = 1 (watchdog enable).

In Table 30-2 (SWT_CR field descriptions), update the MAPn field description to:

Master Access Protection for Master n.

Allows specific master to update watchdog. MAP0 = CPU, MAP2=eDMA.

The platform bus master assignments are device-specific.

0 Access for the master is not enabled

1 Access for the master is enabled

Chapter 31,Error Correction

Status Module (ECSM),

page 833

Insert the following in Section 31.2, Overview:

The AIPS is the interface between the Advanced High performance Bus (AHB) interface and

on-chip IPS peripherals. IPS peripherals are modules that contain readable/writable control

and status registers. The AHB master reads and writes these registers through the AIPS. The

AIPS generates module enables, the module address, transfer attributes, byte enables, and

write data. These elements then function as inputs to the IPS peripherals.

• IPS — Inter Peripheral Subsytem

• AIPS — interface between the Advanced High performance Bus (AHB) interface and on-chip

IPS peripherals

• AHB — Advanced High-performance Bus

Table 2. MPC5602DRM Rev 4 Addenda (continued)

Location Description

Revision History

MPC5602D Reference Manual Addendum, Rev. 2

Freescale Semiconductor 11

3 Revision History

Table 3 provides a revision history for this reference manual addendum document.

Table 3. Revision History Table

Rev. Number Substantive Changes Date of Release

2.0 Added a note below “CFlash TestFlash Structure” table. 09/2013

1.0 Initial release. 05/2012

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MPC5602DRMAD

Rev. 2

12/2013

Freescale Semiconductor

MPC5602DRM

Rev. 4.1, 05/2012

MPC5602D Microcontroller

Reference Manual

by: Microcontroller Solutions Group

This is the MPC5602D Reference Manual set, consisting of the following files:

• MPC5602D Reference Manual Addendum (MPC5602DRMAD), Rev. 1

• MPC5602D Reference Manual (MPC5602DRM), Rev. 4

Freescale Semiconductor

Reference Manual Addendum

MPC5602DRMAD

Rev. 1 , 05/2012

Table of Contents

This addendum document describes corrections to the

MPC5602D Microcontroller Reference Manual, order

number MPC5602DRM. For convenience, the addenda

items are grouped by revision. Please check our website

at http://www.freescale.com/powerarchitecture for the

latest updates.

The current version available of the MPC5602D

Microcontroller Reference Manual is Revision 4.

MPC5602D Reference Manual

Addendum

by: Microcontroller Solutions Group

1 Addendum List for Revision 4. . . . . . . . . . . . . . . . 2

2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 10

Addendum List for Revision 4

MPC5602D Reference Manual Errata, Rev. 1

Freescale Semiconductor2

1 Addendum List for Revision 4

Table 1. MPC5602DRM Rev 4 Addenda