NXP PTN3393BS User guide

Brand: NXP

Model: PTN3393BS

Type: User guide

This manual is also suitable for

PTN3355BS

NXP PTN3393BS is a DisplayPort to LVDS interface bridge IC and a companion chip for PTN3360. It supports up to 2560x1600@60Hz WQXGA resolution with 24-bit color depth using either one or two LVDS channels. The PTN3393BS is a perfect fit for various applications such as mobile or desktop monitors and other embedded systems. PTN3393BS features:

Compliant with VESA DisplayPort 1.2a specification
Compliant with VESA Dual Mode DisplayPort (DP++) specification
Supports up to 2560x1600@60Hz WQXGA resolution
Supports 24-bit color depth
Supports one or two LVDS channels
Integrated HDCP 1.4 decrypter/repeater

Compliant with VESA DisplayPort 1.2a specification
Compliant with VESA Dual Mode DisplayPort (DP++) specification
Supports up to 2560x1600@60Hz WQXGA resolution
Supports 24-bit color depth
Supports one or two LVDS channels
Integrated HDCP 1.4 decrypter/repeater

UM10755

PTN3355 (e)DP to VGA bridge IC application board

Rev. 1 — 19 January 2015 User manual

Document information

Info Content

Keywords PTN3355, PTN3393, DisplayPort, eDP, VGA, bridge, application board

Abstract This user manual presents demonstration / application board capability of

interfacing an (embedded) DisplayPort source to VGA output. The

application board (nicknamed "ULT DPVGA") is intended for use as an

evaluation and customer demonstration tool, as well as a reference

design.

User manual Rev. 1 — 19 January 2015 2 of 19

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

Revision history

Rev Date Description

1 20150119 Initial version.

User manual Rev. 1 — 19 January 2015 3 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

1. Introduction

PTN3355 is a low-power DisplayPort to VGA bridge IC with an integrated 1-2 VGA switch.

PTN3355 consumes approximately 200 mW of power for video streaming in WUXGA

resolution and 890 uW of power in low-power mode. The VGA output is powered down

when there is no valid DisplayPort source data being transmitted. PTN3355 is suitable for

Ultra Low Power Notebook and other low-power devices. PTN3355 also offers a second

VGA port for docking design.

PTN3355 is powered from a 3.3 V power source, and generates 1.5 V through an internal

step-down switch regulator and buck converter for internal core usage and DAC usage.

For cost saving, the external inductor for the buck converter can be removed; the internal

LDO can supply 1.5 V for core usage and DAC usage without any re-work.

However, using LDO consumes twice as much as the buck converter, about 400 mW.

This document describes the user manual of PTN3355 ULT DP-VGA application board,

including:

• Overall PCB connectors, jumpers, and power supplies

• Equipment/Tools that this board will be interfacing with for board testing

• System level connections such as cables and connectors that this board will be

plugged into

This application board is intended to demonstrate the bridging capabilities of PTN3355 on

low power DP to VGA conversion.

1.1 Purposes

This document is for internal engineers to evaluate the performance of PTN3355 and to

develop firmware, including collecting and verifying system level

features/performances/functionalities such as:

• Verify power management schemes

• Power sequence

• Power consumption measurement during various operating modes.

• Allow access to test points and jumpers for measurement and configuration purposes

• Flash over AUX and MS_I2C

• Programming and debug test via MS_I2C

For marketing to demonstrate ULT DP-VGA to customers in the field:

• Functional and interoperability test.

• This board should be connected to a DP or an eDP source.

• This board can be powered by an external 3V3 power adapter, or

• External power supplies with +3.3V (1A), or

• DP 1.0 cable that carries 3V3 power.

User manual Rev. 1 — 19 January 2015 4 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

For customers to evaluate PTN3355:

• Use I2C to change configuration.

2. General description

2.1 Co-layout of PTN3355 with PTN3393

This application board is designed to evaluate PTN3393 first then PTN3355 later with

component stuffing variation. An HVQFN40 socket footprint is reserved in preparation for

socket installation to test and program ICs.

Due to the bulky socket footprint, the bulk converter design has to be placed on the back

side to be close to PTN3355. Also due to co-layout for two ICs, extra components are

necessary for stuffing option.

Hence the layout is not optimal as if only PTN3355 is placed without the socket.

The placement can be dramatically improved in a real application.

2.2 Block diagram

Fig 1. ULT DP-VGA application board block diagram

(e)DP INTF

CFG

VGA CONNECTOR1

SM_BUS

PTN3355 (6x6

mm) in Socket

2-DP

AUX

HPD

H/V Sync

I2C_BUS

3.3V

4.7uH

39,38 36,35

1.5V

GND

4.7uF

1,5,21

DDC_I2C

VGA2

VGA1

VGA CONNECTOR2

JTAG DDC_I2C

4.5"

3.5"

sEEPROM

um10755_bd

User manual Rev. 1 — 19 January 2015 5 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

Fig 2. PTN3393 application board

um10755_appboard

User manual Rev. 1 — 19 January 2015 6 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

2.3 PTN3355 ULT DP-VGA application board features

• Stuff options for PT3393 or PTN3355.

• Groups of jumpers for pin configuration.

• Other jumpers for test options.

• One reset button.

• Power LED.

• HPD LED.

• One I2C header bringing out I2C pins (SCL, SDA, GND) to interface with a I

C-Bird

dongle to program (Flash over I2C) and debug.

• One I2C header for DDC control.

• One JTAG for FW download.

• One 3V3 power adapter jack.

• Test point for external power supplies 3.3 V (1A).

• Option to power from DP connector.

• Jumper to select between 3 power sources

• Two VGA connectors selectable by jumper setting.

Fig 3. PTN3355 application board

um10755_3355appboard

User manual Rev. 1 — 19 January 2015 7 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

3. Hardware requirements

• Item 1 - (e)DP sources of Intel, AMD, Apple

• Item 2 - VTG5225-DP or DPT-200, DP sources with DP 1.1 or DP1.0 cable

• Item 3 - DPA-400, AUX analyzer

• Item 4 - Different native resolution monitors

• Item 5 - FS2 with 2x5 JTAG connection for FW download

• Item 6 - I2C Bird with 1x4 header connection for s-EEPROM R/W

4. Board specifications

4.1 General description

• Layers: 4 layers expected - trace, ground, VCC, trace

• Size: 3.5" x 4.5"

• Material: FR4

• Thickness: 62 mil

• Impedance: 50 ohm single-end, 75 ohm single-end RGB, 100 ohm differential on DP

and AUX signal pairs.

4.2 PCB stack ups

Fig 4. ULT DP-VGA Application Board PCB Stack Up example

um10755_pcbstackup

User manual Rev. 1 — 19 January 2015 8 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

4.3 Top assembly drawings of the PTN3355 Application Board

Fig 5. PTN3355 application board top assembly drawings

um10755_topass

User manual Rev. 1 — 19 January 2015 9 of 19

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UM10755

PTN3355 (e)DP to VGA bridge IC application board

4.4 Bottom assembly drawings of the PTN3355 Application Board

5. Connector specifications

5.1 Connectors and jumpers

Fig 6. PTN3355 application board bottom assembly drawings

um10755_botass

Table 1. Connectors and jumpers

Jumper number Jumper name Connector name Manufacturer Part number

J1 DP CONN SINK DP RCPT 20 POS Molex 47272-0001

J2 POWER JACK CONN JACK POWER

2.1MM PC

CUI PJ-102A

J3,J4 VGA_CONN CONN D-SUB RCPT

15POS HD R/A

EDAC 634-015-274-992

J5,J7 HEADER 4 CONN HEADER .100

SINGL STR 4POS

Sullins PBC04SAAN

User manual Rev. 1 — 19 January 2015 10 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

5.2 Cables

• DP 1.0 cable to power the application board

• DP 1.1 cable for DP communication only

• VGA cable

5.3 Jumper settings

J6 HEADER, 2x5 CONN HEADER .100

DUAL STR 10POS

Sullins PBC05DAAN

J8,J10,J11 CON1 CONN HEADER .100

SINGL STR 1POS

Sullins PBC01SAAN

JP1,JP3,JP4,JP5,JP6,

JP7,JP8,JP9,JP10

HEADER 3 CONN HEADER .100

SINGL STR 3POS

Sullins PBC03SAAN

JP2 HEADER 2 CONN HEADER .100

SINGL STR 2POS

Sullins PBC02SAAN

Table 1. Connectors and jumpers

…continued

Jumper number Jumper name Connector name Manufacturer Part number

Table 2. Jumper settings

Jumper number Signal Names Jumper Settings Default Setting

JP1 +3V3_IC 1-2, select external power to measure

2-3, select 3-1 power source

2-3

JP2 HPD_ON 1-2 Enable HPD LED

OPEN: Disable HPD LED

1-2

JP3 + J8 +3V3_FB 1-2, Select 3V3 power adapter

2-3, Select external power supply

JP3-2 to J8-1, Select DP power

1-2

JP4 TESTMODE 1-2 HIGH, CFG[5:1] = JTAG PINS

2-3 LOW, CFG[5:1] = CONFIG PINS. I2C

= 40H

OPEN, CFG[5:1] = CONFIG PINS. I2C =

C0H

2-3

JP5 CFG5_TCK 1-2 HIGH, 33 MHZ XTAL is used

OPEN, 27 MHZ XTAL is used

2-3 LOW, 25 MHZ XTAL is used

OPEN

JP6 DOCK_IN 1-2 HIGH, Select VGA2

2-3 LOW or OPEN, Select VGA1

OPEN

JP7 CFG1-MS_SCL/TDI CFG1, CFG2:

11: Compliant HPD behavior, MS Bus is

used

10: Non-compliant HPD behavior

2-3

User manual Rev. 1 — 19 January 2015 11 of 19

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UM10755

PTN3355 (e)DP to VGA bridge IC application board

6. Power options

PTN3355_3393 application board can be powered by three different methods.

6.1 DP 1.0 cable

Set JP3-2 to J8-1 to select DP power

6.2 3.3 V power adapter

Set JP3 pin 2 to pin 1 to select 3V3 power adapter

JP9 CFG2-MS_SDA/TMS 01: Non-compliant HPD behavior

00: Compliant HPD behavior, MS bus is

not used

2-3

JP8 WP 1-2 HIGH, WP for S-EEPROM

2-3 LOW, No WP S-EEPROM

2-3

JP10 CFG3-FLT/TDO 1-2 HIGH, Support FLT

2-3 LOW or OPEN, No FLT support

2-3

Table 2. Jumper settings

…continued

Jumper number Signal Names Jumper Settings Default Setting

Fig 7. Power by DP 1.0 cable

um10755_powerbydp

User manual Rev. 1 — 19 January 2015 12 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

6.3 External power source

Set JP3 pin 2 to pin 3 to select external 3.3V power supply.

Clip 3.3V power lead to TP5, and clip ground lead to GND test point.

Fig 8. Power by 3.3 V power adapter

um10755_powerby3v3

User manual Rev. 1 — 19 January 2015 13 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

Fig 9. Power by external 3.3 V power supply (1 of 2)

um10755_extpwrsrc

User manual Rev. 1 — 19 January 2015 14 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

Fig 10. Power by external 3.3 V power supply (2 of 2)

um10755_pwrext3v3

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NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

7. Stuffing options

7.1 PTN3393 stuffing

Fig 11. PTN3393 stuffing option design

um10755_3393stuffing

DOCK_IN=0, SELECT VGA1

DOCK_IN=1, SELECT VGA2

CLK_O

PTN3393

DNL

DNL DNL

DNL

DNL DNL

DNL

PLACE NEAR PIN 8

PLACE NEAR PIN 5

PLACE NEAR PIN 14

PLACE NEAR PIN 27

PLACE NEAR PIN 36

PLACE NEAR PIN 38

PLACE NEAR PIN 2

PLACE NEAR PIN 1

PLACE NEAR PIN 21

TO MEASURE IC POWER

APPLY EXTERNAL PWR TO PIN1

NORMAL OP: PIN2-PIN3

REMOVE R62, PLACE

CURRENT METER ACCROSS

VBUCK_1V5 AND J9

+3V3_IC VDD_3V3

REMOVE L2, PLACE

CURRENT METER ACCROSS

+3V3_IC AND VDD_3V3

DOUBLE FOOTPRINT FOR Y1

2016 AND 3225

PARTS TO TEST: 2016 XTAL

3225 XTAL: ECS-270-20-33

3225 OSC: TXC AU-27.000MBE

DNL

INTERNAL PULL UP

RST SW

R6=10K FOR 3393, DNL

R6=0 FOR 3355. LOAD

DOCK_IN

LDOCAP_AUX

VDDE33

AUX_P

AUX_N

ML1_N

ML1_P

VDD_3V3

DOCK_IN

LDOCAP_AUX

PVDD33

TESTMODE

GRN

BLU

VDDA_DAC

DDC_SCL

RST_N

CFG5_TCK

CFG3_TDO

TDI_33

MS_SCL/TDI

HPD

SWOUT

VBUCK_1V5

ML0_N

ML0_P

HPD

MS_SDA/TMS

RED

RSET

HSYNC

VSYNC

DDC_SDA

OSC_IN

OSC_OUT

LDOCAP_DIG

VCORE

VDDA_DP

VDD_3V3

HSYNC2

VSYNC2

DDC_SCL2

DAC_33

VDDA_DAC

GRN2

RED2

CLK_O_33

DDC_SDA2

LDOCAP_AUX

CLK_O_33

MS_SDA/TMS

TRST_N

CFG5_TCK

CFG3_TDO

TDI_33

MS_SDA/TMS

TRST_N

HPD

RST_N

VDD_3V3

VDDA_3V3

VBUCK_1V5

VDD_3V3

VDD_3V3 VDDA_3V3

VDD_3V3

VDDA_DP

+3V3_IC

PVDD33

VBUCK_1V5

VDD_3V3

VDDE33

VCORE

VBUCK_1V5

LDOCAP_AUX

DOCK_IN

LDOCAP_DIG

+3V3_PWR +3V3

+3V3_IC

+3V3_IC VDD_3V3

GRN SCH[2]

BLU SCH[2]

DDC_SCL SCH[2,4]

RED SCH[2]

HSYNC SCH[2]

VSYNC SCH[2]

DDC_SDA SCH[2,4]

HSYNC2 SCH[2]

VSYNC2 SCH[2]

DDC_SCL2 SCH[2]

BLU2 SCH[2]

GRN2 SCH[2]

RED2 SCH[2]

DDC_SDA2 SCH[2]

TESTMODESCH[4]

DOCK_INSCH[4]

AUX_PSCH[3]

AUX_NSCH[3]

ML0_PSCH[3]

ML0_NSCH[3]

ML1_PSCH[3]

ML1_NSCH[3]

CFG3_TDOSCH[4]

CFG5_TCKSCH[4]

MS_SCL/TDISCH[4]

MS_SDA/TMSSCH[4]

TRST_NSCH[4]

HPDSCH[3]

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VDDA33_AUX

LDOCAP_AUX

AUX_P

AUX_N

PRX

ML0_P

ML0_N

NC1

ML1_P

ML1_N

RST_N

CLK_O

HPD

VDDA33_DP

TCK

TDO

TMS

TRSTn

TDI

DDC_SCL

GRN

RSET

VDDA33_DAC

BLU

HSYNC

NC2

VSYNC

DDC_SDA

VDDD33_IO

VDDD33_CORE

OSC_OUT

LDOCAP_DIG

OSC_IN

RED

(PTN3393)

NC3

NC4

PTN3393

VDDA33_AUX

LDOCAP_AUX

AUX_P

AUX_N

PRX

ML0_P

ML0_N

NC1

ML1_P

ML1_N

RST_N

CLK_O

HPD

VDDA33_DP

TCK

TDO

TMS

TRSTn

TDI

DDC_SCL

GRN

RSET

VDDA33_DAC

BLU

HSYNC

NC2

VSYNC

DDC_SDA

VDDD33_IO

VDDD33_CORE

OSC_OUT

LDOCAP_DIG

OSC_IN

RED

(PTN3393)

NC3

NC4

PTN3393

CFG0/DOCK_IN

OSC_IN

OSC_OUT

DDC_SCL1

RST_N

VSYNC1

HSYNC1

DDC_SDA2

CFG5/TCK

VDDA15_DP

AUX_N

SWOUT

AUX_P

ML0_P

ML0_N

GND

ML1_N

ML1_P

RED1

PVDD33

HPD

VDDA33_DNW

TESTMODE

PGND

VDDE33_IO

VDDD15

CFG1_SCL/TDI

CFG2_SDA/TMS

CFG3/TDO

DDC_SCL2

DDC_SDA1

VSYNC2

HSYNC2

BLU2

VDDE33_IO

BLU1

GRN1

GRN2

RED2

RSET

VDDA15_DAC

C22

1uF

C22

1uF

R8 1.20K 1%R8 1.20K 1%

1 2

R11 12.0K 1%R11 12.0K 1%

1 2

C15

0.1uF

C15

0.1uF

C17 0.01uFC17 0.01uF

R30 R30

1 2

R120 R120

1 2

C14

0.01uF

C14

0.01uF

2.2uF_10V

0.1uF

C18

2.2uF_10V

C18

2.2uF_10V

J11

CON1

J11

CON1

C20

0.1uF

C20

0.1uF

2.2uF_10V

R610K R610K

1 2

4.7uF

JP1

HEADER 3

JP1

HEADER 3

TP1

TP_WHITE

TP1

TP_WHITE

R19 0R19 0

C11

0.1uF

C11

0.1uF

27MHz-6pF

1 2

J10

CON1

J10

CON1

R210 R210

1 2

R9 0R9 0

C13

0.1uF

C13

0.1uF

R20 0R20 0

1 2

0.1uF

C12

2.2uF_10V

C12

2.2uF_10V

TP21

TP_RED

TP21

TP_RED

C16 2.2uF_10VC16 2.2uF_10V

C58

0.1uF

C58

0.1uF

12pF

1 2

TP6

TP_RED

TP6

TP_RED

12pF

1 2

SW1

PB-SPST-MOM

SW1

PB-SPST-MOM

1 2

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User manual Rev. 1 — 19 January 2015 16 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

7.2 PTN3355 stuffing

Fig 12. PTN3355 stuffing option design

um10755_3355stuffing

DOCK_IN=0, SELECT VGA1

DOCK_IN=1, SELECT VGA2

CLK_O

PTN3355

PLACE NEAR PIN 8

PLACE NEAR PIN 5

PLACE NEAR PIN 14

PLACE NEAR PIN 27

PLACE NEAR PIN 36

PLACE NEAR PIN 38

PLACE NEAR PIN 2

PLACE NEAR PIN 1

PLACE NEAR PIN 21

TO MEASURE IC POWER

APPLY EXTERNAL PWR TO PIN1

NORMAL OP: PIN2-PIN3

REMOVE R62, PLACE

CURRENT METER ACCROSS

VBUCK_1V5 AND J9

+3V3_IC VDD_3V3

REMOVE L2, PLACE

CURRENT METER ACCROSS

+3V3_IC AND VDD_3V3

DOUBLE FOOTPRINT FOR Y1

2016 AND 3225

PARTS TO TEST: 2016 XTAL

3225 XTAL: ECS-270-20-33

3225 OSC: TXC AU-27.000MBE

INTERNAL PULL UP

RST SW

R6=10K FOR 3393, DNL

R6=0 FOR 3355. LOAD

DOCK_IN

LDOCAP_AUX

VDDE33

AUX_P

AUX_N

ML1_N

ML1_P

VDD_3V3

DOCK_IN

LDOCAP_AUX

PVDD33

TESTMODE

GRN

BLU

VDDA_DAC

DDC_SCL

RST_N

CFG5_TCK

CFG3_TDO

TDI_33

MS_SCL/TDI

HPD

SWOUT

VBUCK_1V5

ML0_N

ML0_P

HPD

MS_SDA/TMS

RED

RSET

HSYNC

VSYNC

DDC_SDA

OSC_IN

OSC_OUT

LDOCAP_DIG

VCORE

VDDA_DP

VDD_3V3

HSYNC2

VSYNC2

DDC_SCL2

DAC_33

VDDA_DAC

GRN2

RED2

CLK_O_33

DDC_SDA2

LDOCAP_AUX

CLK_O_33

MS_SDA/TMS

TRST_N

CFG5_TCK

CFG3_TDO

TDI_33

MS_SDA/TMS

TRST_N

HPD

RST_N TRST_N

VDD_3V3

VDDA_3V3

VBUCK_1V5

VDD_3V3

VDDA_3V3

VDD_3V3

VDDA_DP

+3V3_IC

PVDD33

VBUCK_1V5

VDD_3V3

VDDE33

VCORE

VBUCK_1V5

LDOCAP_AUX

DOCK_IN

LDOCAP_DIG

+3V3_PWR +3V3

+3V3_IC

+3V3_IC VDD_3V3

GRN SCH[2]

BLU SCH[2]

DDC_SCL SCH[2,4]

RED SCH[2]

HSYNC SCH[2]

VSYNC SCH[2]

DDC_SDA SCH[2,4]

HSYNC2 SCH[2]

VSYNC2 SCH[2]

DDC_SCL2 SCH[2]

BLU2 SCH[2]

GRN2 SCH[2]

RED2 SCH[2]

DDC_SDA2 SCH[2]

TESTMODESCH[4]

DOCK_INSCH[4]

AUX_PSCH[3]

AUX_NSCH[3]

ML0_PSCH[3]

ML0_NSCH[3]

ML1_PSCH[3]

ML1_NSCH[3]

CFG3_TDOSCH[4]

CFG5_TCK

SCH[4]

MS_SCL/TDISCH[4]

MS_SDA/TMSSCH[4]

TRST_N

SCH[4]

HPDSCH[3]

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4.7uH

1 2

VDDA33_AUX

LDOCAP_AUX

AUX_P

AUX_N

PRX

ML0_P

ML0_N

NC1

ML1_P

ML1_N

RST_N

CLK_O

HPD

VDDA33_DP

TCK

TDO

TMS

TRSTn

TDI

DDC_SCL

GRN

RSET

VDDA33_DAC

BLU

HSYNC

NC2

VSYNC

DDC_SDA

VDDD33_IO

VDDD33_CORE

OSC_OUT

LDOCAP_DIG

OSC_IN

RED

(PTN3393)

NC3

NC4

PTN3355

CFG0/DOCK_IN

OSC_IN

OSC_OUT

DDC_SCL1

RST_N

VSYNC1

HSYNC1

DDC_SDA2

CFG5/TCK

VDDA15_DP

AUX_N

SWOUT

AUX_P

ML0_P

ML0_N

GND

ML1_N

ML1_P

RED1

PVDD33

HPD

VDDA33_DNW

TESTMODE

PGND

VDDE33_IO

VDDD15

CFG1_SCL/TDI

CFG2_SDA/TMS

CFG3/TDO

DDC_SCL2

DDC_SDA1

VSYNC2

HSYNC2

BLU2

VDDE33_IO

BLU1

GRN1

GRN2

RED2

RSET

VDDA15_DAC

R8 1.20K 1%

R4 0

1 2

C19

0.1uF

C14

0.01uF

0.1uF

C21

0.1uF

R10 0

2.2uF_10V

C20

0.1uF

J11

CON1

C18

2.2uF_10V

TP1

TP_WHITE

JP1

HEADER 3

4.7uF

27MHz-6pF

R160

1 2

R7 0

1 2

R150

1 2

R17 0

R130

1 2

J10

CON1

0.1uF

C13

0.1uF

C12

2.2uF_10V

0.1uF

TP21

TP_RED

R18 0

1 2

1uF

TP6

TP_RED

12pF

1 2

C58

0.1uF

1 2

C10

0.01uF

SW1

PB-SPST-MOM

12pF

1 2

User manual Rev. 1 — 19 January 2015 17 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

7.3 PTN3355_PTN3393 stuffing options table

8. References

[1] Data Specification, PTN3355.pdf, 14 July 2014

[2] Schematic, PTN3355_1.14_CONFIDENTIAL.pdf

[3] BOM, PTN3355_ONLY_REV14_BOM.xls

[4] AN11413-PTN3393-PTN3355 rev4.pdf

[5] AN11415-PTN3355 rev1.pdf

[6] Allegro layout, PTN3393 DEMO

BOARD_REV1_305-PD12-0592_PCB_07-27-2012.brd

Table 3. PTN3355_PTN3393 stuffing options table

Location Function/Value PTN3355 PTN3393

C6 0.1uF Load No Load

C7 1uF Load No Load

C16 2.2uF_10V No Load Load

C17 0.01uF No Load Load

C19 0.1uF Load No Load

R7 0 Ohm Load No Load

R9 0 Ohm No Load Load

R10 0 Ohm Load No Load

R11 12.0K 1% No Load Load

R1 10K No Load No Load

R5 10K No Load No Load

R6 0 Ohm for PTN3355

10K for PTN3393

Load No Load

R3 0 Ohm No Load Load

L1 4.7uH Load No Load

C3 4.7uF Load No Load

R4 0 Ohm Load No Load

R17 0 Ohm Load No Load

C22 1uF No Load Load

R12 0 Ohm No Load Load

R13 0 Ohm Load No Load

R15 0 Ohm Load No Load

R16 0 Ohm Load No Load

R21 0 Ohm No Load Load

R18 0 Ohm Load No Load

User manual Rev. 1 — 19 January 2015 18 of 19

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

9. Legal information

9.1 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

9.2 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Evaluation products — This product is provided on an “as is” and “with all

faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates

and their suppliers expressly disclaim all warranties, whether express, implied

or statutory, including but not limited to the implied warranties of

non-infringement, merchantability and fitness for a particular purpose. The

entire risk as to the quality, or arising out of the use or performance, of this

product remains with customer.

In no event shall NXP Semiconductors, its affiliates or their suppliers be liable

to customer for any special, indirect, consequential, punitive or incidental

damages (including without limitation damages for loss of business, business

interruption, loss of use, loss of data or information, and the like) arising out

the use of or inability to use the product, whether or not based on tort

(including negligence), strict liability, breach of contract, breach of warranty or

any other theory, even if advised of the possibility of such damages.

Notwithstanding any damages that customer might incur for any reason

whatsoever (including without limitation, all damages referenced above and

all direct or general damages), the entire liability of NXP Semiconductors, its

affiliates and their suppliers and customer’s exclusive remedy for all of the

foregoing shall be limited to actual damages incurred by customer based on

reasonable reliance up to the greater of the amount actually paid by customer

for the product or five dollars (US$5.00). The foregoing limitations, exclusions

and disclaimers shall apply to the maximum extent permitted by applicable

law, even if any remedy fails of its essential purpose.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

9.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

NXP Semiconductors

UM10755

PTN3355 (e)DP to VGA bridge IC application board

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 January 2015

Document identifier: UM10755

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

10. Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Purposes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 General description. . . . . . . . . . . . . . . . . . . . . . 4

2.1 Co-layout of PTN3355 with PTN3393. . . . . . . . 4

2.2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 PTN3355 ULT DP-VGA application board

features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Hardware requirements. . . . . . . . . . . . . . . . . . . 7

4 Board specifications . . . . . . . . . . . . . . . . . . . . . 7

4.1 General description . . . . . . . . . . . . . . . . . . . . . 7

4.2 PCB stack ups . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.3 Top assembly drawings of the PTN3355

Application Board . . . . . . . . . . . . . . . . . . . . . . . 8

4.4 Bottom assembly drawings of the PTN3355

Application Board . . . . . . . . . . . . . . . . . . . . . . . 9

5 Connector specifications . . . . . . . . . . . . . . . . . 9

5.1 Connectors and jumpers . . . . . . . . . . . . . . . . . 9

5.2 Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Jumper settings . . . . . . . . . . . . . . . . . . . . . . . 10

6 Power options . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.1 DP 1.0 cable. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2 3.3 V power adapter . . . . . . . . . . . . . . . . . . . . 11

6.3 External power source . . . . . . . . . . . . . . . . . . 12

7 Stuffing options . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1 PTN3393 stuffing . . . . . . . . . . . . . . . . . . . . . . 15

7.2 PTN3355 stuffing . . . . . . . . . . . . . . . . . . . . . . 16

7.3 PTN3355_PTN3393 stuffing options table . . . 17

8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

9.1 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.2 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.3 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

NXP PTN3393BS User guide

Brand: NXP

Model: PTN3393BS

Type: User guide

This manual is also suitable for

PTN3355BS

Compliant with VESA DisplayPort 1.2a specification
Compliant with VESA Dual Mode DisplayPort (DP++) specification
Supports up to 2560x1600@60Hz WQXGA resolution
Supports 24-bit color depth
Supports one or two LVDS channels
Integrated HDCP 1.4 decrypter/repeater

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NXP PTN3393BS User guide

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NXP PTN3393BS User guide

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