Intel 31154 User manual

Order Number: 278944-001

Intel

®

31154 133 MHz PCI Bridge

Design Guide

April 2004

2 Intel

®

31154 133 MHz PCI Bridge Design Guide

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®

PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS

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The Intel

®

31154 133 MHz PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

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*Other names and brands may be claimed as the property of others.

Intel

®

31154 133 MHz PCI Bridge Design Guide 3

Contents

1 About This Document......................................................................................................................7

1.1 Terminology and Definitions .................................................................................................7

2 Introduction......................................................................................................................................9

2.1 Product Overview .................................................................................................................9

2.2 Features List.......................................................................................................................10

2.3 Related External Specifications..........................................................................................11

2.4 References .........................................................................................................................11

3 Package Information......................................................................................................................13

3.1 Total Signal Count ..............................................................................................................17

4 Terminations..................................................................................................................................19

5 PCI/PCI-X Interface.......................................................................................................................29

5.1 PCI/PCI-X Voltage Levels...................................................................................................29

5.2 Interrupt Routing.................................................................................................................29

5.3 IDSEL Lines........................................................................................................................30

5.3.1 Primary IDSEL Line ...............................................................................................30

5.3.2 Secondary IDSEL Lines.........................................................................................30

5.3.3 Secondary IDSEL Masking....................................................................................31

5.3.4 Secondary Clock Control.......................................................................................31

5.4 CompactPCI* Hot Swap Mode Select ................................................................................31

5.5 Opaque Memory Region Enable ........................................................................................31

5.6 PCI-X Initialization Clocking Modes....................................................................................32

5.6.1 Primary PCI Clocking Mode...................................................................................32

5.6.2 Secondary PCI Clocking Mode..............................................................................32

5.6.3 Primary-to-Secondary Frequency Limits................................................................34

6 Routing Guidelines........................................................................................................................35

6.1 Crosstalk.............................................................................................................................36

6.2 EMI Considerations ............................................................................................................37

6.3 Power Distribution and Decoupling.....................................................................................38

6.3.1 Decoupling Recommendations..............................................................................38

6.4 Trace Impedance................................................................................................................39

7 PCI-X Layout Guidelines ...............................................................................................................41

7.1 PCI Clock Layout Guidelines..............................................................................................42

7.2 PCI-X Topology Layout Guidelines.....................................................................................44

7.2.1 Single Slot at 133 MHz ..........................................................................................45

7.2.1.1 Intel

®

31154 133 MHz PCI Bridge Embedded Application at 133 MHz.46

7.2.2 Dual-Slot at 100 MHz.............................................................................................47

7.2.2.1 Embedded Intel

®

31154 133 MHz PCI Bridge Application at 100 MHz.48

7.2.3 Quad-Slots at 66 MHz ...........................................................................................49

7.2.3.1 Embedded Intel

®

31154 133 MHz PCI Bridge Application at 66 MHz...51

7.2.4 PCI-X at 33 MHz....................................................................................................52

7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview...........................52

4 Intel

®

31154 133 MHz PCI Bridge Design Guide

Contents

7.2.4.2 PICMG 1.2 System Overview................................................................52

8 Power Considerations ...................................................................................................................57

8.1 Analog Power Pins.............................................................................................................57

8.2 Power Sequencing..............................................................................................................58

9 Customer Reference Board...........................................................................................................59

10 Debug Connectors and Logic Analyzer Connectivity ....................................................................61

10.1 Probing PCI-X Signals........................................................................................................61

11 Thermal Solutions..........................................................................................................................69

12 References....................................................................................................................................71

12.1 Related Documents............................................................................................................71

Figures

1Intel

®

31154 133 MHz PCI Bridge Applications............................................................................9

2Intel

®

31154 133 MHz PCI Bridge Package...............................................................................14

3Intel

®

31154 133 MHz PCI Bridge Ball Map—Top View, Left Side............................................15

4Intel

®

31154 133 MHz PCI Bridge Ball Map—Top View, Right Side..........................................16

5 IDSEL Mapping ..........................................................................................................................30

6 Crosstalk Effects on Trace Distance and Height........................................................................36

7 PCB Ground Layout Around Connectors ...................................................................................37

8 PCI Clock Distribution and Matching Requirements...................................................................43

9 Single-Slot Point-to-Point Topology............................................................................................45

10 Embedded Intel

®

31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout..........................46

11 Dual-Slot Configuration ..............................................................................................................47

12 Embedded Intel

®

31154 133 MHz PCI Bridge Design 100 MHz PCI-X Layout..........................48

13 Quad-Slots 66 MHz Topology ....................................................................................................49

14 Embedded Intel

®

31154 133 MHz PCI Bridge Wiring for 66 MHz..............................................51

15 An Example of an ePCI-X System..............................................................................................53

16 PCI-X Data Bus PICMG 1.2 Style Backplane.............................................................................54

17 PCI-X Clock PICMG 1.2 Style Backplane ..................................................................................55

18 P_VCCA Filter............................................................................................................................57

19 S_VCCA Filter............................................................................................................................57

20 PVIO Voltage Protection Diode ..................................................................................................58

21 Intel

®

IQ31154 Customer Reference Board Block Diagram.......................................................59

Tables

1 Terminology and Definition...........................................................................................................7

2 PCI-to-PCI Bridge Configurations.................................................................................................9

3 Features List...............................................................................................................................10

4 Total Signal Count......................................................................................................................17

5 Pull-Up/Pull-Down Terminations.................................................................................................19

6 PCI/PCI-X Voltage Levels ..........................................................................................................29

7 HS_FREQ Encoding...................................................................................................................31

8 PCI-X Clocking Modes ...............................................................................................................33

Intel

®

31154 133 MHz PCI Bridge Design Guide 5

Contents

9 Secondary Bus Frequency Initialization......................................................................................33

10 PCI-X Initialization Pattern..........................................................................................................34

11 Intel

®

31154 133 MHz PCI Bridge Decoupling Recommendations............................................38

12 Add-in Card Routing Parameters................................................................................................41

13 PCI-X Slot Guidelines.................................................................................................................44

14 Wiring Lengths for 133 MHz Slot................................................................................................45

15 Wiring Lengths for Embedded 133 MHz Design.........................................................................46

16 Wiring Lengths for 100 MHz Dual-Slot .......................................................................................47

17 Wiring Lengths for Embedded 100 MHz Design.........................................................................48

18 Wiring Lengths for 66 MHz Quad-Slot........................................................................................49

19 Wiring Lengths for Embedded 66 MHz Design...........................................................................51

20 Wiring Lengths for PICMG 1.2 Backplane..................................................................................54

21 PCI-X Clock Wiring Lengths for PICMG Backplane ...................................................................55

22 Customer Reference Board Stackup..........................................................................................60

23 Logic Analyzer Pod 1..................................................................................................................62

24 Logic Analyzer Pod 2..................................................................................................................63

25 Logic Analyzer Pod 3..................................................................................................................64

26 Logic Analyzer Pod 4..................................................................................................................65

27 Logic Analyzer Pod 5..................................................................................................................66

28 Logic Analyzer Pod 6..................................................................................................................67

29 Operational Power......................................................................................................................69

30 Design Reference Material.........................................................................................................71

31 Intel

®

Related Documentation....................................................................................................71

6 Intel

®

31154 133 MHz PCI Bridge Design Guide

Contents

Revision History

Date Revision Description

April 2004 001 Initial release

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 7

About This Document

About This Document 1

This document provides layout information and guidelines for designing platform or add-in board

applications with the Intel

®

31154 133 MHz PCI Bridge.

This document is intended to be used as a guideline only. Intel recommends that you employ best-

known design practices with board-level simulation, signal-integrity testing, and validation for a

robust design. Please note that this design guide focuses on specific design considerations for the

31154 Bridge and is not intended to be an all-inclusive list of all good design practices. Use this

guide as a starting point, and use empirical data to optimize your particular design.

1.1 Terminology and Definitions

Table 1. Terminology and Definition (Sheet 1 of 2)

Term Definition

31154 Intel

®

31154 133 MHz PCI Bridge

Stripline

Stripline in a PCB is composed of the

conductor inserted in a dielectric with GND

planes to the top and bottom, as shown in the

cross-section diagram at left.

NOTE: An easy way to distinguish stripline

from microstrip is that you need to

strip away layers of the board to view

the trace on stripline.

Microstrip

Microstrip in a PCB is composed of the

conductor on the top layer above the

dielectric with a ground plane below, as

shown in the cross-section diagram at left.

Prepreg

Prepreg is material used for the lamination process of manufacturing PCBs. It consists of a

layer of epoxy material that is placed between two cores. This layer melts into epoxy when

heated and forms around adjacent traces.

Core

Core material is used for the lamination process of manufacturing PCBs. This material is two-

sided laminate with copper on each side. The core is an internal layer that is etched.

PCB

Printed circuit board: An example PCB

manufacturing process consists of the

following steps:

• A PCB consists of alternating layers of

core and prepreg stacked.

• The finished PCB is heated and cured.

• The via holes are drilled.

• Plating covers holes and outer surfaces.

• Etching removes unwanted copper.

• The PCB is tinned, coated with solder

mask, and silk-screened.

Layer 1: copper

Prepreg

Layer 2: GND

Core

Layer 3: V

CC

Layer 4: coppe

r

Prepreg

Example of a cross-section of

a four-layer stack

8 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

About This Document

§ §

Aggressor

An aggressor network is a network that transmits a coupled signal to another network.

Victim

A network that receives a coupled cross-talk signal from another network is a called the victim

network.

Network

A network is the trace of a PCB that completes an electrical connection between two or more

components.

Stub A stub is a branch from a trunk terminating at the pad of an agent.

ISI

Inter-Symbol Interference (ISI) occurs when a transition that has not been completely

dissipated interferes with a signal being transmitted down a transmission line. ISI can impact

both timing and signal integrity. It is dependent on frequency, time delay of the line, and the

refection coefficient at the driver and receiver. Examples of ISI patterns that can be used in

testing at the maximum allowable frequencies are the sequences shown below:

0101 0101 0101 0101

0011 0011 0011 0011

000 1110 0011 1000 1111

Device

A device is a component of a PCI system that connects to a PCI bus. As defined by PCI 2.3,

a device can be a single-function or a multi-function device.

Downstream A transaction that targets the secondary side of the bridge is a downstream transaction.

Upstream A transaction that targets the primary side of the bridge is an upstream transaction.

SHB

SHB is a system host board in a PICMIG 1.2 backplane. The removable CPU board provides

clocks and arbitration signals as well as an optional ATX power supply control.

ePCI-X Embedded PCI-X specification

CRB Customer Reference Board

Table 1. Terminology and Definition (Sheet 2 of 2)

Term Definition

B3337-01

Aggressor Network

Zo Zo

Victim Network

Zo Zo

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 9

Introduction

Introduction 2

2.1 Product Overview

The Intel

®

31154 133 MHz PCI Bridge (called hereafter the “31154”) is a PCI component that

functions as a highly concurrent, low-latency transparent bridge between two PCI buses. The

31154 can operate as a PCI-to-PCI bridge in the configurations shown in Table 2.

The 31154 is used on motherboards to provide additional I/O expansion slots. It is also used on PCI

add-in cards to mitigate the restrictive electrical loading constraints imposed on an expansion slot,

enabling multiple conventional PCI or multiple PCI-X devices to reside on a single PCI I/O

adapter. The 31154 block diagram in Figure 1 indicates potential 31154 applications for a range of

PCI bus speeds.

Table 2. PCI-to-PCI Bridge Configurations

Primary Bus Interface Secondary Bus Interface

PCI 2.3 PCI 2.3

PCI 2.3 PCI-X

PCI-X PCI 2.3

PCI-X PCI-X

Figure 1. Intel

®

31154 133 MHz PCI Bridge Applications

PCI-X Bus

Legacy

33 MHz

Legacy

66 MHz

PCI-X Bus 66 MHz Slots

Multi PCI-X

Devices

PCI-X Bus 100 MHz Slots

High-End

Application

CPU Host

PCI-X Bus 133 MHz Slot

10 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Introduction

The 31154 has additional hardware support for CompactPCI* Hot Swap and Redundant System

Slot via queue flush, arbiter lock, and clock output tristating.

The 31154 supports any combination of 32-bit and 64-bit data transfers on its primary and

secondary bus interfaces. The 31154 is 33/66 MHz capable in conventional PCI mode, and can run

at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode, depending upon its

surrounding environment.

2.2 Features List

Table 3. Features List

• PCI bus interfaces (2):

— PCI Local Bus Specification,

Revision 2.3 compliant

— PCI-to-PCI Bridge Architecture

Specification, Revision 1.2 compliant

— PCI Bus Power Management

Interface Specification, Revision 1.1

compliant

— PCI-X Addendum to the PCI Local

Bus Specification, Revision 1.0b

compliant

— External SROM support

— Vital Products Data (VPD) support

— 64-bit initiator/target capable

— 64-bit addressing

• Hardware support for dual-host cPCI

configurations

• Compact PCI Hot Swap Specification,

Revision 2.1 R2.0 support

• Secondary clock generation with 10 clock

outputs

• Secondary bus arbitration:

— Internal arbiter supports nine agents in

addition to the 31154.

— Internal arbiter can be disabled.

— Optimized for PCI-X mode

— Bus parking on bridge or last master

• Improved buffer architecture:

— 8 KBytes data buffers in each

direction

— Improved level of concurrency:

Up to nine outstanding transactions on

each bus simultaneously

• Scalability and flexibility:

— Conventional PCI 32/64-bit

33/66 MHz, 3.3 V

— 5 V tolerant inputs

— PCI-X 32/64-bit 66/100/133 MHz,

3.3 V

• JTAG interface

• GPIO interface:

— Allows simple software-controlled

signaling protocols

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 11

Introduction

2.3 Related External Specifications

• PCI Local Bus Specification, Revision 2.3

• PCI-to-PCI Bridge Architecture Specification, Revision 1.1

• PCI Bus Power Management Interface Specification, Revision 1.1

• Compact PCI Hot Swap Specification, Revision 2.1 R2.0

• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.1

• Embedded PCI-X Specification PICMG 1.2 R1.0

2.4 References

This section lists references that can be useful with a 31154 application. These documents are

available on the Intel Developer website (http://developer.intel.com):

• Intel

®

31154 133 MHz PCI Bridge Datasheet (278821)

• Intel

®

31154 133 MHz PCI Bridge Developer’s Manual (278848)

• Intel

®

31154 133 MHz PCI Bridge Specification Update (300826)

• Intel

®

31154 133 MHz PCI Bridge Design Checklist (300959)

• Intel

®

31154 133 MHz PCI Bridge Evaluation Board Schematics (278839)

§ §

12 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Introduction

THIS PAGE INTENTIONALLY LEFT BLANK

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 13

Package Information

Package Information 3

The Intel

®

31154 133 MHz PCI Bridge is offered in a 421-lead PBGA package. The mechanical

dimensions for this package are provided in Figure 2 on page 14.

Figure 3 on page 15 and Figure 4 on page 16 show the 421-lead PBGA, mapped by pin function.

These figures are helpful in placing components around the 31154 for the layout of a PCB. To

simplify routing and minimize the number of cross traces, keep this layout in mind when placing

components on your board. The signals, by design, are located on the PBGA package to simplify

signal routing and system implementation. Figure 3 shows the left side of the 31154 ball map, and

Figure 4 shows the right side of the ball map.

14 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Package Information

Figure 2. Intel

®

31154 133 MHz PCI Bridge Package

B1290-01

BOTTOM VIEW

SIDE VIEW

TOP VIEW

1.27

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

AA

Y

W

U

T

C

Ø

BA0.30

S

S S

Ø

1.53 REF 1.27

1.27

1.53 REF

PIN #1

CORNER

0.90

0.60

23

22

21

20

19

18

17

16

V

AB

AC

PIN #1 I.D. (SHINY)

1.0 DIA. X 0.15 DEPTH

9.0 X 9.0 FROM CENTER LINE

90.0˚

1.70

Au GATE

PIN #1 CORNER

NO RADIUS

SEE DETAIL "A"

45˚ CHAMFER

4 PLACES

(22.10 REF)

26.00 ± 0.20

(22.10 REF)

31.00 ± 0.10

26.00 ± 0.20

3 X Ø1.00 THRU

0.61 ± 0.06

2.38 ± 0.21

30˚

0.60 ± 0.10

1.17 ± 0.05

SEATING PLANE

3

2

3

0.15

// C

0.127 A

-B-

0.127// A

-C-

NOT TO SCALE

DETAIL "A"

1. All dimensions and tolerances conform to ANSI Y14.5M-1982.

Dimension is measured at the maximum solder ball

diameter, parallel to primary datum

Primary datum and seating plane are defined by the

spherical crowns of the solder balls.

4. All dimensions, unless otherwise specified, are in millimeters.

Notes:

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 15

Package Information

Figure 3. Intel

®

31154 133 MHz PCI Bridge Ball Map—Top View, Left Side

B2240-01

A

1 2 3 4 5 6 7 8 9 10 11 12

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

A

1 2 3 4 5 6 7 8 9 10 11 12

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

VSSVCCP VCC VCC

VSSVSS

VSS

VSSVCCP VSS VSS VSS VSS

VSS VSS

VCCP VSS VSS

VSS

P_

ACK64#

P_

AD56

P_

AD43

P_

AD38

P_

AD45

P_

AD42

P_

AD36

P_

AD41

HS_

SM

P_

AD44

P_

AD46

S_CLK

OEN1

S_CLK

OEN0

S_

AD34

S_

AD33

S_

AD36

S_

AD35

S_

AD32

S_

AD37

S_

AD49

S_

AD48

S_

GNT7#

S_

AD42

S_

AD53

S_

AD52

S_

AD55

S_MAX

100

S_

AD54

S_

GNT6#

S_

AD44

S_

REQ2#

S_CLK

STABLE

S_

AD46

S_

AD57

S_

CBE7#

S_

GNT2#

S_

REQ1#

S_

GNT1#

S_

REQ4#

S_

CBE6#

S_

GNT4#

S_

GNT3#

S_

REQ5#

S_

GNT5#

S_

AD02

S_

AD03

S_

CBE4#

S_

AD58

S_

AD59

S_

AD61

S_

AD60

S_

AD62

S_

AD63

S_

AD01

S_

CBE0#

S_

AD04

S_

AD06

S_

AD00

S_

PAR64

S_

CBE5#

S_

ACK64#

S_

AD56

S_

REQ6#

S_VIO

S_

AD51

S_

AD50

S_

REQ7#

S_

AD47

S_

AD45

S_

AD43

SR_

CLK

SR_CS

S_

AD39

S_

AD38

SR_DO

HS_

LED_

OUT

S_TRI

STATE

HS_

LSTAT

HS_

FREQ0

HS_

ENUM#

SCAN_

EN

S_CLK

OEN2

P_

AD54

P_

AD48

P_

AD47

P_

AD51

P_

AD62

P_

AD53

P_

PERR#

P_

AD58

P_

AD61

P_

CBE5#

P_

REQ64#

P_

STOP#

S_CLK

OEN3

P_

SERR#

P_

AD49

P_

AD50

P_

AD52

P_

AD35

P_

AD39

P_

AD40

P_

AD33

P_

AD32

P_

AD34

P_

AD37

P_

M66EN

P_

AD55

P_

AD57

P_

AD59

P_

AD63

P_

CBE6#

P_

AD60

P_

CBE4#

P_

CBE7#

P_

PAR64

VSS

VSS VCCP

VCCP VSS VSS VCCP

VCCP VSS

VSS

VSS VCC VCC

VCC

S_

AD41

S_

AD40

SR_DIVCC

VCC VCC

VCC

NC

VCC

VCCP VSS

VSS

VCCP VSS

VSS

QE

VSS VSS VSS

VSS

VCCP

VSS

VSS VSS VSS VCCP

VSS

VCCP

VSSVSS

VCCP VCC VCCVSS

VSS

VSS VSS

VSSVCCP R_REF VSS

TMODE

2

CRS

TEN

S_

REQ3#

16 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Package Information

Figure 4. Intel

®

31154 133 MHz PCI Bridge Ball Map—Top View, Right Side

B2241-01

A

13 14 15 16 17 18 19 20 21 22 23

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

VSS

VSSVCCP

VSS

P_

VCCA

VCCP

VSS

TDIVSS

VSSTCKVSSVSS

VCC VSS

VCC

VCC VCC

VSS VCCP

VSS

VCCVCC

VCC

VCC VCC

GPIO7GPIO6GPIO4

TMODE

1

OPAQUE

_EN

IDSEL_

MASK

TMODE

3

RSRV0VSS

DEV_

64BIT#

GPIO3 GPIO5 VSS VSS

VSS VCCP

TMODE

0

VSS

VCCP

VSS

VCC

P_

AD06

P_

AD03

MT0#

P_

CBE2#

P_DEV

SEL#

P_

AD22

P_

CLK

GPIO2

S_

CLKO0

S_

CLKO2

S_

CLKO1

S_

CLKO4

GPIO1GPIO0

HS_

FREQ1

NT_

MASK#

P_

AD24

P_

RST#

P_

AD16

P_

AD26

P_

AD14

P_

AD20

P_

AD31

P_

AD19

P_

AD25

P_

AD21

P_

AD23

S_

CLKO3

P_

AD27

P_

AD28

S_

CLKO5

S_

AD27

S_

CLKO6

S_

AD30

S_

AD31

S_

AD25

S_

AD26

S_

AD28

S_BRG

CLKO

S_

CLK07

S_

CLKO8

S_

M66EN

S_

AD24

S_PCIX

CAP

S_

AD23

S_

AD20

S_ARB

_DIS

ABLE

S_

AD22

S_

GCLK

OEN

S_

AD19

S_

RST#

S_

AD18

S_

AD16

S_

AD17

S_

AD14

S_

AD29

S_

CBE3#

S_

AD10

S_

AD07

S_

FRAME#

S_

PAR

S_

AD09

S_

CBE1#

S_

REQ64#

S_

CBE2#

S_

STOP#

S_

VCCA

S_

CLKI

S_

AD12

S_

SERR#

S_

DEVSEL#

S_

IRDY#

S_

AD08

S_

AD05

MT1#

S_

PERR#

S_

GNT0#

S_

AD13

S_

REQ0#

P_

AD29

P_

AD30

P_

AD18

P_

AD17

P_VIO

P_

AD12

P_

AD13

P_

AD11

P_

AD01

P_

AD07

P_

AD04

P_

FRAME#

P_

IRDY#

P_

CBE3#

P_

CBE0#

P_

AD00

P_

AD02

P_

CBE1#

P_

REQ#

P_

AD15

P_

AD08

P_

AD05

P_

TRDY#

P_

IDSEL

P_

GNT#

P_

PAR

P_

AD10

P_

AD09

VSS

TRST#

VCCP TMSVCC

VSS

VSS VSS

S_

REQ8#

S_

AD15

S_

AD21

S_

GNT8#

S_

TRDY#

S_

AD11

VSS VSS

VCC VSS

VSS

VSSVSS VCCP VSS VSS

VSS

VCCPVSS

VSS

VCC

VSS VCCP

TDO

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 17

Package Information

3.1 Total Signal Count

§ §

Table 4. Total Signal Count

Interface Signals

PCI bus interface 112

PCI 64-bit extensions 78

Clock and reset 20

JTAG 12

Serial ROM interface 4

CompactPCI* Hot Swap 6

Hardware strap 5

Miscellaneous 17

Total 254

18 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Package Information

THIS PAGE INTENTIONALLY LEFT BLANK

Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide 19

Terminations

Terminations 4

This chapter details all the recommended Intel

®

31154 133 MHz PCI Bridge terminations required

for the different operating modes.

The chapter provides the recommended pull-up and pull-down terminations for a 31154 layout.

Table 5 lists these 31154 termination values. Note that for motherboards, the PCI Local Bus

Specification, Revision 2.3 requires that the PCI signals provide the termination resistors.

Table 5. Pull-Up/Pull-Down Terminations (Sheet 1 of 9)

Signal Pull-Up/Pull-Down or Termination (See Note 1) Comments

PCI Reset

P_RST# Connect to bus RST# signal on primary PCI bus.

S_RST#

Connect to bus RST# signal on secondary PCI

bus.

Primary PCI Signals

P_AD[31:0] Connect to primary PCI bus AD[31:0].

P_AD[63:32]

For 64-bit primary PCI bus:

• Connect to the AD[63:32] bits of the primary

PCI bus.

For 32 bit Primary PCI Bus:

• Pull up through individual external resistors

(see Note 2 and Note 3).

P_CBE[3:0]

Connect to the CBE[3:0}# bits of the primary PCI

bus.

P_CBE[7:4]#

For 64-bit primary PCI bus:

• Connect to the CBE[7:4]# bits of the primary

PCI bus.

For 32-bit primary PCI Bus:

• Pull up through individual external resistors

(see Note 2 and Note 3).

P_FRAME# Connect to FRAME# of the primary PCI bus.

P_DEVSEL# Connect to DEVSEL# of the primary PCI bus.

P_IRDY# Connect to IRDY# of the primary PCI bus.

P_TRDY# Connect to TRDY# of the primary PCI bus.

P_STOP# Connect to STOP# of the primary PCI bus.

NOTES:

1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V

signaling R

MIN

= 2.42 KΩ, R

TYP

=8.2KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value

is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3. For plug-in card implementations, the pull-up must be on the motherboard.

4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or

0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in

Section 8.2 on page 58

.

20 Intel

®

31154 133 MHz PCI Bridge Design Guide Design Guide

Terminations

P_GNT# Connect to GNT# of the primary PCI bus.

P_IDSEL#

Connect to one of the AD lines of the primary PCI

bus or to the IDSEL# signal of the PCI edge

connector (for add-in card applications).

Refer to Section 5.3, “IDSEL Lines” on page 30 for

more details.

P_M66EN

Connect to the M66EN signal of the primary PCI

bus of the PCI add-in card finger.

P_PAR Connect to PAR of the primary PCI bus.

P_PAR64 Connect to PERR# of the primary PCI bus.

P_PERR# Connect to PERR# of the primary PCI bus.

P_REQ#

Connect to one of the PCI bus request signals of

the primary PCI bus.

P_SERR# Connect to SERR# of the primary PCI bus.

Secondary PCI Signals

S_AD[63:32]

Pull up to VCC33 through external 8.2 KΩ

resistors.

S_CBE[7:4]#

Pull up to VCC33 through external 8.2 KΩ

resistors.

S_REQ64#

Pull up to VCC33 through external 8.2 KΩ

resistors.

S_ACK64#

Pull up to VCC33 through external 8.2 KΩ

resistors.

S_FRAME#,

S_IRDY#,

S_TRDY#,

S_STOP#,

S_DEVSEL#,

S_PERR#,

S_SERR#

Pull up to VCC33 voltage through external 8.2 KΩ

resistors.

S_REQ[8:1]#,

S_REQ0#/BR_GNT#,

S_GNT0#/BR_REQ#

Pull up to VCC33 voltage through external 8.2 KΩ

resistors.

Pull-up for both internal and external arbiter mode.

Secondary GNT#

S_GNT1#,

S_GNT2#,

S_GNT3#,

S_GNT4#,

S_GNT5#,

S_GNT6#,

S_GNT7#,

S_GNT8#

Connect to GNT# input of the PCI devices on the

secondary PCI bus.

NC when not used.

Table 5. Pull-Up/Pull-Down Terminations (Sheet 2 of 9)

Signal Pull-Up/Pull-Down or Termination (See Note 1) Comments

NOTES:

1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V

signaling R

MIN

=2.42KΩ, R

TYP

=8.2KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value

is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3. For plug-in card implementations, the pull-up must be on the motherboard.

4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or

0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in

Section 8.2 on page 58

.

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Intel 31154 User manual

Intel 31154 User manual

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