NXP MCF51Qx Reference guide

MCF51QM128 Reference Manual

Supports the MCF51QM32, MCF51QM64, and MCF51QM128

Document Number: MCF51QM128RM

Rev. 4, 08/2012

MCF51QM128 Reference Manual, Rev. 4, 08/2012

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................57

1.1.1 Purpose...........................................................................................................................................................57

1.1.2 Audience........................................................................................................................................................57

1.2 Conventions..................................................................................................................................................................57

1.2.1 Numbering systems........................................................................................................................................57

1.2.2 Typographic notation.....................................................................................................................................58

1.2.3 Special terms..................................................................................................................................................58

1.2.4 Register reset..................................................................................................................................................59

Chapter 2

Introduction

2.1 ColdFire+ Portfolio Introduction..................................................................................................................................61

2.2 MCF51QM128 Block Diagram....................................................................................................................................62

2.3 MCF51QM Feature Summary......................................................................................................................................63

2.4 MCF51QM Features by Package..................................................................................................................................67

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................69

3.2 Module to Module Interaction Summary......................................................................................................................69

3.3 Core modules................................................................................................................................................................71

3.3.1 Version 1 (V1) ColdFire Core Configuration................................................................................................71

3.3.2 Debug Configuration......................................................................................................................................71

3.3.2.1 VREG in BDM...........................................................................................................................72

3.4 System modules............................................................................................................................................................72

3.4.1 Crossbar Switch Configuration......................................................................................................................72

3.4.1.1 Crossbar Switch Master Assignments........................................................................................73

3.4.1.2 Crossbar Switch Slave Assignments..........................................................................................74

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3.4.2 Peripheral Bridge Configuration....................................................................................................................74

3.4.2.1 Peripheral bridge interfaces.......................................................................................................74

3.4.2.2 Memory map and module register access..................................................................................75

3.4.3 DMA Controller Configuration.....................................................................................................................75

3.4.3.1 DMA Request Sources...............................................................................................................75

3.4.4 Interrupt Controller (INTC) Configuration....................................................................................................76

3.4.4.1 Interrupt priority levels..............................................................................................................77

3.4.4.2 Interrupt channel assignments....................................................................................................77

3.4.5 Low-Leakage Wakeup Unit (LLWU) Configuration....................................................................................79

3.4.5.1 LLWU wakeup sources..............................................................................................................80

3.4.5.2 Reset due to LLWU wakeup event............................................................................................81

3.4.5.3 LLWU register reset...................................................................................................................81

3.4.6 Computer Operating Properly (COP) Watchdog Configuration....................................................................82

3.4.6.1 COP clocks.................................................................................................................................82

3.4.6.2 COP watchdog operation...........................................................................................................82

3.4.7 System Mode Controller (SMC) Configuration.............................................................................................84

3.4.7.1 SMC register reset......................................................................................................................84

3.4.8 Power Management Controller (PMC) Configuration...................................................................................85

3.4.8.1 PMC register reset......................................................................................................................85

3.4.9 Reset Control Module (RCM) Configuration................................................................................................85

3.4.9.1 RCM register reset.....................................................................................................................86

3.4.10 Voltage Regulator (VREG) Configuration....................................................................................................86

3.4.10.1 VREG operation controls...........................................................................................................87

3.4.10.2 VREG in BDM...........................................................................................................................87

3.4.11 System Integration Module (SIM) Configuration..........................................................................................87

3.4.11.1 SIM register reset.......................................................................................................................88

3.5 Clock Modules..............................................................................................................................................................88

3.5.1 Multipurpose Clock Generator (MCG) Configuration..................................................................................88

3.5.1.1 MCG oscillator-frequency trim settings: factory and custom....................................................89

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3.5.2 Oscillator (OSC) Configuration.....................................................................................................................90

3.6 Memories and Memory Interfaces................................................................................................................................91

3.6.1 RAM Configuration.......................................................................................................................................91

3.6.1.1 RAM overview...........................................................................................................................91

3.6.1.2 RAM sizes..................................................................................................................................91

3.6.1.3 RAM retention in low power modes..........................................................................................92

3.6.1.4 RAM accesses............................................................................................................................92

3.6.2 Flash Memory Controller (FMC) Configuration...........................................................................................92

3.6.3 Flash Memory Module (FTFL) Configuration..............................................................................................93

3.6.3.1 Flash Memory Types.................................................................................................................94

3.6.3.2 Flash Memory Sizes...................................................................................................................94

3.6.3.3 Flash Memory Map....................................................................................................................95

3.6.3.4 Flash Security.............................................................................................................................96

3.6.3.5 Flash Modes...............................................................................................................................96

3.6.3.6 Erase All Flash Contents............................................................................................................96

3.6.3.7 FTFL_FOPT Register................................................................................................................96

3.6.4 System Register File Configuration...............................................................................................................96

3.6.4.1 Register file details.....................................................................................................................97

3.6.5 EzPort Configuration.....................................................................................................................................97

3.6.5.1 EzPort and BDM........................................................................................................................98

3.6.5.2 Flash Option Register (FOPT)...................................................................................................98

3.6.5.3 EzPort Clocking.........................................................................................................................98

3.6.6 Mini-FlexBus Configuration..........................................................................................................................99

3.6.6.1 Mini-FlexBus instantiation information.....................................................................................99

3.6.6.2 Mini-FlexBus CSCR0 reset value..............................................................................................100

3.6.6.3 Mini-FlexBus security................................................................................................................100

3.7 Security.........................................................................................................................................................................100

3.7.1 Cryptographic Acceleration Unit (CAU) Configuration...............................................................................100

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3.7.2 Random Number Generator (RNG) Configuration.......................................................................................101

3.7.2.1 Module register width and serialization of accesses..................................................................101

3.7.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................102

3.7.3.1 Module register width and serialization of accesses..................................................................102

3.8 Analog...........................................................................................................................................................................102

3.8.1 16-bit Analog-to-Digital Converter (ADC) Configuration............................................................................102

3.8.1.1 Module register width and serialization of accesses..................................................................103

3.8.1.2 ADC instantiation information...................................................................................................103

3.8.1.3 DMA support on ADC...............................................................................................................103

3.8.1.4 ADC0 Channel Assignments.....................................................................................................104

3.8.1.5 ADC Reference, Triggers, and Alternate Clock........................................................................105

3.8.1.6 Clock Gating..............................................................................................................................105

3.8.2 Comparator (CMP) Configuration.................................................................................................................106

3.8.2.1 CMP instantiation information...................................................................................................106

3.8.2.2 External window/sample input...................................................................................................107

3.8.3 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................108

3.8.3.1 12-bit DAC Overview................................................................................................................108

3.8.3.2 12-bit DAC Instantiation............................................................................................................108

3.8.3.3 12-bit DAC Reference...............................................................................................................108

3.8.3.4 DAC DMA request ...................................................................................................................109

3.8.4 Voltage Reference (VREF) Configuration....................................................................................................109

3.8.4.1 VREF Overview.........................................................................................................................109

3.9 Timers...........................................................................................................................................................................110

3.9.1 Programmable Delay Block (PDB) Configuration........................................................................................110

3.9.1.1 Module register width and serialization of accesses..................................................................110

3.9.1.2 PDB Overview...........................................................................................................................111

3.9.1.3 PDB instantiation.......................................................................................................................111

3.9.1.4 PDB Module Interconnections...................................................................................................111

3.9.1.5 PDB acknowledgement connections..........................................................................................112

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3.9.1.6 PDB Interval Trigger Connection to DAC................................................................................112

3.9.1.7 DAC External Trigger Input Connection...................................................................................112

3.9.1.8 Pulse-Out Connection................................................................................................................112

3.9.1.9 Pulse-Out Enable Register Implementation...............................................................................112

3.9.2 FlexTimer (FTM) Configuration...................................................................................................................113

3.9.2.1 FTM overview............................................................................................................................113

3.9.2.2 FTM instantiation information...................................................................................................113

3.9.2.3 FTM external clock options.......................................................................................................115

3.9.3 Modulo Timer (MTIM) Configuration..........................................................................................................115

3.9.3.1 MTIM overview.........................................................................................................................115

3.9.4 Low Power Timer (LPTMR) Configuration..................................................................................................116

3.9.4.1 LPTMR overview......................................................................................................................116

3.9.4.2 LPTMR pin connections............................................................................................................117

3.9.4.3 LPTMR clock options................................................................................................................117

3.9.4.4 LPTMR register reset.................................................................................................................117

3.9.5 Carrier Modulator Transmitter (CMT) Configuration...................................................................................118

3.9.5.1 CMT instantiation information..................................................................................................118

3.9.5.2 CMT IRO drive strength............................................................................................................118

3.10 Communication interfaces............................................................................................................................................119

3.10.1 Serial Peripheral Interface (SPI) Configuration.............................................................................................119

3.10.1.1 Number and instantiation of SPI modules.................................................................................119

3.10.1.2 SPI baud rate..............................................................................................................................119

3.10.2 Inter-Integrated Circuit (I2C) Configuration.................................................................................................120

3.10.2.1 Number of I2C modules.............................................................................................................120

3.10.3 Universal Asynchronous Receiver/Transmitter (UART) Configuration.......................................................121

3.10.3.1 UART instances.........................................................................................................................121

3.10.3.2 UART wakeup...........................................................................................................................121

3.10.3.3 UART support for opto-isolated interface.................................................................................121

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3.11 Human-machine interfaces (HMI)................................................................................................................................122

3.11.1 Rapid GPIO (RGPIO) Configuration.............................................................................................................122

3.11.1.1 Number of available RGPIO pins..............................................................................................122

3.11.1.2 RGPIO clock gating...................................................................................................................123

3.11.2 Enhanced GPIO (EGPIO) Configuration.......................................................................................................123

3.11.2.1 Instantiation Information............................................................................................................123

3.11.2.2 EGPIO registers.........................................................................................................................124

3.11.3 Touch Sense Input (TSI) Configuration.........................................................................................................124

3.11.3.1 Module register width and serialization of accesses..................................................................125

3.11.3.2 Number and instantiation of inputs............................................................................................125

3.11.3.3 TSI clock names.........................................................................................................................125

3.11.3.4 TSI module functionality in MCU operation modes.................................................................125

3.11.3.5 TSI Interrupts.............................................................................................................................126

3.11.4 External Interrupt (IRQ) Module Configuration............................................................................................126

Chapter 4

Memory Map

4.1 System Memory Map....................................................................................................................................................129

4.2 Read-after-write sequence and required serialization of memory operations..............................................................134

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................135

5.2 Clock distribution.........................................................................................................................................................135

5.2.1 High-Level device clocking diagram.............................................................................................................135

5.2.2 Device Clock Summary.................................................................................................................................136

5.2.3 Architecture....................................................................................................................................................138

5.2.4 Clock divider requirements............................................................................................................................138

5.2.5 Clock gating...................................................................................................................................................139

5.2.6 Module clocks................................................................................................................................................139

5.2.6.1 VLPR Mode Clocking...............................................................................................................140

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5.2.6.2 UART Clocking.........................................................................................................................140

5.2.6.3 PMC's LPO clock.......................................................................................................................141

Chapter 6

Reset and Boot

6.1 Reset..............................................................................................................................................................................143

6.1.1 MCU reset sources.........................................................................................................................................143

6.1.1.1 Power-on reset (POR)................................................................................................................144

6.1.1.2 External RESET pin (PIN).........................................................................................................144

6.1.1.3 COP watchdog (WDOG) timer..................................................................................................145

6.1.1.4 Illegal opcode detect (ILOP)......................................................................................................145

6.1.1.5 Illegal address detect (ILAD).....................................................................................................145

6.1.1.6 Multipurpose Clock Generator loss of clock (LOC)..................................................................146

6.1.1.7 Low voltage detect (LVD).........................................................................................................146

6.1.1.8 Low leakage wakeup (WAKEUP).............................................................................................146

6.1.1.9 Stop mode acknowledge error (SACKERR) ............................................................................147

6.1.1.10 Background debug forced reset (BDFR)...................................................................................147

6.1.2 Reset Pin .......................................................................................................................................................147

6.1.3 MCU Resets...................................................................................................................................................148

6.1.3.1 POR Only ..................................................................................................................................148

6.1.3.2 Chip POR not VLLS .................................................................................................................148

6.1.3.3 Chip POR ..................................................................................................................................148

6.1.3.4 Chip Reset not VLLS ................................................................................................................148

6.1.3.5 Early Chip Reset .......................................................................................................................148

6.1.3.6 Chip Reset .................................................................................................................................149

6.2 Boot...............................................................................................................................................................................149

6.2.1 Boot sources...................................................................................................................................................149

6.2.2 Boot options...................................................................................................................................................149

6.2.3 FOPT boot options.........................................................................................................................................150

6.2.4 Boot sequence................................................................................................................................................151

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Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................153

7.2 Power modes.................................................................................................................................................................153

7.3 Module Operation in Low Power Modes......................................................................................................................154

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................159

8.2 Flash Security...............................................................................................................................................................159

8.3 Flash Security Options..................................................................................................................................................160

8.3.1 Backdoor Key Access....................................................................................................................................160

8.3.2 Freescale Factory Access...............................................................................................................................160

8.3.3 Mass Erase Disable........................................................................................................................................161

8.4 Enabling Flash Security................................................................................................................................................161

8.5 Unsecuring the MCU using Backdoor Key Access......................................................................................................162

8.6 Unsecuring the MCU using the Erase All Blocks command........................................................................................163

8.7 Security Interactions with other Modules.....................................................................................................................163

8.7.1 Security interactions with Mini-FlexBus.......................................................................................................163

8.7.2 Security interactions with EzPort...................................................................................................................163

8.7.3 Security interactions with Debug...................................................................................................................164

Chapter 9

Signal Multiplexing and Signal Descriptions

9.1 Introduction...................................................................................................................................................................165

9.2 Signal Multiplexing Integration....................................................................................................................................165

9.3 Port Mux Control Features............................................................................................................................................166

9.4 Signal Multiplexing and Pin Assignments....................................................................................................................167

9.5 Pinout diagrams............................................................................................................................................................170

9.6 Module-by-module signals...........................................................................................................................................174

9.7 Module Signal Description Tables................................................................................................................................183

9.7.1 Core Modules.................................................................................................................................................183

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9.7.2 System Modules.............................................................................................................................................183

9.7.3 Clock Modules...............................................................................................................................................184

9.7.4 Memories and Memory Interfaces.................................................................................................................184

9.7.5 Analog............................................................................................................................................................186

9.7.6 Timer Modules...............................................................................................................................................186

9.7.7 Communication Interfaces.............................................................................................................................188

9.7.8 Human-Machine Interfaces (HMI)................................................................................................................189

Chapter 10

Port Mux Control

10.1 Port Mux Control..........................................................................................................................................................191

10.2 Memory Map and Registers..........................................................................................................................................191

10.2.1 Port A Pin Function 1 Register (MXC_PTAPF1).........................................................................................192

10.2.2 Port A Pin Function 2 Register (MXC_PTAPF2).........................................................................................193

10.2.3 Port A Pin Function 3 Register (MXC_PTAPF3).........................................................................................194

10.2.4 Port A Pin Function 4 Register (MXC_PTAPF4).........................................................................................194

10.2.5 Port B Pin Function 1 Register (MXC_PTBPF1)..........................................................................................195

10.2.6 Port B Pin Function 2 Register (MXC_PTBPF2)..........................................................................................196

10.2.7 Port B Pin Function 3 Register (MXC_PTBPF3)..........................................................................................197

10.2.8 Port B Pin Function 4 Register (MXC_PTBPF4)..........................................................................................197

10.2.9 Port C Pin Function 1 Register (MXC_PTCPF1)..........................................................................................198

10.2.10 Port C Pin Function 2 Register (MXC_PTCPF2)..........................................................................................199

10.2.11 Port C Pin Function 3 Register (MXC_PTCPF3)..........................................................................................200

10.2.12 Port C Pin Function 4 Register (MXC_PTCPF4)..........................................................................................200

10.2.13 Port D Pin Function 1 Register (MXC_PTDPF1).........................................................................................201

10.2.14 Port D Pin Function 2 Register (MXC_PTDPF2).........................................................................................202

10.2.15 Port D Pin Function 3 Register (MXC_PTDPF3).........................................................................................203

10.2.16 Port D Pin Function 4 Register (MXC_PTDPF4).........................................................................................203

10.2.17 Port E Pin Function 1 Register (MXC_PTEPF1)..........................................................................................204

10.2.18 Port E Pin Function 2 Register (MXC_PTEPF2)..........................................................................................205

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10.2.19 Port E Pin Function 3 Register (MXC_PTEPF3)..........................................................................................206

10.2.20 Port E Pin Function 4 Register (MXC_PTEPF4)..........................................................................................206

10.2.21 Port F Pin Function 1 Register (MXC_PTFPF1)...........................................................................................207

10.2.22 Port F Pin Function 2 Register (MXC_PTFPF2)...........................................................................................208

10.2.23 Port F Pin Function 3 Register (MXC_PTFPF3)...........................................................................................209

10.2.24 Port F Pin Function 4 Register (MXC_PTFPF4)...........................................................................................209

Chapter 11

Core

11.1 Introduction...................................................................................................................................................................211

11.1.1 Overview........................................................................................................................................................211

11.2 Memory Map/Register Description..............................................................................................................................213

11.2.1 Data registers (D0–D7)..................................................................................................................................215

11.2.2 Address registers (A0–A6).............................................................................................................................216

11.2.3 Supervisor/user stack pointers (A7 and OTHER_A7)...................................................................................216

11.2.4 Condition code register (CCR)......................................................................................................................218

11.2.5 Program counter (PC)....................................................................................................................................219

11.2.6 Vector base register (VBR)............................................................................................................................219

11.2.7 CPU configuration register (CPUCR)............................................................................................................220

11.2.8 Status register (SR)........................................................................................................................................223

11.3 Functional Description..................................................................................................................................................224

11.3.1 Instruction Set Architecture...........................................................................................................................224

11.3.2 Exception Processing Overview....................................................................................................................225

11.3.2.1 Exception Stack Frame Definition.............................................................................................228

11.3.2.2 S08 and ColdFire Exception Processing Comparison...............................................................229

11.3.3 Processor Exceptions.....................................................................................................................................230

11.3.3.1 Access Error Exception..............................................................................................................230

11.3.3.2 Address Error Exception............................................................................................................231

11.3.3.3 Illegal Instruction Exception......................................................................................................232

11.3.3.4 Divide-By-Zero..........................................................................................................................233

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11.3.3.5 Privilege Violation.....................................................................................................................233

11.3.3.6 Trace Exception.........................................................................................................................234

11.3.3.7 Unimplemented Line-A Opcode................................................................................................234

11.3.3.8 Unimplemented Line-F Opcode.................................................................................................235

11.3.3.9 Debug Interrupt .........................................................................................................................235

11.3.3.10 RTE and Format Error Exception .............................................................................................235

11.3.3.11 TRAP Instruction Exception......................................................................................................236

11.3.3.12 Unsupported Instruction Exception...........................................................................................236

11.3.3.13 Interrupt Exception....................................................................................................................236

11.3.3.14 Fault-on-Fault Halt.....................................................................................................................236

11.3.3.15 Reset Exception..........................................................................................................................237

11.3.4 Instruction Execution Timing........................................................................................................................240

11.3.4.1 Timing Assumptions..................................................................................................................240

11.3.4.2 MOVE Instruction Execution Times.........................................................................................241

11.3.4.3 Standard One Operand Instruction Execution Times................................................................242

11.3.4.4 Standard Two Operand Instruction Execution Times................................................................243

11.3.4.5 Miscellaneous Instruction Execution Times..............................................................................244

11.3.4.6 EMAC Instruction Execution Times..........................................................................................245

11.3.4.7 Branch Instruction Execution Times..........................................................................................247

Chapter 12

Enhanced Multiply-Accumulate Unit (EMAC)

12.1 Introduction...................................................................................................................................................................249

12.1.1 Overview........................................................................................................................................................249

12.1.1.1 Introduction to the MAC............................................................................................................250

12.2 Memory Map/Register Definition.................................................................................................................................251

12.2.1 MAC Status Register (MACSR)....................................................................................................................252

12.2.2 Mask Register (MASK).................................................................................................................................254

12.2.3 Accumulator Registers (ACC0-3)..................................................................................................................256

12.2.4 Accumulator Extension Registers (ACCext01, ACCext23)..........................................................................257

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12.3 Functional Description..................................................................................................................................................258

12.3.1 Fractional Operation Mode............................................................................................................................260

12.3.1.1 Rounding....................................................................................................................................261

12.3.1.2 Saving and Restoring the EMAC Programming Model............................................................262

12.3.1.3 MULS/MULU............................................................................................................................263

12.3.1.4 Scale Factor in MAC or MSAC Instructions.............................................................................263

12.3.2 EMAC Instruction Set Summary...................................................................................................................263

12.3.3 EMAC Instruction Execution Times..............................................................................................................264

12.3.4 Data Representation.......................................................................................................................................265

12.3.5 MAC Opcodes................................................................................................................................................265

Chapter 13

System Integration Module (SIM)

13.1 Introduction...................................................................................................................................................................271

13.2 Memory Map and Registers..........................................................................................................................................271

13.2.1 System Options Register 1 (SIM_SOPT1)....................................................................................................273

13.2.2 System Options Register 2 (SIM_SOPT2)....................................................................................................274

13.2.3 System Options Register 3 (SIM_SOPT3)....................................................................................................275

13.2.4 System Options Register 4 (SIM_SOPT4)....................................................................................................276

13.2.5 System Options Register 5 (SIM_SOPT5)....................................................................................................277

13.2.6 System Options Register 6 (SIM_SOPT6)....................................................................................................277

13.2.7 System Options Register 7 (SIM_SOPT7)....................................................................................................278

13.2.8 COP Control Register (SIM_COPC).............................................................................................................279

13.2.9 Service COP Register (SIM_SRVCOP)........................................................................................................280

13.2.10 Oscillator 1 Control Register (SIM_OSC1)...................................................................................................281

13.2.11 Device Identification High Register (SIM_SDIDH).....................................................................................282

13.2.12 Device Identification Low Register (SIM_SDIDL).......................................................................................282

13.2.13 Clock Gate Control Register 1 (SIM_SCGC1)..............................................................................................283

13.2.14 Clock Gate Control Register 2 (SIM_SCGC2)..............................................................................................284

13.2.15 Clock Gate Control Register 3 (SIM_SCGC3)..............................................................................................285

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13.2.16 Clock Gate Control Register 4 (SIM_SCGC4)..............................................................................................286

13.2.17 Clock Gate Control Register 5 (SIM_SCGC5)..............................................................................................287

13.2.18 Clock Gate Control Register 6 (SIM_SCGC6)..............................................................................................288

13.2.19 Clockout Register (SIM_CLKOUT)..............................................................................................................289

13.2.20 Clock Divider 0 Register (SIM_CLKDIV0)..................................................................................................290

13.2.21 Flash Configuration Register (SIM_SPCR)...................................................................................................291

13.2.22 Unique Identification Register (SIM_UIDH3)..............................................................................................292

13.2.23 Unique Identification Register (SIM_UIDH2)..............................................................................................293

13.2.24 Unique Identification Register (SIM_UIDH1)..............................................................................................294

13.2.25 Unique Identification Register (SIM_UIDH0)..............................................................................................294

13.2.26 Unique Identification Register (SIM_UIDMH3)...........................................................................................295

13.2.27 Unique Identification Register (SIM_UIDMH2)...........................................................................................296

13.2.28 Unique Identification Register (SIM_UIDMH1)...........................................................................................296

13.2.29 Unique Identification Register (SIM_UIDMH0)...........................................................................................297

13.2.30 Unique Identification Register (SIM_UIDML3)...........................................................................................298

13.2.31 Unique Identification Register (SIM_UIDML2)...........................................................................................298

13.2.32 Unique Identification Register (SIM_UIDML1)...........................................................................................299

13.2.33 Unique Identification Register (SIM_UIDML0)...........................................................................................300

13.2.34 Unique Identification Register (SIM_UIDL3)...............................................................................................300

13.2.35 Unique Identification Register (SIM_UIDL2)...............................................................................................301

13.2.36 Unique Identification Register (SIM_UIDL1)...............................................................................................302

13.2.37 Unique Identification Register (SIM_UIDL0)...............................................................................................302

Chapter 14

Crossbar Switch

14.1 Introduction...................................................................................................................................................................305

14.1.1 Features..........................................................................................................................................................305

14.2 Memory Map / Register Definition...............................................................................................................................306

14.3 Functional Description..................................................................................................................................................306

14.3.1 General operation...........................................................................................................................................306

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14.3.2 Arbitration......................................................................................................................................................307

14.3.2.1 Arbitration During Undefined Length Bursts............................................................................307

14.3.2.2 Fixed-priority operation.............................................................................................................307

14.3.2.3 Round-robin priority operation..................................................................................................308

14.3.2.4 Priority Elevation.......................................................................................................................308

14.4 Initialization/application information...........................................................................................................................309

Chapter 15

Interrupt Controller (INTC)

15.1 Introduction...................................................................................................................................................................311

15.1.1 Overview........................................................................................................................................................312

15.1.2 Features..........................................................................................................................................................315

15.1.3 Modes of Operation.......................................................................................................................................316

15.2 External Signal Description..........................................................................................................................................316

15.3 Interrupt Request Level and Priority Assignments.......................................................................................................316

15.4 Memory Map and Registers..........................................................................................................................................317

15.4.1 Interrupt Mask Register High (INTC_IMRH)...............................................................................................318

15.4.2 Interrupt Mask Register Low (INTC_IMRL)................................................................................................320

15.4.3 Force Interrupt Register (INTC_FRC)...........................................................................................................324

15.4.4 INTC Programmable Level 6 Priority Registers (INTC_PL6Pn)..................................................................325

15.4.5 INTC Wakeup Control Register (INTC_WCR)............................................................................................326

15.4.6 Set Interrupt Mask Register (INTC_SIMR)...................................................................................................327

15.4.7 Clear Interrupt Mask Register (INTC_CIMR)...............................................................................................328

15.4.8 INTC Set Interrupt Force Register (INTC_SFRC)........................................................................................329

15.4.9 INTC Clear Interrupt Force Register (INTC_CFRC)....................................................................................330

15.4.10 INTC Software IACK Register (INTC_SWIACK).......................................................................................331

15.4.11 INTC Level-n IACK Registers (INTC_LVLnIACK)....................................................................................331

15.5 Functional Description..................................................................................................................................................332

15.5.1 Handling of Non-Maskable Level 7 Interrupt Requests................................................................................332

15.6 Initialization Information..............................................................................................................................................333

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15.7 Application Information................................................................................................................................................333

15.7.1 Emulation of the HCS08's 1-Level IRQ Handling.........................................................................................333

15.7.2 Using INTC_PL6P{7,6} Registers................................................................................................................334

15.7.3 More on Software IACKs..............................................................................................................................335

Chapter 16

Low Leakage Wakeup Unit (LLWU)

16.1 Introduction...................................................................................................................................................................339

16.1.1 Features..........................................................................................................................................................339

16.1.2 Modes of operation........................................................................................................................................340

16.1.2.1 LLS mode...................................................................................................................................340

16.1.2.2 VLLS modes..............................................................................................................................340

16.1.2.3 Non-low leakage modes.............................................................................................................340

16.1.2.4 Debug mode...............................................................................................................................341

16.1.3 Block diagram................................................................................................................................................341

16.2 LLWU signal descriptions............................................................................................................................................342

16.3 Memory map/register definition...................................................................................................................................343

16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................344

16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................345

16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................346

16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................347

16.3.5 LLWU Module Enable register (LLWU_ME)..............................................................................................348

16.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................350

16.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................351

16.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................353

16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................355

16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................356

16.3.11 LLWU Reset Enable register (LLWU_RST).................................................................................................357

16.4 Functional description...................................................................................................................................................358

16.4.1 LLS mode.......................................................................................................................................................358

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16.4.2 VLLS modes..................................................................................................................................................358

16.4.3 Initialization...................................................................................................................................................359

Chapter 17

Reset Control Module (RCM)

17.1 Introduction...................................................................................................................................................................361

17.2 Reset memory map and register descriptions...............................................................................................................361

17.2.1 System Reset Status Register 0 (RCM_SRS0)..............................................................................................361

17.2.2 System Reset Status Register 1 (RCM_SRS1)..............................................................................................363

17.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................364

17.2.4 Reset Pin Filter Width register (RCM_RPFW).............................................................................................365

17.2.5 Mode Register (RCM_MR)...........................................................................................................................367

Chapter 18

System Mode Controller (SMC)

18.1 Introduction...................................................................................................................................................................369

18.2 Modes of operation.......................................................................................................................................................369

18.3 Memory map and register descriptions.........................................................................................................................371

18.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................371

18.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................372

18.3.3 VLLS Control register (SMC_VLLSCTRL).................................................................................................374

18.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................375

18.4 Functional description...................................................................................................................................................376

18.4.1 Power mode transitions..................................................................................................................................376

18.4.2 Power mode entry/exit sequencing................................................................................................................379

18.4.2.1 Stop mode entry sequence..........................................................................................................380

18.4.2.2 Stop mode exit sequence............................................................................................................381

18.4.2.3 Aborted stop mode entry............................................................................................................381

18.4.2.4 Transition to wait modes............................................................................................................381

18.4.2.5 Transition from stop modes to Debug mode..............................................................................381

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18.4.3 Run modes......................................................................................................................................................381

18.4.3.1 RUN mode.................................................................................................................................382

18.4.3.2 Very-Low Power Run (VLPR) mode........................................................................................382

18.4.3.3 BDM in Run and VLPR Mode..................................................................................................383

18.4.4 Wait modes....................................................................................................................................................383

18.4.4.1 WAIT mode...............................................................................................................................383

18.4.4.2 Very-Low-Power Wait (VLPW) mode......................................................................................384

18.4.4.3 BDM in Wait and VLPW Mode................................................................................................384

18.4.5 Stop modes.....................................................................................................................................................385

18.4.5.1 STOP mode................................................................................................................................385

18.4.5.2 Very-Low-Power Stop (VLPS) mode........................................................................................386

18.4.5.3 BDM in Stop and VLPS Modes.................................................................................................386

18.4.5.4 Low-Leakage Stop (LLS) mode................................................................................................387

18.4.5.5 Very-Low-Leakage Stop (VLLSx) modes.................................................................................387

18.4.5.6 BDM in LLS and VLLSx Modes...............................................................................................388

Chapter 19

Power Management Controller (PMC)

19.1 Introduction...................................................................................................................................................................389

19.2 Features.........................................................................................................................................................................389

19.3 Low-voltage detect (LVD) system................................................................................................................................389

19.3.1 LVD reset operation.......................................................................................................................................390

19.3.2 LVD interrupt operation.................................................................................................................................390

19.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................390

19.4 I/O retention..................................................................................................................................................................391

19.5 Memory map and register descriptions.........................................................................................................................391

19.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................391

19.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................393

19.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................394

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Chapter 20

Voltage Regulator (VREG)

20.1 Introduction...................................................................................................................................................................397

20.1.1 Overview........................................................................................................................................................397

20.1.2 Features..........................................................................................................................................................398

20.1.3 Modes of Operation.......................................................................................................................................399

20.2 Voltage Regulator Module Signal Descriptions...........................................................................................................399

Chapter 21

DMA Controller

21.1 Introduction...................................................................................................................................................................401

21.1.1 Overview........................................................................................................................................................401

21.1.2 Features..........................................................................................................................................................402

21.2 DMA Transfer Overview..............................................................................................................................................403

21.3 Memory Map and Registers..........................................................................................................................................404

21.3.1 DMA Request Control Register (DMA_REQC)...........................................................................................405

21.3.2 Source Address Register (DMA_SARn).......................................................................................................409

21.3.3 Destination Address Register (DMA_DARn)...............................................................................................410

21.3.4 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................410

21.3.5 DMA Control Register (DMA_DCRn)..........................................................................................................413

21.4 Functional Description..................................................................................................................................................416

21.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)..............................................................................417

21.4.2 Channel Initialization and Startup..................................................................................................................417

21.4.2.1 Channel Prioritization................................................................................................................417

21.4.2.2 Programming the DMA Controller Module...............................................................................418

21.4.3 Dual-Address Data Transfer Mode................................................................................................................419

21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................420

21.4.5 Termination....................................................................................................................................................421

MCF51QM128 Reference Manual, Rev. 4, 08/2012

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