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MANUAL
PTP270PEX
IEEE 1588 Computer Clock
1 Impressum
2 General information
2.1 Content of the USB stick
2.2 Mode of operation
2.3 Features PTP270PEX
2.4 Pulse and frequency outputs
2.5 Time capture inputs
2.6 Asynchronous serial port
2.7 Block Diagram PTP270PEX
PCI Express
Interface
time stamp unit
(TSU)
MAC
FPGA
PHY
RJ45
with
magnetics
input signals
time capture,...
output signals
signal generator
PCI Express Bus
register set
single board
computer (SBC)
running PTP stack
microcontroller
reference oscillator
O(T)CXO
Tx Rx CLK
16-bit local bus
MII interface
Host bus
USB
PCI-IntTSU-Int
MAC-Int
3 Precision Time Protocol (PTP) / IEEE1588
3.1 General Information
10/100MBit
LAN
Network Interface Card
PTP Time Stamp Unit
Single Board Computer
PTP Protocol Stack
Reference Time Source
GPS Receiver
PTP Master System only
USB
PPS10MHz
3.2 Functionality in Master Systems
10/100MBit
LAN
10 Mhz from GPS
RJ45 with
magnetics
and LEDs
PHYceiver
MAC
controller
USB hub
FPGA
microcontroller
with integrated
progr. memory
10M/activity
100M/activity
Rx/Tx
MII interface
USB
USB 1.1
to computer
module
Time Stamp Unit PTP Master
FPGA
configuration
memory
PPS from GPS
control
adr/data
control
data
USB
3.3 Functionality in Slave Systems
10/100MBit
LAN
10 MHz
PPS
programmable
outputs
modulated
time code
RJ45 with
magnetics
and LEDs
PHYceiver
MAC
controller
USB hub
status LEDs
driver
circuits
FPGA
filter and
driver circuit
oscillator
DAC
microcontroller
with integrated
progr. memory
FPGA
configuration
memory
10M/activity
100M/activity
Rx/Tx
MII interface
USB
USB
data control
control
control
voltage
PWM time code
clock
adr/data
control
USB 1.1
to computer
module
clock
status
Time Stamp Unit PTP Slave
3.4 PTPv2 IEEE 1588-2008 Configuration Guide
3.4.1 General Options
3.4.2 Network Layer 2 or Layer 3
3.4.3 Multicast or Unicast
3.4.4 Two-Step or One-Step
3.4.5 End-To-End (E2E) or Peer-To-Peer (P2P) Delay Measurements
3.4.6 Mode Recommendations
3.4.7 Message Rate Settings
3.4.8 ANNOUNCE Messages
3.4.9 SYNC/FOLLOWUP Messages
3.4.10 (P)DELAY REQUEST Messages
3.4.11 HQ Filter
4 PCI Express (PCIe)
Selectable Width
Device A
Device B
Ref. Clock Ref. Clock
TX
Logic
D+
Component A Component B
D+
VBIAS
VBIAS
D-
D-
RX
Logic
RX
Logic
TX
Logic
Interoperability
Slot x1 x4 x8 x16
Card
x1 Yes Yes Yes Yes
x4 No Yes Yes Yes
x8 No No Yes Yes
X16 No No No Yes
5 Mounting and Configuration of the PTP card
5.1 Configuring the 9 pin connector
5.2 Installing PTP270PEX in your computer
7 Time codes
7.1 The time code generator
7.2 Generated Time Codes
7.3 IRIG Standard Format
7.4 AFNOR Standard Format
7.5 Assignment of CF Segment in IEEE1344 Code
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