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MiTAC Mio336i User manual

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SERVICE MANUAL FOR
Mio336i
Mio336iMio336i
Mio336i
SERVICE MANUAL FOR
SERVICE MANUAL FOR
Mio336i
Mio336iMio336i
Mio336i
Mio336i
Mio336iMio336i
Mio336i
BY:
Sissel Diao
Sissel Diao
Repair Technology Research Department /EDVD
Repair Technology Research Department /EDVD
Nov. 2003
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Contents
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1. Hardware Engineering Specification ---------------------------------------------------------------------------
1.1 Overview ----------------------------------------------------------------------------------------------------------------------------
1.2 System Configuration -------------------------------------------------------------------------------------------------------------
1.3 Main System ------------------------------------------------------------------------------------------------------------------------
1.4 Lithium Ion Rechargeable Battery (CGA523450, Panasonic) ------------------------------------------------------------
1.5 GPIO Table -------------------------------------------------------------------------------------------------------------------------
2. System View and Disassembly -----------------------------------------------------------------------------------
2.1 Tools Introduction -----------------------------------------------------------------------------------------------------------------
2.2 System Views -----------------------------------------------------------------------------------------------------------------------
2.3 System Disassembly ---------------------------------------------------------------------------------------------------------------
3. Definition & Location of Connectors / Major Components -----------------------------------------------
3.1 Main Board -------------------------------------------------------------------------------------------------------------------------
4. Pin Description of Major Components -------------------------------------------------------------------------
4.1 Intel PXA255 (Cotulla) Application Processor -----------------------------------------------------------------------------
5. System Block Diagram ---------------------------------------------------------------------------------------------
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6. Mio336i WinCE Image Upgrade --------------------------------------------------------------------------------
6.1 Burning IPL file & Upgrade tool -----------------------------------------------------------------------------------------------
6.2 Burning WinCE Image file ------------------------------------------------------------------------------------------------------
7. Mio336i Service TPI -----------------------------------------------------------------------------------------------
7.1 Board Function Test --------------------------------------------------------------------------------------------------------------
7.2 Run In Test -------------------------------------------------------------------------------------------------------------------------
7.3 D.M. Test Introduction -----------------------------------------------------------------------------------------------------------
8. Trouble Shooting ---------------------------------------------------------------------------------------------------
8.1 No Power ----------------------------------------------------------------------------------------------------------------------------
8.2 LCD No Display --------------------------------------------------------------------------------------------------------------------
8.3 LCD Display Abnormal ----------------------------------------------------------------------------------------------------------
8.4 Memory Test Error ---------------------------------------------------------------------------------------------------------------
8.5 Audio Function Failure -----------------------------------------------------------------------------------------------------------
8.6 Touch Screen Function Failure -------------------------------------------------------------------------------------------------
9. Spare Parts List -----------------------------------------------------------------------------------------------------
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10. System Exploded Views ------------------------------------------------------------------------------------------
11. Circuit Diagram ---------------------------------------------------------------------------------------------------
12. Reference Material ------------------------------------------------------------------------------------------------
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1.1 Overview
This documents descript the electrical functionality of Mio336i which is an embedded system using Intel PXA255
(Cotulla) SOC & Microsoft Pocket PC 2003 system OS. Mio336i is a slim and fashion form-factor with multimedia
capability. It equip with 64K color 320*240 portrait reflective TFT LCD, touch screen input, one stereo audio out
earphone Jack, one microphone and speaker for voice recording and playback, IrDA, RS232, USB, Joy stick and
some s/w application hot keys, SD slot, an Amber/Green color battery charger LED and a Red color Notification
LED.
1. Hardware Engineering Specification
1.2 System Configuration
CPU: Intel PXA255/Cotulla 300MHz
RAM: 64MByte SDRAM (K4S561633C-RL *2)
ROM: 32Mbyte INTEL STRATA FLASH (28F256L30/K3 *1)
Audio Codec: Wolfson WM9705 (AC97 interface)
Audio Amplifier: TI TPA0253
IrDA: ZILOG ZHX1403
UART transceiver: TI MAX3243
LCD Timing controller: SIL50282F23K100 (For NEC panel)
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Panel: NEC NL2432DR22 240*320 TFT Color LCD, build-in Touch Screen/Transflective with LED backlight.
Charger controller: TI BQ24010
Micro-controller : EM78P156ELAS
USB Client => for Window Active sync
Serial Port
IrDA (Compatible with SIR, 115.2Kbps )
SD/MMC
Microphone input (Mono)
Earphone output (Stereo)
Speaker output (Mono)
IO Interface :
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1.3 Main System
1.3.1 Block Diagram
Cradle Conn.
COM port BUS
USB Client
(Max. 12Mbps)
COM1 BUS
IR_TXD
IR_RXD
JTAG
interface
RS-232 Transceiver (ADM3311)
16550-compatible UART
IrDA/Zilog ZHX1403
Compliant to IrDA 1.1
specification
JTAG CONN.
(For debug use)
EEPROM/24LC00
(Option)
Back Light
Controller
MP1521
NEC Timing
Controller
SD/MMC
controller
NEC color TFT
Module
240*320 / 3.5”
LCD control
data bus
LCD bus
Touch Screen bus
Speaker/0.8W
(Mono)
Power amplifier
TPA0253
Earphone Jack
(Stereo)
Audio codec/WM9705
AC’97
interface
2
PWM
BL_ON/OFF#
2
L/R
L/R
L/R
24.576M
XTAL
When earphone inserted, speaker output will be muted.
5
Joystick
Contact
button
Calendar
button
Record
button
Home
button
Task
button
Power
button
Micro Phone
Input (mono)
Host Address Bus
SDRAM @ 103MHz
32Mbyte *2
Intel StrataFlash
28F256L30/K3 *1
Host Data Bus
SD Control
/data bus
Gauge bus
SD/MMC Socket
Extend GPIO
74LCX374
LCD/Panel/Audio
control
Micro controller
EM78P156
3.6864M XTAL
Li-Ion
Battery
930mAH
3.6864M XTAL
32.768K
XTAL
H/W OSC
circuit
Red LED
(for Notification)
Charger
BQ24010
Green LED
(for charger)
Amber LED
(for charger)
DC Adapter-In
(5V)
Intel / PXA255
-300MHz
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Power Structure
Battery
(3.5~4.2V)
930mAH
MOS
Switch
If Adapter plug-in,
The way will be
disconnected
M/E
Switch
Turn ON/OFF all
of system power
VCC_IN
AME8815
VCC_3VSB
Charger
BQ24010
VCC_P+
(5V)
CPU Core – PXA255
VCC_CORE
Can be turned-OFF when
in sleep mode
Amplifier – TPA0253
AMP_5V
These part can be shut-down
when it’s not active
TPS62000
ML4854
MP1521
(Backlight Controller)
These part can be shut-down
when it’s not active
VCC_IN
AAT3110
VCC_+15
VCC_-15
AIC1896
MOS
Switch
VCC_5V
LCD Panel
LCD Timing ASIC
VCC3_LCD
VCC3_LCD
Can be turned-OFF
when display is OFF
Flash --
28F256L30
VCC1.8VSB
MIC5207
Codec – WM9705
Microphone
MOS
Switch
MOS
Switch
VCC_AUD
VCC_3VSB
VCC_IN
VCC_IN
CPU I/O -- PXA255
SDRAM -- K4S561633C
Flash -- 28F256L30/K3
Reset IC -- MIC811
COM Port -- MAX3243
IrDA -- ZHX1403
Micro-P -- EM78P156
EEPROM -- 24LC00
Extend GPIO -- 74LCX374
SD Card
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1.3.2 Main Board
1.3.2.1 CPU : Intel PXA255, 300MHz
The PXA255 applications processors provide high integration, high performance and low power consumption for
portable handheld and handset devices. These applications processors incorporate Intel’s XScaleTM
Microarchitecture based on the ARM* V5TE architecture. The applications processor’s memory interface supports
a variety of memory types that allow flexibility in design requirements. Hooks for connection to two companion
chips permit glueless connection to external devices. An integrated LCD display controller provides support for
displays, and permits 1, 2 and 4 bit grayscale and 8 or 16 bit color pixels. A 256-byte palette RAM provides
flexibility in color mapping. A rich set of serial devices as well as general system resources provide enough
compute and connectivity capability for many applications. For details on the programming model and theory of
operation of each of these units, refer to the Intel® PXA255 and PXA210 Applications Processors Developer's
Manual.
High Performance Processor
- Intel® XScale™ Microarchitecture
- 32 KB Instruction Cache3
- 2 KB Data Cache
- 2 KB “mini” Data Cache
- Extensive Data Buffering
Product Features
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Intel® Media Processing Technology
- Enhanced 16-bit Multiply
- 40-bit Accumulator
Flexible Clocking
- CPU clock from 66 to 300 MHz
- Flexible memory clock ratios
- Frequency change modes
Rich Serial Peripheral Set
- AC97 Audio port
- I2S Audio port
- USB client controller
- High speed UART
- Second UART with flow control
- FIR and SIR infrared comm ports
Low Power
- Less than 500mW typical internal dissipation
- Supply voltage may be reduced to 0.85V
- Low power/Sleep modes
High Performance Memory Controller
- Four Banks of SDRAM – up to 100MHz
- Five Static Chip Selects
- Support for PCMCIA or Compact Flash
- Companion Chip Interface
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Additional Peripherals for System Connectivity
- Multimedia card controller (MMC)
- SSP controller
- I²C controller
- Two Pulse Width Modulators (PWMs)
- All peripheral pins double as GPIOs
Hardware Debug Features
Hardware Performance Monitoring Features
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Voltage, temperature, and frequency Electrical Specifications
MHz99.550External Synchronous Memory Frequency, Peak RangefSDRAM_P
MHz398.299.5Turbo Mode Frequency, Peak RangefTURBO_P
V1.431.301.17VCC, PLL_VCC Voltage, Peak RangeWCC_P
Peak Voltage Range (PXA250)
MHz99.550External Synchronous Memory Frequency, High RangefSDRAM_H
MHz298.799.5Turbo Mode Frequency, High RangefTURBO_H
V1.211.100.99VCC, PLL_VCC Voltage, High RangeWCC_H
High Voltage Range (PXA250)
MHz99.550External Synchronous Memory Frequency, Mid RangefSDRAM_M
MHz199.199.5Turbo Mode Frequency, Mid RangefTURBO_M
V1.101.000.90VCC, PLL_VCC Voltage, Mid RangeWCC_M
Medium Voltage Range (PXA250 and PXA210)
MHz99.550External Synchronous Memory Frequency, Low RangefSDRAM_L
MHz132.799.5Turbo Mode Frequency, Low RangefTURBO_L
V0.9350.850.765VCC, PLL_VCC Voltage, Low RangeWCC_L
Low Voltage Range (PXA250 and PXA210)
V3.62.5/3.32.375VCCN VoltageWCCN
V3.63.33.0VCCQ VoltageWCCQ
V0.30-0.3VSS, VSSN, VSSQ VoltageWSS
ºC70-0Ambient Temperature - Nominal TemptA
ºC85--40Ambient Temperature - Extended TemptA
UnitsMaxTypicalMinDescriptionSymbol
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Note 1: Part number change approved for C1 stepping
PXA250C1 PXA255A0
Note 2: 301-400MHz commercial temperature range is reduced from 0-70C to 0-60C Ta (Ambient Temperature).
Note 3: PXA250 C stepping Core voltage & frequency updated:
1.65
1.43
1.32
1.155
Max
1.3
1.1
1.0
1.0
Typ
998.2
298.7
199.1
118.0
Max
1.23599.5
1.04599.5
0.9599.5
0.9599.5
MinMin
VCC (Volts)Turbo Mode Frequency (MHz)
Voltage and frequency Specifications
Note 1: PXA255 (PXA250 C stepping) ID values updated:
0x692640130x69052D06A0
JTAG IDARM IDStepping
PXA255 ID Values
Package Introduction
The applications processor is offered in the packages: 256-pin mBGA
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1.3.2.2 RAM : Synchronous DRAM (SDRAM)
SAMSUNG 256M-bit (16Mx16) Synchronous DARM
The K4S561633C is 268, 435, 456 bits synchronous high data rate Dynamic RAM organized as 4 x 4, 196, 304
words by 16bits, fabricated with SAMSUNG high performance CMOS technology. Synchronous design allows
precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Description
3.0V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (1& 2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
EMRS cycle with address key programs
All inputs are sampled at the positive going edge of the system clock
DQM for masking
Feature :
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Auto refresh
64ms refresh period (8K cycle)
Commercial Temperature Operation (-25’C ~ 70’C)
Extended Temperature Operation ( -25’C ~ 85’C)
54balls CSP
Package Information :
VDDA2A3A4A5VSSJ
A10A1A0A6A7A8H
CSBA1BA0A9A11A12G
WERASCASCKECLKUDQMF
DQ7LDQMVDDVSSNCDQ8E
DQ5DQ6VSSQVDDQDQ9DQ10D
DQ3DQ4VDDQVSSQDQ11DQ12C
DQ1DQ2VSSQVDDQDQ13DQ14B
VDDDQ0VDDQVSSQDQ15VSSA
219873
54Ball (6x9) CSP
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3uA10--10ILIInput leakage current
V3.63.02.7VDDQ
IOL=2mA
IOH=2mA
2
1
Note
V
V
V
V
V
UnitMaxTypSymbol
0.4
-
0.5
3.6
3.6
-
-
0
3.0
3.0
VOL
VOH
VIL
VIH
VDD
-Output logic low voltage
2.4Output logic high voltage
-0.3Input low voltage
2.2Input logic high voltage
2.7Supply voltage
MinParameter
Recommended operation conditions (Voltage reference to VSS=0V, TA=-25C~70C(Commercial),
-25C~85C (Extended))
Note 1: Pin to pin compatible SDRAM vender & part number:
(1) SAMSUNG K4S561633C-RL(N)
(2) INFINEON HYB39L256160AC
(3) MICRON MT48LC16M16LFFG-
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1.3.2.3 ROM : 32Mbyte INTEL STRATAFLASH , 28f256K3/L30 (options one)
K3 Performance
- 110/115/120 ns Initial Access Speed for 64/128/256Mbit Densities
- 25 ns Asynchronous Page-Mode Reads, 8 Words Wide
- 13 ns Synchronous Burst-Mode Reads, 8 or 16 Words Wide
- 32-Word Write Buffer
- Buffered Enhanced Factory Programming
K3 Architecture
- Multi-Level Cell Technology: High Density at Low Cost
- Symmetrical 64 K-Word Blocks
- 256Mbit (256 Blocks)
- 128Mbit (128 Blocks)
- 64Mbit (64 Blocks)
- Ideal for “CODE + DATA” applications
K3 Packaging and Voltage
- 64-Ball Intel® Easy BGA Package
- 56-and 79-Ball Intel® VF BGA Package
- VCC = 2.70 V – 3.60 V
- VCCQ = 1.65 – 1.95 V or 2.70 V– 3.60 V
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L30 description:
The 1.8 Volt Intel StrataFlash. wireless memory with 3-Volt I/O product is the latest generation of Intel StrataFlash.
memory devices featuring flexible, multiple-partition, dual operation. It provides high performance synchronous-
burst read mode and asynchronous read mode using 1.8 volt low-voltage, multilevel cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition while
code execution or data reads take place in another partition. This dual-operation architecture also allows two
processors to interleave code operations while program and erase operations take place in the background.
The 1.8 Volt Intel StrataFlash. wireless memory with 3-Volt I/O device is manufactured using Intel 0.13 ¦Ìm ETOX.
VIII process technology. It is available in industry-standard chip scale packaging.
L30 High performance Read-While-Write/Erase
- 85 ns initial access
- 52MHz with zero wait state, 17 ns clock-to-data output synchronous-burst mode
- 25 ns asynchronous-page mode
- 4-, 8-, 16-, and continuous-word burst mode
- Burst suspend
- Programmable WAIT configuration
- Buffered Enhanced Factory Programming(Buffered EFP): 3.5 µs/byte (Typ)
- 1.8 V low-power buffered and non-buffered programming @ 10 µs/byte (Typ)
L30 Architecture
- Asymmetrically-blocked architecture
- Multiple 8Mbit partitions: 64Mb and 128Mb devices
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- Multiple 16Mbit partitions: 256Mb devices
- Four 16KWord parameter blocks: top or bottom configurations
- 64K-Word main blocks
- Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE)
- Status register for partition and device status
L30 Power
- 1.7 V - 2.0 V VCC operation
- I/O voltage: 2.2 V - 3.3 V
- Standby current: 30 µA (Typ)
- 4-Word synchronous read current: 17 mA (Typ) @ 54 MHz
L30 Software
- 20 µs (Typ) program suspend
- 20 µs (Typ) erase suspend
- Intel® Flash Data Integrator (FDI) optimized
- Basic Command Set (BCS) and Extended Command Set (ECS) compatible
- Common Flash Interface (CFI) capable
L30 Security
- OTP space:
- 64 unique device identifier bits
- 64 user-programmable OTP bits
- Additional 2048 user-programmable OTP bits
- Absolute write protection: VPP = GND
- Power-transition erase/program lockout
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- Individual zero-latency block locking
- Individual block lock-down
L30 Quality and Reliability
- Expanded temperature: –25 C to +85 C
- Minimum 100,000 erase cycles per block
- ETOX™ VIII process technology (0.13 µm)
L30 Density and Packaging
- 64-, 128- and 256Mbit density in VF BGA packages.
- 128/0, and 256/0 Density in Stacked-CSP
- 16-bit wide data bus
/