MiTAC E - 8188 User manual

SERVICE MANUAL FOR

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-8188

81888188

8188

SERVICE MANUAL FOR

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8188

81888188

8188

81888188

8188

TESTING TECHNOLOGY DEPARTMENT / TSSC

Apr . 2003

BY:

Rain Li

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Contents

1. Hardware Engineering Specification ---------------------------------------------------------------------------

1.1 Introduction ---------------------------------------------------------------------------------------------------------

1.2 System Hardware ---------------------------------------------------------------------------------------------------

1.3 TV/FM General Feature -------------------------------------------------------------------------------------------

1.4 Other Functions-----------------------------------------------------------------------------------------------------

1.5 Peripheral Components------------------------------------------------------------------------------------------------------------

1.6 Power Management-----------------------------------------------------------------------------------------------------------------

1.7 Appendix------------------------------------------------------------------------------------------------------------------------------

2. System View & Disassembly --------------------------------------------------------------------------------------

2.1 System View ---------------------------------------------------------------------------------------------------------

2.2 System Disassembly -------------------------------------------------------------------------------------------------

3. Definition & Location of Connectors / Switches Setting ----------------------------------------------------

4. Definition & Location of Major Component ------------------------------------------------------------------

5. Subsystem Board Connection with System Board------------------------------------------------------------

6. Pin Description of Major Component ---------------------------------------------------------------------------

6.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pins ---------------------------------------------------------

6.2 VIA VT8703 North Bridge with S3 Savage4 AGPX4--------------------------------------------------------------

6.3 VIA VT8235 PCI-LPC/ISA South Bridge -------------------------------------------------------------------------

7. System Block Diagram ---------------------------------------------------------------------------------------------

8. Maintenance Diagnostics ------------------------------------------------------------------------------------------

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8.1 Introduction ---------------------------------------------------------------------------------------------------------

8.2 PCI Debug Card ----------------------------------------------------------------------------------------------------

8.3 Error Codes ---------------------------------------------------------------------------------------------------------

9. Trouble Shooting ----------------------------------------------------------------------------------------------------

9.1 No Power ------------------------------------------------------------------------------------------------------------

9.2 No Display -----------------------------------------------------------------------------------------------------------

9.3 AGP Controller Error-----------------------------------------------------------------------------------------------

9.4 Memory Test Error -------------------------------------------------------------------------------------------------

9.5 Keyboard Test Error ------------------------------------------------------------------------------------------------

9.6 Hard Disk Test Error------------------------------------------------------------------------------------------------

9.7 CD-ROM Drive Test Error------------------------------------------------------------------------------------------

9.8 USB Port Test Error ------------------------------------------------------------------------------------------------

9.9 PC Card Socket Test Error ----------------------------------------------------------------------------------------

9.10 Memory_Card Test Error -----------------------------------------------------------------------------------------

9.11 LAN Test Error -----------------------------------------------------------------------------------------------------

9.12 IEEE1394 Test Error-----------------------------------------------------------------------------------------------

9.13 Audio Driver Failure -----------------------------------------------------------------------------------------------

10. Spare Parts List ----------------------------------------------------------------------------------------------------

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12. Circuit Diagram-----------------------------------------------------------------------------------------------------

***

13. Reference Material -------------------------------------------------------------------------------------------------

***

11. System Exploded Views--------------------------------------------------------------------------------------------

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Contents

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1. Hardware Engineering Specification

1.1 Introduction

The E8188 model motherboard would support the Desktop P4 processor (Northwood) at 2.0~3.06 GHz or above

(supported Intel Hyper threading) and the Celeron low-profile, lidless FC-PGA2 (Flip-chip Pin Grid Array) package

on socket 478.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has

standard hardware peripheral interface and support Intel mobile Pentium 4-M and Desktop Pentium 4 family. The

power management complies with Advanced Configuration and Power Interface (ACPI) 1.0b. System also provides

icon LEDs to display system status, such as AC Power indicator and CDROM, HDD, NUM LOCK, CAP LOCK,

SCROLL LOCK. It also equipped with 4 USB2.0 ports, two IEEE1394, one PCI Card slots (For TV tuner Card),

one type II PCMCIA slot and one memory card reader, LAN 10/100TX, MDC modem and AC97 3D stereo audio

functions. Also with a specific AGP slot can upgrade VGA with customs needed.

The memory subsystem supports two 184 pin DDR DIMM socket for upgrading up to 2.0GB of 200MHz,

266MHz or 333MHz DDR SDRAM using DDR-SDAM DIMM modules with SPD.

The ENE CB710 CARDBUS controller supports one PCMCIA or CARDBUS interfaces and Memory card reader

interface.

The VIA 6307L controller supports two port multimedia feature.

To provide for the increasing number of multimedia applications, the AC97 CODEC C-Media CMI9739 is

integrated onto the motherboard which contain 3D audio output.

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A full set of software drivers and utilities are available to allow advanced operating systems such as Windows and

Windows 2000 and Windows XP to take full advantage of the hardware capabilities such as bus mastering IDE,

Windows 95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power

interface (ACPI).

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Parts

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1.2.1 CPU-Intel Desktop Pentium4(Northwood) Processor In FC-PGA478 Package

The Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process is a follow on to the Pentium 4

processor in the 478-pin package with Intel Net Burst. microarchitecture. The Pentium 4 processor with 512-KB L2

cache on 0.13 micron process utilizes Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a

478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket.

The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process, like its predecessor, the Pentium 4

processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of

Compatibility with IA-32 software. In this document, the Pentium 4 processor with 512-KB L2 cache on 0.13 micron

process will be referred to as the “Pentium 4 processor with 512-KB L2 cache on 0.13 micron process,” or simply

“the processor.”

The Intel NetBurst microarchitecture features include hyper pipelined technology, a rapid execution engine, a 400-

MHz or a 533-MHz system bus, and an execution trace cache. The hyper pipelined technology doubles the pipeline

depth in the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process, allowing the processor to reach

much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at

twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz or 533-

MHz system bus is a quad-pumped bus running off a 100-MHz or a 133-MHz system clock making 3.2 Gbytes/sec

and 4.3 Gbytes/sec data transfer rates possible. The execution trace cache is a first-level cache that stores

approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main

execution path, thereby increasing performance. Additional features within the Intel NetBurst microarchitecture

include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and

Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch

prediction internal to the processor. The advanced transfer cache is a 512 KB, on-die level 2 (L2) cache.

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A new floating point and multi media unit has been implemented which provides superior performance for multi-

media and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision

floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-

Grant, Sleep, and Deep Sleep have been retained. The Streaming SIMD Extensions 2 (SSE2) enable break-through

levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech

recognition. The new packed double-precision floating-point instructions enhance performance for applications that

require greater range and precision, including scientific and engineering applications and advanced 3-D geometry

techniques, such as ray tracing.

The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process Intel Net Burst microarchitecture system

bus utilizes a split-transaction, deferred reply protocol like the Pentium 4 processor. This system bus is not

compatible with the P6 processor family bus. The Intel Net Burst microarchitecture system bus uses Source-

Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus

clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two

times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus

and 2X address bus provide a data bus bandwidth of up to 4.3 G byte s/second.

Intel will enable support components for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process

including heat sinks, heat sink retention mechanisms, and sockets. Manufacturability is a high priority; hence,

mechanical assembly can be completed from the top of the motherboard and should not require any special tooling.

The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic

(AGTL+) signal technology.

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1.2.1.1 Intel Desktop Pentium 4 Processor (Northwood) Microarchitecture Summary

The following features summarize the Intel Pentium 4 Processor microarchitecture:

Available at 2 GHz, 2.20 GHz, 2.26 GHz,2.40 GHz, and 2.53 GHz

Binary compatible with applications running on previous members of the Intel microprocessor line

Intel® Net Burst™ micro-architecture

System bus frequency at 400 MHz and 533 MHz

Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency

Hyper Pipelined Technology

Advance Dynamic Execution

----Very deep out-of-order execution

----Enhanced branch prediction

Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops

8 KB Level 1 data cache

512 KB Advanced Transfer Cache (on- die, full speed Level 2 (L2) cache) with 8-way associativity and Error

Correcting Code (ECC)

144 Streaming SIMD Extensions 2 (SSE2) instructions

Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance

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Power Management capabilities

----System Management mode

----Multiple low-power states

Optimized for 32-bit applications running on advanced 32-bit operating systems

8-way cache associativity provides improved cache hit rate on load/store operations.

Table 1.Voltage identification Definition for Desktop Northwood

VID4 VID3 VID2 VID1 VID0 Vc c_ M A X

11111VRM output of

f

111101.100

111011.125

111001.150

110111.175

110101.200

110011.225

110001.250

101111.275

101101.300

101011.325

101001.350

100111.375

100101.400

100011.425

100001.450

011111.475

011101.500

011011.525

011001.550

Processor Pins

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1.2.2 CPU – Intel Celeron Processor In Micro-PGA 478 Package

The Intel® Celeron® processor in the 478-pin package utilizes Flip-Chip Pin Grid Array (FC-PGA2) package

technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B

socket. The Celeron processor in the 478-pin package maintains the tradition of compatibility with IA-32 software.

The Celeron processor in the 478-pin package is designed for uni-processor based Value PC desktop systems.

Features of processor include hyper pipelined technology, a 400 MHz system bus, and an execution trace cache. The

400 MHz system bus is a quad-pumped bus that is clocked with a 100 MHz system clock, making 3.2 GB/sec data

transfer rates possible. The execution trace cache is a first level cache that stores approximately 12k decoded micro-

operations, which removes the decoder from the main execution path. Additional features include advanced dynamic

execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2

(SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the

processor. The advanced transfer cache is a 128 KB, on-die level 2 (L2) cache. The floating point and multimedia

units have 128 bit wide registers with a separate register for data movement. Finally, SSE2 support includes

instructions for double-precision floating point, SIMD integer, and memory management. Power management

capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep have also been retained. The Celeron processor

in the 478-pin package 400 MHz system bus utilizes a split-transaction, deferred reply protocol. This system bus is

not compatible with the P6 processor family bus. The 400 MHz system bus uses Source-Synchronous Transfer (SST)

of address and data to improve throughput by transferring data four times per bus clock (4X data transfer rate, as in

AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock, and is referred

to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus

bandwidth of up to 3.2 GB/second. Intel will be enabling support components for the Celeron processor in the 478-

pin package including a heatsink, heat sink retention mechanism, and socket. Manufacturability is a high priority;

hence mechanical assembly can be completed from the top of the motherboard and should not require any special

tooling. The processor system bus uses a variant of GTL+ signaling technology called Assisted Gunning Transceiver

Logic (AGTL+) signalling technology.

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1.2.2.1 Intel Celeron–Processor Microarchitecture Summary

The following features summarize the Intel Celeron Processor Microarchitecture:

Available at 1.70,1.8G and 1.90 GHz

Binary compatible with applications running on previous members of the Intel microprocessor line

System bus frequency at 400 MHz.

Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency.

Hyper Pipelined Technology.

Advanced Dynamic Execution

----Very deep out-of-order execution

----Enhanced branch prediction

8 KB Level 1 data cache

Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops

128 KB Advanced Transfer Cache (on-die,full speed Level 2 (L2) cache) with Error Correction Code (ECC)

144 Streaming SIMD Extensions 2 (SSE2) Instructions

Power Management capabilities

----System Management mode

----Multiple low-power states

Optimized for 32-bit applications running on advanced 32-bit operating systems

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Table 2. Voltage identification Definition for Mobile Northwood

VID4 VID3 VID2 VI D1 VID0 Vc c_ M A X

11111VRM output of

f

111101.100

111011.125

111001.150

110111.175

110101.200

110011.225

110001.250

101111.275

101101.300

101011.325

101001.350

100111.375

100101.400

100011.425

100001.450

011111.475

011101.500

011011.525

011001.550

010111.575

010101.600

010011.625

010001.650

001111.675

001101.700

001011.725

001001.750

000111.775

000101.800

000011.825

000001.850

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1.2.3 Intel 845GE/PE GMCH

1.2.3.1 System Overview:

The 845GE/PE chipsets are a Graphics Memory Controller Hub (GMCH) designed for use with a mPGA478

processor. The GMCH component provides the CPU interface, DDR-SDRAM interface, AGP interface, Hub Interface,

and integrated graphics with several display interfaces (845GE only). The CPU interface supports the Pentium 4

processor subset of the Extended Mode of the Scalable Bus Protocol. The GMCH supports a single channel of DDR

SDRAM. It also supports 1x/2x/4x AGP data transfers and 2x/4x AGP Fast Writes, as defined in the Accelerated

Graphics Port Interface Specification, Revision 2.0 for 1.5V signaling. The integrated graphics controller uses a

portion of system memory for graphics memory (UMA); it does not support Local Memory. The 845GE/PE chipset

platform supports the fourth-generation I/O Controller Hub (ICH4).

1.2.3.2 845GE/PE GMCH Feature List:

Host Interface

--- Supports one physical CPU in a mPGA478 package

--- Supports VTT range from 1.15-1.75 V. The Vtt range is 1.29V – 1.525V for Intel ® Pentium® 4 processor

with 512-KB L2 cache on 0.13 micron process. Supports VTT range from 1.535V – 1.75V for the Pentiun 4

processor with 256-KB L2 cache

--- Supports FSB frequency of 400MHz (100MHz bus clock) and 533MHz (133MHz bus clock)

--- Supports FSB Dynamic Bus Inversion on the data bus

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--- Supports 32-bit addressing for access to 4 GB of Memory Space

--- Supports 8 deep In Order Queue

--- Supports AGTL+ On-die Termination

System Memory Controller (DDR only)

--- Supports one 64-bit wide DDR SDRAM data channel

--- Available bandwidth up to 2.7GB/s (DDR333)

--- Supports DDR memory only

--- Supports 64-MB, 128-MB, 256-MB, 512-MB SDRAM technologies

--- Supports only x8 and x16 SDRAM devices with four banks

--- Does not support ECC function

--- Registered DIMMs not support

--- Supports unberffered non-ECC DIMMs only

--- Support opportunistic refresh

--- Up to 16, simultaneously open pages (fore per row, four rows maximum)

--- SPD (Serial Presence Detect) scheme for DIMM detection

--- Suspend-to-RAM support using CKE

--- Double Data Rate (DDR) SDRAM configuration

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Hub Interface

--- Supports Hub Interface 1.5

--- 266MB/s point-to-point Hub Interface to the ICH4

--- 66MHz base clock

--- 1.5V operation

AGP Interface

--- Supports a single 1.5V Accelerated Graphics Port Interface, Specification 2.0-compliant device

--- Support 1x/2x/4x data transfers and 2x/4x Fast Writes

--- 32-deep AGP request queue

--- AGP signals multiplexed with two Intel® DVO port (Intel® 845GE only)

Graphics Features (Intel ® 845GE only)

--- Core Frequency of 266MHz

--- Setup and Render Engine

--- Zone Rendering Support

--- Quality Texture Engine

--- 3D Graphics Rasterization Enhancements

--- 2D Graphics

--- Video DVD/PC-VCR

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--- Video Overlay

Display (Intel ® 845GE only)

--- Analog Display Support

--- Multiplexed Digital Display Channels

GMCH Package

--- 37.5mm x 37.5mm FC-BGA package with 1 mm ball pitch

--- 1.5V core voltage

Supported FSB/Memory Configurations

--- FSB 400MHz and DDR 200 supported

--- FSB 400/533MHz and DDR 266 supported

--- FSB 533MHz and DDR 333 supported

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1.2.4 Intel ® 82801DB I/O Controller Hub 4 (ICH4)

1.2.4.1 System Overview:

The ICH4 provides extensive I/O support. Functions and capabilities include:

PCI Local Bus Specification, Revision 2.2-compliant with support for 33 MHz PCI operations.

PCI slots (supports up to 6 Req/Gnt pairs)

ACPI Power Management Logic Support

Enhanced DMA controller, Interrupt controller, and timer functions

Integrated IDE controller supports Ultra ATA100/66/33

USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI high-speed

USB 2.0 Host controller

Integrated LAN controller

System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices

Supports Audio Codec ’97, Revision 2.3 specification (a.k.a., AC ’97 Component Specification,

Revision 2.3) Link for Audio and Telephony codecs (up to seven channels)

Low Pin Count (LPC) interface

Firmware Hub (FWH) interface support

Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)

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1.2.4.2 An overview of the ICH4 capabilities.

 Hub Architecture

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With AC ’97,

USB 2.0, and Ultra ATA/100, coupled with the existing USB, I/O requirements could impact PCI bus performance.

The chipset’s hub interface architecture ensures that the I/O subsystem; both PCI and the integrated I/O features

(IDE, AC ‘97, USB, etc.), receive adequate bandwidth. By placing the I/O bridge on the hub interface (instead of

PCI), the hub architecture ensures that both the I/O functions integrated into the ICH4 and the PCI peripherals

obtain the bandwidth necessary for peak performance.

 PCI Interface

The ICH4 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are 5 V tolerant,

except PME#. The ICH4 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the

internal ICH4 requests.

 IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and ATAPI

devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16

Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not consume any ISA DMA resources. The IDE

interface integrates 16x32-bit buffers for optimal transfers.

The ICH4’s IDE system contains two independent IDE signal channels. They can be electrically isolated

independently. They can be configured to the standard primary and secondary channels (four devices). There are

integrated series resistors on the data and control lines (see Section 5.15 for details).

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 Low Pin Count (LPC) Interface

The ICH4 implements an LPC Interface as described in the LPC 1.0 specification. The Low Pin Count (LPC)

Bridge function of the ICH4 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function,

D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power Management, System

Management, GPIO, and RTC.

Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low Pin Count (LPC)

interface. Migration to the LPC interface allows for lower cost Super I/O designs.

 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently

programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are

hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support

fast Type-F transfers.

The ICH4 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA. LPC DMA and

PC/PCI DMA use the ICH4’s DMA controller. The PC/PCI protocol allows PCI-based peripherals to initiate DMA

cycles by encoding requests and grants via two PC/PCI REQ#/GNT# pairs.

LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0]

from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are

8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those found in one 82C54

programmable interval timer. These three counters are combined to provide the system timer function, and speaker

tone. The 14.31818 MHz oscillator input provides the clock source for these three counters.

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