MCF5213 ColdFire
®
Integrated
Microcontroller Reference Manual
Devices Supported:
MCF5211
MCF5212
MCF5213
Document Number: MCF5213RM
Rev. 5
4/2011
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Document Number: MCF5213RM
Rev. 5
4/2011
Freescale Semiconductor iii
Chapter 1
Overview
1.1 Introduction ................................................................................................................................... 1-1
1.2 MCF5213 Family Configurations ................................................................................................. 1-1
1.3 Block Diagram .............................................................................................................................. 1-2
1.4 Part Numbers and Packaging ........................................................................................................ 1-3
1.5 Features ......................................................................................................................................... 1-4
1.5.1 V2 Core Overview ........................................................................................................ 1-8
1.5.2 Integrated Debug Module ............................................................................................. 1-8
1.5.3 JTAG ............................................................................................................................. 1-9
1.5.4 On-Chip Memories ....................................................................................................... 1-9
1.5.5 Power Management .................................................................................................... 1-10
1.5.6 FlexCAN ..................................................................................................................... 1-10
1.5.7 UARTs ........................................................................................................................ 1-10
1.5.8 I
2
C Bus ....................................................................................................................... 1-11
1.5.9 QSPI ........................................................................................................................... 1-11
1.5.10 Fast ADC .................................................................................................................... 1-11
1.5.11 DMA Timers (DTIM0–DTIM3) ................................................................................ 1-11
1.5.12 General Purpose Timer (GPT) .................................................................................... 1-11
1.5.13 Periodic Interrupt Timers (PIT0 and PIT1) ................................................................ 1-12
1.5.14 Pulse-Width Modulation (PWM) Timers ................................................................... 1-12
1.5.15 Software Watchdog Timer .......................................................................................... 1-12
1.5.16 Phase-Locked Loop (PLL) ......................................................................................... 1-12
1.5.17 Interrupt Controller (INTC) ........................................................................................ 1-12
1.5.18 DMA Controller ......................................................................................................... 1-13
1.5.19 Reset ........................................................................................................................... 1-13
1.5.20 GPIO ........................................................................................................................... 1-13
1.6 Memory Map Overview .............................................................................................................. 1-13
Chapter 2
Signal Descriptions
2.1 Introduction ................................................................................................................................... 2-1
2.2 Overview ....................................................................................................................................... 2-1
2.3 Pin Functions ................................................................................................................................. 2-2
2.4 Reset Signals ................................................................................................................................. 2-7
2.5 PLL and Clock Signals .................................................................................................................. 2-7
2.6 Mode Selection .............................................................................................................................. 2-7
2.7 External Interrupt Signals .............................................................................................................. 2-7
2.8 Queued Serial Peripheral Interface (QSPI) ...................................................................................2-8
2.9 I
2
C I/O Signals .............................................................................................................................. 2-8
2.10 UART Module Signals .................................................................................................................. 2-8
iv Freescale Semiconductor
2.11 DMA Timer Signals ...................................................................................................................... 2-9
2.12 ADC Signals .................................................................................................................................. 2-9
2.13 General Purpose Timer Signals ..................................................................................................... 2-9
2.14 Pulse-Width Modulator Signals .................................................................................................. 2-10
2.15 Debug Support Signals ................................................................................................................ 2-10
2.16 EzPort Signal Descriptions .......................................................................................................... 2-11
2.17 Power and Ground Pins ............................................................................................................... 2-11
Chapter 3
ColdFire Core
3.1 Introduction ................................................................................................................................... 3-2
3.1.1 Overview ...................................................................................................................... 3-2
3.2 Memory Map/Register Description ............................................................................................... 3-3
3.2.1 Data Registers (D0–D7) ............................................................................................... 3-5
3.2.2 Address Registers (A0–A6) .......................................................................................... 3-5
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) ................................................ 3-5
3.2.4 Condition Code Register (CCR) ................................................................................... 3-6
3.2.5 Program Counter (PC) .................................................................................................. 3-7
3.2.6 Vector Base Register (VBR) ......................................................................................... 3-7
3.2.7 Status Register (SR) ..................................................................................................... 3-8
3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR) ...................................... 3-9
3.3 Functional Description .................................................................................................................. 3-9
3.3.1 Version 2 ColdFire Microarchitecture .......................................................................... 3-9
3.3.2 Instruction Set Architecture (ISA_A+) ...................................................................... 3-14
3.3.3 Exception Processing Overview ................................................................................. 3-15
3.3.4 Processor Exceptions .................................................................................................. 3-18
3.3.5 Instruction Execution Timing ..................................................................................... 3-26
Chapter 4
Multiply-Accumulate Unit (MAC)
4.1 Introduction ................................................................................................................................... 4-2
4.1.1 Overview ...................................................................................................................... 4-2
4.2 Memory Map/Register Definition ................................................................................................. 4-3
4.2.1 MAC Status Register (MACSR) .................................................................................. 4-3
4.2.2 Mask Register (MASK) ................................................................................................ 4-5
4.2.3 Accumulator Register (ACC) ....................................................................................... 4-6
4.3 Functional Description .................................................................................................................. 4-7
4.3.1 Fractional Operation Mode ........................................................................................... 4-8
4.3.2 MAC Instruction Set Summary .................................................................................... 4-9
4.3.3 MAC Instruction Execution Times ............................................................................. 4-10
4.3.4 Data Representation .................................................................................................... 4-10
4.3.5 MAC Opcodes ............................................................................................................ 4-10
Freescale Semiconductor v
Chapter 5
Static RAM (SRAM)
5.1 Introduction ................................................................................................................................... 5-1
5.1.1 Overview ...................................................................................................................... 5-1
5.1.2 Features ......................................................................................................................... 5-1
5.2 Memory Map/Register Description ............................................................................................... 5-1
5.2.1 SRAM Base Address Register (RAMBAR) ................................................................. 5-2
5.3 Initialization/Application Information .......................................................................................... 5-3
5.3.1 SRAM Initialization Code ............................................................................................ 5-4
5.3.2 Power Management ...................................................................................................... 5-4
Chapter 6
Clock Module
6.1 Introduction ................................................................................................................................... 6-1
6.2 Features ......................................................................................................................................... 6-1
6.3 Modes of Operation ....................................................................................................................... 6-1
6.3.1 Normal PLL Mode ....................................................................................................... 6-1
6.3.2 1:1 PLL Mode ............................................................................................................... 6-2
6.3.3 External Clock Mode .................................................................................................... 6-2
6.3.4 Clock Mode Selection (CLKMOD[1:0]) ...................................................................... 6-2
6.4 Low-Power Mode Operation ......................................................................................................... 6-2
6.5 Block Diagram .............................................................................................................................. 6-3
6.6 Signal Descriptions ....................................................................................................................... 6-5
6.6.1 EXTAL ......................................................................................................................... 6-5
6.6.2 XTAL ............................................................................................................................ 6-5
6.6.3 CLKOUT ...................................................................................................................... 6-5
6.6.4 RSTO ............................................................................................................................ 6-5
6.7 Memory Map and Registers .......................................................................................................... 6-5
6.7.1 Register Descriptions .................................................................................................... 6-6
6.8 Functional Description ................................................................................................................ 6-10
6.8.1 System Clock Modes .................................................................................................. 6-10
6.8.2 Clock Operation During Reset ................................................................................... 6-11
6.8.3 System Clock Generation ........................................................................................... 6-11
6.8.4 PLL Operation ............................................................................................................ 6-12
Chapter 7
Power Management
7.1 Introduction ................................................................................................................................... 7-1
7.1.1 Features ......................................................................................................................... 7-1
7.2 Memory Map/Register Definition ................................................................................................. 7-1
7.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) .................................... 7-2
7.2.2 Low-Power Interrupt Control Register (LPICR) .......................................................... 7-5
7.2.3 Peripheral Power Management Set Register (PPMRS) ................................................ 7-7
7.2.4 Peripheral Power Management Clear Register (PPMRC) ............................................ 7-7
7.2.5 Low-Power Control Register (LPCR) .......................................................................... 7-8
vi Freescale Semiconductor
7.3 IPS Bus Timeout Monitor ............................................................................................................. 7-9
7.4 Functional Description ................................................................................................................ 7-10
7.4.1 Low-Power Modes ..................................................................................................... 7-10
7.4.2 Peripheral Behavior in Low-Power Modes ................................................................ 7-12
7.4.3 Summary of Peripheral State During Low-Power Modes .......................................... 7-17
Chapter 8
Chip Configuration Module (CCM)
8.1 Introduction ................................................................................................................................... 8-1
8.1.1 Features ......................................................................................................................... 8-1
8.2 External Signal Descriptions ......................................................................................................... 8-1
8.2.1 RCON ........................................................................................................................... 8-2
8.2.2 CLKMOD[1:0] ............................................................................................................. 8-2
8.2.3 JTAG_EN ..................................................................................................................... 8-2
8.2.4 TEST ............................................................................................................................. 8-2
8.3 Memory Map/Register Definition ................................................................................................. 8-2
8.3.1 Programming Model ..................................................................................................... 8-2
8.3.2 Memory Map ................................................................................................................8-3
8.3.3 Register Descriptions .................................................................................................... 8-3
Chapter 9
Reset Controller Module
9.1 Introduction ................................................................................................................................... 9-1
9.2 Features ......................................................................................................................................... 9-1
9.3 Block Diagram .............................................................................................................................. 9-1
9.4 Signals ........................................................................................................................................... 9-2
9.4.1 RSTI ............................................................................................................................. 9-2
9.4.2 RSTO ............................................................................................................................ 9-2
9.5 Memory Map and Registers .......................................................................................................... 9-2
9.5.1 Reset Control Register (RCR) ...................................................................................... 9-3
9.5.2 Reset Status Register (RSR) ......................................................................................... 9-4
9.6 Functional Description .................................................................................................................. 9-5
9.6.1 Reset Sources ................................................................................................................ 9-5
9.6.2 Reset Control Flow ....................................................................................................... 9-6
9.6.3 Concurrent Resets .........................................................................................................9-8
Chapter 10
System Control Module (SCM)
10.1 Introduction ................................................................................................................................. 10-1
10.2 Overview ..................................................................................................................................... 10-1
10.3 Features ....................................................................................................................................... 10-1
10.4 Memory Map and Register Definition ........................................................................................ 10-2
10.5 Register Descriptions .................................................................................................................. 10-3
10.5.1 Internal Peripheral System Base Address Register (IPSBAR) ................................... 10-3
10.5.2 Memory Base Address Register (RAMBAR) ............................................................ 10-4
Freescale Semiconductor vii
10.5.3 Core Reset Status Register (CRSR) ........................................................................... 10-6
10.5.4 Core Watchdog Control Register (CWCR) ................................................................ 10-7
10.5.5 Core Watchdog Service Register (CWSR) ................................................................. 10-8
10.6 Internal Bus Arbitration .............................................................................................................. 10-9
10.6.1 Overview .................................................................................................................... 10-9
10.6.2 Arbitration Algorithms ............................................................................................. 10-10
10.6.3 Bus Master Park Register (MPARK) ........................................................................ 10-10
10.7 System Access Control Unit (SACU) ....................................................................................... 10-12
10.7.1 Overview .................................................................................................................. 10-12
10.7.2 Features ..................................................................................................................... 10-12
10.7.3 Memory Map/Register Definition ............................................................................ 10-13
Chapter 11
General Purpose I/O Module
11.1 Introduction ................................................................................................................................. 11-1
11.2 Overview ..................................................................................................................................... 11-2
11.3 Features ....................................................................................................................................... 11-2
11.4 Signal Descriptions ..................................................................................................................... 11-2
11.5 Memory Map/Register Definition ............................................................................................... 11-2
11.5.1 Ports Memory Map ..................................................................................................... 11-2
11.6 Register Descriptions .................................................................................................................. 11-3
11.6.1 Port Output Data Registers (PORTn) ......................................................................... 11-3
11.6.2 Port Data Direction Registers (DDRn) ....................................................................... 11-5
11.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn) .................................................... 11-7
11.6.4 Port Clear Output Data Registers (CLRn) .................................................................. 11-9
11.6.5 Pin Assignment Registers ......................................................................................... 11-10
11.6.6 Pad Control Registers ............................................................................................... 11-13
11.7 Ports Interrupts .......................................................................................................................... 11-15
Chapter 12
Edge Port Module (EPORT)
12.1 Introduction ................................................................................................................................. 12-1
12.2 Low-Power Mode Operation ....................................................................................................... 12-1
12.3 Interrupt/General-Purpose I/O Pin Descriptions ......................................................................... 12-2
12.4 Memory Map and Registers ........................................................................................................ 12-3
12.4.1 Memory Map .............................................................................................................. 12-3
12.4.2 Registers ..................................................................................................................... 12-3
Chapter 13
Interrupt Controller Module
13.1 68K/ColdFire Interrupt Architecture Overview .......................................................................... 13-1
13.1.1 Interrupt Controller Theory of Operation ................................................................... 13-2
13.2 Memory Map ............................................................................................................................... 13-4
13.3 Register Descriptions .................................................................................................................. 13-5
13.3.1 Interrupt Pending Registers (IPRHn, IPRLn) ............................................................. 13-5
viii Freescale Semiconductor
13.3.2 Interrupt Mask Registers (IMRHn, IMRLn) .............................................................. 13-6
13.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) ................................................. 13-8
13.3.4 Interrupt Request Level Register (IRLRn) ................................................................. 13-8
13.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) ............................ 13-9
13.3.6 Interrupt Control Registers (ICRnx) ......................................................................... 13-10
13.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn) ............................ 13-11
13.3.8 Global Level m IACK Registers (GLmIACK) ......................................................... 13-12
13.4 Low-Power Wakeup Operation ................................................................................................. 13-15
Chapter 14
DMA Controller Module
14.1 Introduction ................................................................................................................................. 14-1
14.1.1 Overview .................................................................................................................... 14-1
14.1.2 Features ....................................................................................................................... 14-2
14.2 DMA Transfer Overview ............................................................................................................ 14-3
14.3 Memory Map/Register Definition ............................................................................................... 14-3
14.3.1 DMA Request Control (DMAREQC) ........................................................................ 14-4
14.3.2 Source Address Registers (SARn) .............................................................................. 14-5
14.3.3 Destination Address Registers (DARn) ...................................................................... 14-6
14.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) ........................... 14-6
14.3.5 DMA Control Registers (DCRn) ................................................................................ 14-8
14.4 Functional Description .............................................................................................................. 14-11
14.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) ......................................... 14-12
14.4.2 Dual-Address Data Transfer Mode ........................................................................... 14-12
14.4.3 Channel Initialization and Startup ............................................................................ 14-13
14.4.4 Data Transfer ............................................................................................................ 14-14
14.4.5 Termination ............................................................................................................... 14-15
Chapter 15
ColdFire Flash Module (CFM)
15.1 Introduction ................................................................................................................................. 15-1
15.1.1 Overview .................................................................................................................... 15-1
15.1.2 Features ....................................................................................................................... 15-2
15.2 External Signal Description ........................................................................................................ 15-3
15.3 Memory Map and Register Definition ........................................................................................ 15-3
15.3.1 Memory Map .............................................................................................................. 15-3
15.3.2 Flash Base Address Register (FLASHBAR) .............................................................. 15-4
15.3.3 Register Descriptions .................................................................................................. 15-7
15.4 Functional Description .............................................................................................................. 15-16
15.4.1 General ..................................................................................................................... 15-16
15.4.2 Flash Normal Mode .................................................................................................. 15-16
15.4.3 Flash Security Operation .......................................................................................... 15-30
Freescale Semiconductor ix
Chapter 16
EzPort
16.1 Features ....................................................................................................................................... 16-1
16.2 Modes of Operation ..................................................................................................................... 16-1
16.3 External Signal Description ........................................................................................................ 16-2
16.3.1 Overview .................................................................................................................... 16-2
16.3.2 Detailed Signal Descriptions ...................................................................................... 16-2
16.4 Command Definition ................................................................................................................... 16-3
16.4.1 Command Descriptions .............................................................................................. 16-4
16.5 Functional Description ................................................................................................................ 16-7
16.6 Initialization/Application Information ........................................................................................ 16-8
Chapter 17
Programmable Interrupt Timers (PIT0–PIT1)
17.1 Introduction ................................................................................................................................. 17-1
17.1.1 Overview .................................................................................................................... 17-1
17.1.2 Block Diagram ............................................................................................................ 17-1
17.1.3 Low-Power Mode Operation ...................................................................................... 17-1
17.2 Memory Map/Register Definition ............................................................................................... 17-2
17.2.1 PIT Control and Status Register (PCSRn) .................................................................. 17-3
17.2.2 PIT Modulus Register (PMRn) .................................................................................. 17-4
17.2.3 PIT Count Register (PCNTRn) .................................................................................. 17-5
17.3 Functional Description ................................................................................................................ 17-5
17.3.1 Set-and-Forget Timer Operation ................................................................................. 17-5
17.3.2 Free-Running Timer Operation .................................................................................. 17-6
17.3.3 Timeout Specifications ............................................................................................... 17-6
17.3.4 Interrupt Operation ..................................................................................................... 17-6
Chapter 18
General Purpose Timer Module (GPT)
18.1 Introduction ................................................................................................................................. 18-1
18.2 Features ....................................................................................................................................... 18-1
18.3 Block Diagram ............................................................................................................................ 18-2
18.4 Low-Power Mode Operation ....................................................................................................... 18-3
18.5 Signal Description ....................................................................................................................... 18-3
18.5.1 GPT[2:0] ..................................................................................................................... 18-3
18.5.2 GPT3 ........................................................................................................................... 18-3
18.6 Memory Map and Registers ........................................................................................................ 18-3
18.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ............................... 18-5
18.6.2 GPT Compare Force Register (GPCFORC) ............................................................... 18-5
18.6.3 GPT Output Compare 3 Mask Register (GPTOC3M) ................................................ 18-6
18.6.4 GPT Output Compare 3 Data Register (GPTOC3D) .................................................. 18-7
18.6.5 GPT Counter Register (GPTCNT) .............................................................................. 18-7
18.6.6 GPT System Control Register 1 (GPTSCR1) ............................................................. 18-8
18.6.7 GPT Toggle-On-Overflow Register (GPTTOV) ........................................................ 18-9
x Freescale Semiconductor
18.6.8 GPT Control Register 1 (GPTCTL1) .......................................................................... 18-9
18.6.9 GPT Control Register 2 (GPTCTL2) ........................................................................ 18-10
18.6.10 GPT Interrupt Enable Register (GPTIE) ................................................................... 18-10
18.6.11 GPT System Control Register 2 (GPTSCR2) ........................................................... 18-11
18.6.12 GPT Flag Register 1 (GPTFLG1) ............................................................................. 18-12
18.6.13 GPT Flag Register 2 (GPTFLG2) ............................................................................. 18-12
18.6.14 GPT Channel Registers (GPTCn) ............................................................................. 18-13
18.6.15 Pulse Accumulator Control Register (GPTPACTL) ................................................. 18-13
18.6.16 Pulse Accumulator Flag Register (GPTPAFLG) ...................................................... 18-14
18.6.17 Pulse Accumulator Counter Register (GPTPACNT) ................................................ 18-15
18.6.18 GPT Port Data Register (GPTPORT) ....................................................................... 18-16
18.6.19 GPT Port Data Direction Register (GPTDDR) ......................................................... 18-16
18.7 Functional Description .............................................................................................................. 18-16
18.7.1 Prescaler ................................................................................................................... 18-17
18.7.2 Input Capture ............................................................................................................ 18-17
18.7.3 Output Compare ....................................................................................................... 18-17
18.7.4 Pulse Accumulator .................................................................................................... 18-18
18.7.5 Event Counter Mode ................................................................................................. 18-18
18.7.6 Gated Time Accumulation Mode ............................................................................. 18-18
18.7.7 General-Purpose I/O Ports ........................................................................................ 18-19
18.8 Reset .......................................................................................................................................... 18-21
18.9 Interrupts ................................................................................................................................... 18-21
18.9.1 GPT Channel Interrupts (CnF) ................................................................................. 18-21
18.9.2 Pulse Accumulator Overflow (PAOVF) ................................................................... 18-21
18.9.3 Pulse Accumulator Input (PAIF) .............................................................................. 18-21
18.9.4 Timer Overflow (TOF) ............................................................................................. 18-22
Chapter 19
DMA Timers (DTIM0–DTIM3)
19.1 Introduction ................................................................................................................................. 19-1
19.1.1 Overview .................................................................................................................... 19-1
19.1.2 Features ....................................................................................................................... 19-2
19.2 Memory Map/Register Definition ............................................................................................... 19-3
19.2.1 DMA Timer Mode Registers (DTMRn) ..................................................................... 19-3
19.2.2 DMA Timer Extended Mode Registers (DTXMRn) .................................................. 19-5
19.2.3 DMA Timer Event Registers (DTERn) ...................................................................... 19-5
19.2.4 DMA Timer Reference Registers (DTRRn) ............................................................... 19-7
19.2.5 DMA Timer Capture Registers (DTCRn) .................................................................. 19-7
19.2.6 DMA Timer Counters (DTCNn) ................................................................................ 19-8
19.3 Functional Description ................................................................................................................ 19-8
19.3.1 Prescaler ..................................................................................................................... 19-8
19.3.2 Capture Mode ............................................................................................................. 19-8
19.3.3 Reference Compare .................................................................................................... 19-8
19.3.4 Output Mode ............................................................................................................... 19-9
19.4 Initialization/Application Information ........................................................................................ 19-9
Freescale Semiconductor xi
19.4.1 Code Example ............................................................................................................ 19-9
19.4.2 Calculating Time-Out Values ................................................................................... 19-10
Chapter 20
Queued Serial Peripheral Interface (QSPI)
20.1 Introduction ................................................................................................................................. 20-1
20.1.1 Block Diagram ............................................................................................................ 20-1
20.1.2 Overview .................................................................................................................... 20-2
20.1.3 Features ....................................................................................................................... 20-2
20.1.4 Modes of Operation .................................................................................................... 20-2
20.2 External Signal Description ........................................................................................................ 20-2
20.3 Memory Map/Register Definition ............................................................................................... 20-3
20.3.1 QSPI Mode Register (QMR) ...................................................................................... 20-3
20.3.2 QSPI Delay Register (QDLYR) ................................................................................. 20-5
20.3.3 QSPI Wrap Register (QWR) ...................................................................................... 20-6
20.3.4 QSPI Interrupt Register (QIR) .................................................................................... 20-6
20.3.5 QSPI Address Register (QAR) ................................................................................... 20-7
20.3.6 QSPI Data Register (QDR) ........................................................................................ 20-8
20.3.7 Command RAM Registers (QCR0–QCR15) ............................................................. 20-8
20.4 Functional Description ................................................................................................................ 20-9
20.4.1 QSPI RAM ............................................................................................................... 20-11
20.4.2 Baud Rate Selection ................................................................................................. 20-12
20.4.3 Transfer Delays ......................................................................................................... 20-13
20.4.4 Transfer Length ........................................................................................................ 20-14
20.4.5 Data Transfer ............................................................................................................ 20-14
20.5 Initialization/Application Information ...................................................................................... 20-15
Chapter 21
UART Modules
21.1 Introduction ................................................................................................................................. 21-1
21.1.1 Overview .................................................................................................................... 21-1
21.1.2 Features ....................................................................................................................... 21-2
21.2 External Signal Description ........................................................................................................ 21-3
21.3 Memory Map/Register Definition ............................................................................................... 21-3
21.3.1 UART Mode Registers 1 (UMR1n) ........................................................................... 21-5
21.3.2 UART Mode Register 2 (UMR2n) ............................................................................. 21-6
21.3.3 UART Status Registers (USRn) ................................................................................. 21-8
21.3.4 UART Clock Select Registers (UCSRn) .................................................................... 21-9
21.3.5 UART Command Registers (UCRn) .......................................................................... 21-9
21.3.6 UART Receive Buffers (URBn) ............................................................................... 21-11
21.3.7 UART Transmit Buffers (UTBn) .............................................................................. 21-12
21.3.8 UART Input Port Change Registers (UIPCRn) ........................................................ 21-12
21.3.9 UART Auxiliary Control Register (UACRn) ........................................................... 21-13
21.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) ........................................ 21-13
21.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) ....................................... 21-15
xii Freescale Semiconductor
21.3.12 UART Input Port Register (UIPn) ............................................................................ 21-15
21.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ..................................... 21-16
21.4 Functional Description .............................................................................................................. 21-16
21.4.1 Transmitter/Receiver Clock Source .......................................................................... 21-16
21.4.2 Transmitter and Receiver Operating Modes ............................................................. 21-18
21.4.3 Looping Modes ......................................................................................................... 21-22
21.4.4 Multidrop Mode ........................................................................................................ 21-24
21.4.5 Bus Operation ........................................................................................................... 21-26
21.5 Initialization/Application Information ...................................................................................... 21-26
21.5.1 Interrupt and DMA Request Initialization ................................................................ 21-26
21.5.2 UART Module Initialization Sequence .................................................................... 21-29
Chapter 22
I
2
C Interface
22.1 Introduction ................................................................................................................................. 22-1
22.1.1 Block Diagram ............................................................................................................ 22-1
22.1.2 Overview .................................................................................................................... 22-2
22.1.3 Features ....................................................................................................................... 22-2
22.2 Memory Map/Register Definition ............................................................................................... 22-3
22.2.1 I
2
C Address Register (I2ADR) ................................................................................... 22-3
22.2.2 I
2
C Frequency Divider Register (I2FDR) .................................................................. 22-3
22.2.3 I
2
C Control Register (I2CR) ....................................................................................... 22-4
22.2.4 I
2
C Status Register (I2SR) .......................................................................................... 22-6
22.2.5 I
2
C Data I/O Register (I2DR) ..................................................................................... 22-7
22.3 Functional Description ................................................................................................................ 22-7
22.3.1 START Signal ............................................................................................................. 22-7
22.3.2 Slave Address Transmission ....................................................................................... 22-8
22.3.3 Data Transfer .............................................................................................................. 22-8
22.3.4 Acknowledge .............................................................................................................. 22-9
22.3.5 STOP Signal ............................................................................................................... 22-9
22.3.6 Repeated START ........................................................................................................ 22-9
22.3.7 Clock Synchronization and Arbitration .................................................................... 22-11
22.3.8 Handshaking and Clock Stretching .......................................................................... 22-12
22.4 Initialization/Application Information ...................................................................................... 22-12
22.4.1 Initialization Sequence ............................................................................................. 22-12
22.4.2 Generation of START ............................................................................................... 22-12
22.4.3 Post-Transfer Software Response ............................................................................. 22-13
22.4.4 Generation of STOP ................................................................................................. 22-13
22.4.5 Generation of Repeated START ............................................................................... 22-14
22.4.6 Slave Mode ............................................................................................................... 22-14
22.4.7 Arbitration Lost ........................................................................................................ 22-14
Chapter 23
Analog-to-Digital Converter (ADC)
23.1 Introduction ................................................................................................................................. 23-1
Freescale Semiconductor xiii
23.2 Features ....................................................................................................................................... 23-1
23.3 Block Diagram ............................................................................................................................ 23-2
23.4 Memory Map and Register Definition ........................................................................................ 23-2
23.4.1 Control 1 Register (CTRL1) ....................................................................................... 23-3
23.4.2 Control 2 Register (CTRL2) ....................................................................................... 23-5
23.4.3 Zero Crossing Control Register (ADZCC) ................................................................. 23-8
23.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2) .......................................... 23-8
23.4.5 Sample Disable Register (ADSDIS) ........................................................................ 23-10
23.4.6 Status Register (ADSTAT) ....................................................................................... 23-11
23.4.7 Limit Status Register (ADLSTAT) ........................................................................... 23-13
23.4.8 Zero Crossing Status Register (ADZCSTAT) .......................................................... 23-14
23.4.9 Result Registers (ADRSLTn) ................................................................................... 23-14
23.4.10 Low and High Limit Registers (ADLLMTn and ADHLMTn) ................................ 23-15
23.4.11 Offset Registers (ADOFSn) ..................................................................................... 23-17
23.4.12 Power Control Register (POWER) ........................................................................... 23-17
23.4.13 Voltage Reference Register (CAL) ........................................................................... 23-20
23.5 Functional Description .............................................................................................................. 23-21
23.5.1 Input MUX Function ................................................................................................ 23-23
23.5.2 ADC Sample Conversion ......................................................................................... 23-25
23.5.3 ADC Data Processing ............................................................................................... 23-27
23.5.4 Sequential vs. Parallel Sampling .............................................................................. 23-28
23.5.5 Scan Sequencing ....................................................................................................... 23-29
23.5.6 Scan Configuration and Control ............................................................................... 23-30
23.5.7 Interrupt Sources ...................................................................................................... 23-32
23.5.8 Power Management .................................................................................................. 23-32
23.5.9 ADC Clock ............................................................................................................... 23-34
23.5.10 Voltage Reference Pins VREFH and VREFL .......................................................... 23-37
23.5.11 Supply Pins VDDA and VSSA ................................................................................ 23-38
Chapter 24
Pulse-Width Modulation (PWM) Module
24.1 Introduction ................................................................................................................................. 24-1
24.1.1 Overview .................................................................................................................... 24-1
24.2 Memory Map/Register Definition ............................................................................................... 24-2
24.2.1 PWM Enable Register (PWME) ................................................................................ 24-3
24.2.2 PWM Polarity Register (PWMPOL) .......................................................................... 24-4
24.2.3 PWM Clock Select Register (PWMCLK) .................................................................. 24-4
24.2.4 PWM Prescale Clock Select Register (PWMPRCLK) .............................................. 24-5
24.2.5 PWM Center Align Enable Register (PWMCAE) ..................................................... 24-6
24.2.6 PWM Control Register (PWMCTL) .......................................................................... 24-7
24.2.7 PWM Scale A Register (PWMSCLA) ....................................................................... 24-8
24.2.8 PWM Scale B Register (PWMSCLB) ........................................................................ 24-9
24.2.9 PWM Channel Counter Registers (PWMCNTn) ....................................................... 24-9
24.2.10 PWM Channel Period Registers (PWMPERn) ........................................................ 24-10
24.2.11 PWM Channel Duty Registers (PWMDTYn) .......................................................... 24-11
xiv Freescale Semiconductor
24.2.12 PWM Shutdown Register (PWMSDN) .................................................................... 24-12
24.3 Functional Description .............................................................................................................. 24-13
24.3.1 PWM Clock Select ................................................................................................... 24-13
24.3.2 PWM Channel Timers .............................................................................................. 24-15
Chapter 25
FlexCAN
25.1 Introduction ................................................................................................................................. 25-1
25.1.1 Block Diagram ............................................................................................................ 25-1
25.1.2 Features ....................................................................................................................... 25-3
25.1.3 Modes of Operation .................................................................................................... 25-3
25.2 External Signal Description ........................................................................................................ 25-5
25.3 Memory Map/Register Definition ............................................................................................... 25-5
25.3.1 FlexCAN Configuration Register (CANMCR) .......................................................... 25-6
25.3.2 FlexCAN Control Register (CANCTRL) ................................................................... 25-8
25.3.3 FlexCAN Free Running Timer Register (TIMER) ................................................... 25-10
25.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK) .............................. 25-11
25.3.5 FlexCAN Error Counter Register (ERRCNT) ......................................................... 25-12
25.3.6 FlexCAN Error and Status Register (ERRSTAT) ..................................................... 25-13
25.3.7 Interrupt Mask Register (IMASK) ........................................................................... 25-15
25.3.8 Interrupt Flag Register (IFLAG) .............................................................................. 25-16
25.3.9 Message Buffer Structure ......................................................................................... 25-16
25.3.10 Functional Overview ................................................................................................ 25-20
25.3.11 Transmit Process ....................................................................................................... 25-20
25.3.12 Arbitration Process ................................................................................................... 25-21
25.3.13 Receive Process ........................................................................................................ 25-21
25.3.14 Matching Process ...................................................................................................... 25-23
25.3.15 Message Buffer Managing ....................................................................................... 25-23
25.3.16 CAN Protocol Related Frames ................................................................................. 25-25
25.3.17 Time Stamp ............................................................................................................... 25-25
25.3.18 Protocol Timing ........................................................................................................ 25-26
25.4 Initialization/Application Information ...................................................................................... 25-28
25.4.1 Interrupts ................................................................................................................... 25-29
Chapter 26
Debug Module
26.1 Introduction ................................................................................................................................. 26-2
26.1.1 Block Diagram ............................................................................................................ 26-2
26.1.2 Overview .................................................................................................................... 26-2
26.2 Signal Descriptions ..................................................................................................................... 26-3
26.3 Memory Map/Register Definition ............................................................................................... 26-4
26.3.1 Shared Debug Resources ............................................................................................ 26-5
26.3.2 Configuration/Status Register (CSR) ......................................................................... 26-6
26.3.3 BDM Address Attribute Register (BAAR) ................................................................ 26-9
26.3.4 Address Attribute Trigger Register (AATR) ............................................................ 26-10
Freescale Semiconductor xv
26.3.5 Trigger Definition Register (TDR) ........................................................................... 26-11
26.3.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) ........................... 26-14
26.3.7 Address Breakpoint Registers (ABLR, ABHR) ....................................................... 26-16
26.3.8 Data Breakpoint and Mask Registers (DBR, DBMR) .............................................. 26-17
26.4 Functional Description .............................................................................................................. 26-18
26.4.1 Background Debug Mode (BDM) ............................................................................ 26-18
26.4.2 Real-Time Debug Support ........................................................................................ 26-39
26.4.3 Concurrent BDM and Processor Operation .............................................................. 26-41
26.4.4 Real-Time Trace Support ......................................................................................... 26-41
26.4.5 Processor Status, Debug Data Definition ................................................................. 26-44
26.4.6 Freescale-Recommended BDM Pinout .................................................................... 26-50
Chapter 27
IEEE 1149.1 Test Access Port (JTAG)
27.1 Introduction ................................................................................................................................. 27-1
27.1.1 Block Diagram ............................................................................................................ 27-1
27.1.2 Features ....................................................................................................................... 27-2
27.1.3 Modes of Operation .................................................................................................... 27-2
27.2 External Signal Description ........................................................................................................ 27-2
27.2.1 JTAG Enable (JTAG_EN) .......................................................................................... 27-2
27.2.2 Test Clock Input (TCLK) ........................................................................................... 27-3
27.2.3 Test Mode Select/Breakpoint (TMS/BKPT) .............................................................. 27-3
27.2.4 Test Data Input/Development Serial Input (TDI/DSI) ............................................... 27-3
27.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) ............................................ 27-4
27.2.6 Test Data Output/Development Serial Output (TDO/DSO) ....................................... 27-4
27.3 Memory Map/Register Definition ............................................................................................... 27-4
27.3.1 Instruction Shift Register (IR) .................................................................................... 27-4
27.3.2 IDCODE Register ....................................................................................................... 27-5
27.3.3 Bypass Register .......................................................................................................... 27-5
27.3.4 JTAG_CFM_CLKDIV Register ................................................................................. 27-5
27.3.5 TEST_CTRL Register ................................................................................................ 27-6
27.3.6 Boundary Scan Register ............................................................................................. 27-6
27.4 Functional Description ................................................................................................................ 27-6
27.4.1 JTAG Module ............................................................................................................. 27-6
27.4.2 TAP Controller ........................................................................................................... 27-6
27.4.3 JTAG Instructions ....................................................................................................... 27-7
27.5 Initialization/Application Information ...................................................................................... 27-10
27.5.1 Restrictions ............................................................................................................... 27-10
27.5.2 Nonscan Chain Operation ......................................................................................... 27-10
Appendix A
Register Memory Map Quick Reference
Appendix B
Revision History
Freescale Semiconductor xxvii
About This Book
The primary objective of this reference manual is to define the functionality of the MCF5213 family of
microcontrollers for use by software and hardware developers. The MCF5213 family is a highly integrated
implementation of the ColdFire
®
family of reduced instruction set computing (RISC) microcontrollers that
also includes the MCF5211 and MCF5212. This book is written from the perspective of the MCF5213,
and unless otherwise noted, the information also applies to the MCF5211 and MCF5212. The differences
between these parts are summarized in Table 1-1 and differences in data regarding bus timing, signal
behavior, and AC, DC, and thermal characteristics are in the data sheet.
The information in this book is subject to change without notice, as described in the disclaimers on the title
page. As with any technical documentation, it is the reader’s responsibility to be sure he is using the most
recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MCF5213. It is assumed that the reader understands operating systems,
microprocessor system design, basic principles of software and hardware, and basic details of the
ColdFire
®
architecture.
Organization
Following is a summary and brief description of the major sections of this manual:
• Chapter 1, “Overview,” includes general descriptions of the modules and features on the device,
focusing in particular on new features.
• Chapter 2, “Signal Descriptions,” includes a listing of signals that characterizes each signal as an
input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.
• Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core. It describes the
organization of the Version 2 (V2) ColdFire processor core and includes an overview of the
programming model as it is implemented on the device.
• Chapter 4, “Multiply-Accumulate Unit (MAC),” describes the module that executes integer
multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated
into the operand execution pipeline (OEP).
• Chapter 5, “Static RAM (SRAM),” covers general operations, configuration, and initialization of
the on-chip static RAM (SRAM) implementation. It also provides information and examples of
how to minimize power consumption when using the SRAM.
xxviii Freescale Semiconductor
• Chapter 6, “Clock Module,” describes the device’s different clocking methods. It also describes
clock module operation in low power modes.
• Chapter 7, “Power Management,” describes the low power operation of the device and peripheral
behavior in low power modes.
• Chapter 8, “Chip Configuration Module (CCM),” details the various operating configurations of
the device. It provides a description of signals used by the CCM and a programming model.
• Chapter 9, “Reset Controller Module,” describes the operation of the reset controller module,
detailing the different types of reset that can occur.
• Chapter 10, “System Control Module (SCM),” describes the functionality of the SCM, which
provides the programming model for peripheral access control, the software core watchdog timer
(CWT), and the generic access error information.
• Chapter 11, “General Purpose I/O Module,” describes the operation and programming model of the
general purpose I/O (GPIO) ports on the device.
• Chapter 14, “DMA Controller Module,” describes operation of the interrupt controller portion of
the SCM. It includes descriptions of the registers in the interrupt controller memory map and the
interrupt priority scheme.
• Chapter 12, “Edge Port Module (EPORT),” describes the module’s functionality, including
operation in low power mode.
• Chapter 19, “DMA Timers (DTIM0–DTIM3),” describes the direct memory access (DMA)
controller module. It provides an overview of the module and describes in detail its signals and
registers. The latter sections of this chapter describe operations, features, and supported data
transfer modes in detail.
• Chapter 15, “ColdFire Flash Module (CFM),” describes implementation of the SuperFlash®
technology licensed from SST used on this device. The ColdFire Flash Module (CFM) is
constructed with four banks of 32K x 16-bit flash to generate a 256-Kbyte, 32-bit wide electrically
erasable and programmable read-only memory array. The CFM is ideal for program and data
storage for single-chip applications and allows for field reprogramming without external
high-voltage sources.
• Chapter 16, “EzPort,” describes the interface that allows the flash memory contents on a 32 bit
general-purpose microcontroller to be read, erased and programmed from off-chip in a format
compatible to many standalone flash memory chips.
• Chapter 17, “Programmable Interrupt Timers (PIT0–PIT1),” describes the functionality of the PIT
timers, including operation in low power mode.
• Chapter 18, “General Purpose Timer Module (GPT),” describes the functionality of the 4-channel
general purpose timer module (GPT), including the configuration of channel 3 as a 16-bit pulse
accumulator that can operate as a simple event counter or as a gated time accumulator.
• Chapter 19, “DMA Timers (DTIM0–DTIM3),” describes the configuration and operation of the
four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These
32-bit timers provide input capture and reference compare capabilities with optional signaling of
events using interrupts or DMA triggers. Programming examples are included.
Freescale Semiconductor xxix
• Chapter 20, “Queued Serial Peripheral Interface (QSPI),” provides a feature-set overview and a
description of operation, including details of the QSPI’s internal storage organization. The chapter
concludes with the programming model and a timing diagram.
• Chapter 21, “UART Modules,” describes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the device and includes programming examples.
• Chapter 22, “I2C Interface,” describes the I
2
C module, including I
2
C protocol, clock
synchronization, and I
2
C programming model registers.
• Chapter 23, “Analog-to-Digital Converter (ADC),” describes the two separate and complete
ADCs, each with their own sample and hold circuits and a common voltage reference and common
digital control module.
• Chapter 24, “Pulse-Width Modulation (PWM) Module,” describes the configuration and operation
of the pulse width modulation (PWM) module. It includes a block diagram, programming model,
and functional description.
• Chapter 25, “FlexCAN,” describes the implementation of the controller area network (CAN)
protocol. It describes FlexCAN module operation and provides a programming model.
• Chapter 26, “Debug Module,” describes the hardware debug support in the device.
• Chapter 27, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the
Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE
1149.1 standard and provides additional information specific to the device. For internal details and
sample applications, see the IEEE 1149.1 document.
• Appendix A, “Register Memory Map Quick Reference,” summarizes the address, name, and byte
assignment for registers within the CPU space, lists an overview of the memory map for the
on-chip modules, and provides a detailed memory map including all of the registers for on-chip
modules.
Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MNEMONICS In text, instruction mnemonics are shown in uppercase.
mnemonics In code and tables, instruction mnemonics are shown in lowercase.
italics Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
xxx Freescale Semiconductor
nibble A 4-bit data unit
byte An 8-bit data unit
word A 16-bit data unit
1
longword A 32-bit data unit
x In some contexts, such as signal encodings, x indicates a don’t care.
n Used to express an undefined numerical value
~ NOT logical operator
& AND logical operator
| OR logical operator
OVERBAR An overbar indicates that a signal is active-low.
Register Figure Conventions
This document uses the following conventions for the register reset values:
— Undefined at reset.
u Unaffected by reset.
[signal_name] Reset value is determined by the polarity of the indicated signal.
The following register fields are used:
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
R0
Indicates a reserved bit field in a memory-mapped register. These bits are
always read as zeros.
W
R1
Indicates a reserved bit field in a memory-mapped register. These bits are
always read as ones.
W
R FIELDNAME
Indicates a read/write bit.
W
R FIELDNAME
Indicates a read-only bit field in a memory-mapped register.
W
R
Indicates a write-only bit field in a memory-mapped register.
W FIELDNAME
R FIELDNAME
Write 1 to clear: indicates that writing a 1 to this bit field clears it.
Ww1c
R0
Indicates a self-clearing bit.
W FIELDNAME
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