Samsung M471B1G73AH0 User manual

Samsung
Brand
Samsung
Model
M471B1G73AH0
Category
Memory modules
Type
User manual
- 1 -
M471B1G73AH0
Rev. 1.0, Jul. 2010
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
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may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
datasheet
204pin Unbuffered SODIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
- 2 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
Revision History
Revision No. History Draft Date Remark Editor
1.0 - First Release Jul. 2010 - S.H.Kim
- 3 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
Table Of Contents
204pin Unbuffered SODIMM based on 4Gb A-die
1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5
5. Pin Description .............................................................................................................................................................6
6. Input/Output Functional Description..............................................................................................................................7
7. Function Block Diagram:...............................................................................................................................................8
7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ....................................................................... 8
8. Absolute Maximum Ratings ..........................................................................................................................................9
8.1 Absolute Maximum DC Ratings............................................................................................................................... 9
8.2 DRAM Component Operating Temperature Range ................................................................................................ 9
9. AC & DC Operating Conditions.....................................................................................................................................9
9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 9
10. AC & DC Input Measurement Levels .......................................................................................................................... 10
10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 10
10.2 V
REF
Tolerances.................................................................................................................................................... 11
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 12
10.3.1. Differential Signals Definition ......................................................................................................................... 12
10.3.2. Differential Swing Requirement for Clock (CK-CK
) and Strobe (DQS-DQS) ................................................ 12
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 13
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 14
10.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 14
10.5 Slew rate definition for Differential Input Signals ................................................................................................... 14
11. AC & DC Output Measurement Levels .......................................................................................................................15
11.1 Single Ended AC and DC Output Levels............................................................................................................... 15
11.2 Differential AC and DC Output Levels ................................................................................................................... 15
11.3 Single-ended Output Slew Rate ............................................................................................................................ 15
11.4 Differential Output Slew Rate ................................................................................................................................ 16
12. DIMM IDD specification definition ...............................................................................................................................17
13. IDD SPEC Table .........................................................................................................................................................19
14. Input/Output Capacitance ...........................................................................................................................................20
14.1 2Rx8 2GB SODIMM .............................................................................................................................................. 20
15. Electrical Characteristics and AC timing ..................................................................................................................... 21
15.1 Refresh Parameters by Device Density................................................................................................................. 21
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 21
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 21
15.3.1. Speed Bin Table Notes .................................................................................................................................. 25
16. Timing Parameters by Speed Grade ..........................................................................................................................26
16.1 Jitter Notes ............................................................................................................................................................ 29
16.2 Timing Parameter Notes........................................................................................................................................ 30
17. Physical Dimensions :.................................................................................................................................................31
17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0................................................................................ 31
- 4 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
1. DDR3 Unbuffered SODIMM Ordering Information
NOTE :
1. "##" - F8/H9
2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
• JEDEC standard 1.5V ± 0.075V Power Supply
•V
DDQ
= 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
CASE
85°C, 3.9us at 85°C < T
CASE
≤ 95°C
• Asynchronous Reset
3. Address Configuration
Part Number
2
Density Organization Component Composition
Number of
Rank
Height
M471B1G73AH0-CF8/H9 8GB 1Gx64 512Mx8(K4B4G0846A-HC##)*16 2 30mm
Speed
DDR3-800 DDR3-1066 DDR3-1333
Unit
6-6-6 7-7-7 9-9-9
tCK(min) 2.5 1.875 1.5 ns
CAS Latency 6 79tCK
tRCD(min) 15 13.125 13.5 ns
tRP(min) 15 13.125 13.5 ns
tRAS(min) 37.5 37.5 36 ns
tRC(min) 52.5 50.625 49.5 ns
Organization Row Address Column Address Bank Address Auto Precharge
512Mx8(4Gb) based Module A0-A15 A0-A9 BA0-BA2 A10/AP
- 5 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
4. x64 DIMM Pin Configurations (Front side/Back Side)
NOTE :
1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1
V
REFDQ
2
V
SS
71
V
SS
72
V
SS
139 V
SS
140 DQ38
3
V
SS
4 DQ4 KEY
141
DQ34 142 DQ39
5 DQ0 6 DQ5 73 CKE0 74 CKE1
143
DQ35 144
V
SS
7DQ18
V
SS
75
V
DD
76
V
DD
145 V
SS
146 DQ44
9
V
SS
10 DQS077 NC 78
A15
3
147
DQ40 148 DQ45
11 DM0 12DQS079 BA2 80
A14
3
149
DQ41 150
V
SS
13
V
SS
14
V
SS
81
V
DD
82
V
DD
151
V
SS
152 DQS5
15 DQ2 16 DQ6 83 A12/BC
84 A11 153 DM5 154 DQS5
17 DQ3 18 DQ7 85 A9 86 A7 155
V
SS
156
V
SS
19
V
SS
20
V
SS
87
V
DD
88
V
DD
157 DQ42 158 DQ46
21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47
23 DQ9 24 DQ13 91 A5 92 A4 161
V
SS
162
V
SS
25
V
SS
26
V
SS
93
V
DD
94
V
DD
163 DQ48 164 DQ52
27 DQS
1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53
29 DQS1 30 RESET
97 A1 98 A0 167
V
SS
168
V
SS
31
V
SS
32
V
SS
99
V
DD
100
V
DD
169
DQS
6
170
DM6
33 DQ10 34 DQ14 101 CK0 102 CK1 171
DQS6
172
V
SS
35 DQ11 36 DQ15 103 CK0104CK1 173
V
SS
174 DQ54
37
V
SS
38
V
SS
105 V
DD
106
V
DD
175 DQ50 176 DQ55
39 DQ16 40 DQ20
107
A10/AP 108 BA1 177 DQ51 178
V
SS
41 DQ17 42 DQ21
109
BA0 110 RAS 179
V
SS
180 DQ60
43
V
SS
44
V
SS
111 V
DD
112
V
DD
181 DQ56 182 DQ61
45 DQS
246 DM2
113
WE 114 S0 183 DQ57 184
V
SS
47 DQS2 48
V
SS
115
CAS
116 ODT0 185
V
SS
186 DQS7
49
V
SS
50 DQ22
117 V
DD
118
V
DD
187 DM7 188 DQS7
51 DQ18 52 DQ23
119
A13
3
120ODT1189
V
SS
190
V
SS
53 DQ19 54
V
SS
121
S
1 122 NC 191 DQ58 192 DQ62
55
V
SS
56 DQ28
123 V
DD
124
V
DD
193 DQ59 194 DQ63
57 DQ24 58 DQ29
125
TEST 126
V
REFCA
195
V
SS
196
V
SS
59 DQ25 60
V
SS
127 V
SS
128
V
SS
197 SA0 198 NC
61
V
SS
62 DQS3
129
DQ32 130 DQ36 199
V
DDSPD
200 SDA
63 DM3 64 DQS3 131 DQ33 132 DQ37 201 SA1 202 SCL
65
V
SS
66
V
SS
133 V
SS
134
V
SS
203
V
TT
204
V
TT
67 DQ26 68 DQ30 135 DQS4136 DM4
69 DQ27 70 DQ31
137
DQS4 138
V
SS
- 6 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
5. Pin Description
NOTE:
* The V
DD
and V
DDQ
pins are tied common to a single power-plane on these designs.
Pin Name Description Number Pin Name Description Number
CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64
CK
0, CK1 Clock Inputs, negative line 2 DM0-DM7
Data Masks/ Data strobes,
Termination data strobes
8
CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8
RAS
Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8
CAS
Column Address Strobe 1 RESET Reset Pin 1
WE
Write Enable 1 TEST
Logic Analyzer specific test pin (No connect
on SODIMM)
1
S
0, S1 Chip Selects 2
V
DD
Core and I/O Power 18
A0-A9, A11,
A13-A15
Address Inputs 14
V
SS
Ground 52
A10/AP Address Input/Autoprecharge 1
V
REFDQ
V
REFCA
Input/Output Reference 2
A12/BC
Address Input/Burst chop 1
V
DDSPD
SPD and Temp sensor Power 1
BA0-BA2 SDRAM Bank Addresses 3
V
TT
Termination Voltage 2
ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3
SCL Serial Presence Detect (SPD) Clock Input 1 Total 204
SDA SPD Data Input/Output 1
SA0-SA1 SPD Address 2
- 7 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
6. Input/Output Functional Description
Symbol Type Function
CK0-CK1
CK0
-CK1
Input
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-
tions is synchronized to the input clock.
CKE0-CKE1 Input
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
S
0-S1 Input
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S
0; Rank 1 is selected by S1.
R
AS, CAS, WE Input
When sampled at the cross point of the rising edge of CK and falling edge of CK
, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
A0-A9,
A10/AP,
A11
A12/BC
A13-A15
Input
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK
. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK
. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.A12(BC
) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
DQ0-DQ63 I/O Data Input/Output pins.
DM0-DM7 Input
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
DQS0-DQS7
DQS
0-DQS7
I/O
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS
signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS
.
V
DD
,V
DDSPD,
V
SS
Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
V
REFDQ,
V
REFCA
Supply Reference voltage for SSTL15 inputs.
SDA I/O
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull up.
SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.
TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET
Input RESET In Active Low This signal resets the DDR3 SDRAM
- 8 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
7. Function Block Diagram:
7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
V7
V8
V5
S1
RAS
CAS
WE
CK1
CK1
CKE1
ODT1
A[0:N]
/BA[0:N]
S0
CK0
CK0
CKE0
ODT0
DQS3
DQS3
DM3
DQS
DQS
D11
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[24:31]
D3
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
Vtt
V
DD
Vtt
Rank0
Rank1
NOTE :
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS
relationships are maintained as shown
V
SS
V
DD
D0 - D15
V
REFCA
V
DDSPD
SPD
CK0
V
REFDQ
D0 - D15
D0 - D15
D0 - D15, SPD
V
tt
CK1
CK0
CK1
RESET
V
tt
D8 - D15
D0 - D7
D0 - D7
D8 - D15
D0 - D7
V6
V2
V3
D6D12D3D9
V
tt
Address and Controllines
DQS
DQS
DQ[0:7]
DM
DQS1
DQS1
DM1
DQS
DQS
D1
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[8:15]
D9
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS0
DQS0
DM0
DQS
DQS
D0
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[0:7]
D8
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS2
DQS2
DM2
DQS
DQS
D2
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240
Ω
± 1%
DQ[16:23]
D10
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D4
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D12
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D14
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D6
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D15
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D7
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D13
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240
Ω
± 1%
D5
CS
RAS
CAS
WE
CK
CK
CKE
ODT
A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:63]
DQS5
DQS5
DM5
DQ[40:47]
V
DD
D7D5D10D8
V1
V4
V9
V7
V6
V9
V8
V4
V3
D15D13D2D0
D14D4D11D1
V1
V2
V5
V1
Vtt
A0
A1
A2
SA0
SA1
SCL
SDA
WP
SCL
(SPD)
- 9 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
8. Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. V
DD
and V
DDQ
must be within 300mV of each other at all times;and V
REF
must be not greater than 0.6 x V
DDQ
, When V
DD
and V
DDQ
are less than 500mV; V
REF
may be
equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range
NOTE :
1. Operating Temperature T
OPER
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI
to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
9. AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL-15)
NOTE:
1. Under all conditions V
DDQ
must be less than or equal to V
DD
.
2. V
DDQ
tracks with V
DD
. AC parameters are measured with V
DD
and V
DDQ
tied together.
Symbol Parameter Rating Units NOTE
V
DD
Voltage on V
DD
pin relative to V
SS
-0.4 V ~ 1.975 V V 1,3
V
DDQ
Voltage on V
DDQ
pin relative to V
SS
-0.4 V ~ 1.975 V V 1,3
V
IN,
V
OUT
Voltage on any pin relative to V
SS
-0.4 V ~ 1.975 V V 1
T
STG
Storage Temperature -55 to +100 °C 1, 2
Symbol Parameter rating Unit NOTE
T
OPER
Operating Temperature Range 0 to 95 °C 1, 2, 3
Symbol Parameter
Rating
Units NOTE
Min. Typ. Max.
V
DD
Supply Voltage 1.425 1.5 1.575 V 1,2
V
DDQ
Supply Voltage for Output 1.425 1.5 1.575 V 1,2
- 10 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 1 ] Single-ended AC & DC input levels for Command and Address
NOTE :
1. For input only pins except RESET
, V
REF
= V
REFCA
(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V
REF
may not allow V
REF
to deviate from V
REF
(DC) by more than ± 1% V
DD
(for reference : approx. ± 15mV)
4. For reference : approx. V
DD
/2 ± 15mV
5. V
IH
(dc) is used as a simplified symbol for V
IH.CA
(DC100)
6. V
IL
(dc) is used as a simplified symbol for V
IL.CA
(DC100)
7. V
IH
(ac) is used as a simplified symbol for V
IH.CA
(AC175) and V
IH.CA
(AC150); V
IH.CA
(AC175) value is used when V
REF
+ 175mV is referenced and V
IH.CA
(AC150) value is
used when VREF + 150mV is referenced.
8. V
IL
(ac) is used as a simplified symbol for V
IL.CA
(AC175) and V
IL.CA
(AC150); V
IL.CA
(AC175) value is used when V
REF
- 175mV is referenced and V
IL.CA
(AC150) value is used
when V
REF
- 150mV is referenced.
[ Table 2 ] Single-ended AC & DC input levels for DQ and DM
NOTE :
1. For input only pins except RESET
, V
REF
= V
REFDQ
(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V
REF
may not allow V
REF
to deviate from V
REF
(DC) by more than ± 1% V
DD
(for reference : approx. ± 15mV)
4. For reference : approx. V
DD
/2 ± 15mV
5. V
IH
(dc) is used as a simplified symbol for V
IH.DQ
(DC100)
6. V
IL
(dc) is used as a simplified symbol for V
IL.DQ
(DC100)
7. V
IH
(ac) is used as a simplified symbol for V
IH.DQ
(AC175), V
IH.DQ
(AC150) ; V
IH.DQ
(AC175) value is used when V
REF
+ 175mV is referenced, V
IH.DQ
(AC150) value is used
when V
REF
+ 150mV is referenced.
8. V
IL
(ac) is used as a simplified symbol for V
IL.DQ
(AC175), V
IL.DQ
(AC150) ; V
IL.DQ
(AC175) value is used when V
REF
- 175mV is referenced, V
IL.DQ
(AC150) value is used when
V
REF
- 150mV is referenced.
Symbol Parameter
DDR3-800/1066/1333/1600
Unit NOTE
Min. Max.
V
IH.CA
(DC100)
DC input logic high
V
REF
+ 100 V
DD
mV 1,5
V
IL.CA
(DC100)
DC input logic low
V
SS
V
REF
- 100
mV 1,6
V
IH.CA
(AC175)
AC input logic high
V
REF
+ 175
- mV 1,2,7
V
IL.CA
(AC175)
AC input logic low -
V
REF
- 175
mV 1,2,8
V
IH.CA
(AC150)
AC input logic high
V
REF
+150
- mV 1,2,7
V
IL.CA
(AC150)
AC input logic low -
V
REF
-150
mV 1,2,8
V
REFCA
(DC)
Reference Voltage for ADD,
CMD inputs
0.49*V
DD
0.51*V
DD
V3,4
Symbol Parameter
DDR3-800/1066 DDR3-1333/1600
Unit NOTE
Min. Max. Min. Max.
V
IH.DQ
(DC100)
DC input logic high
V
REF
+ 100 V
DD
V
REF
+ 100 V
DD
mV 1,5
V
IL.DQ
(DC100)
DC input logic low
V
SS
V
REF
- 100 V
SS
V
REF
- 100
mV 1,6
V
IH.DQ
(AC175)
AC input logic high
V
REF
+ 175
- - - mV 1,2,7
V
IL.DQ
(AC175)
AC input logic low -
V
REF
- 175
--mV1,2,8
V
IH.DQ
(AC150)
AC input logic high
V
REF
+ 150
NOTE 2
V
REF
+ 150
NOTE 2 mV 1,2,7
V
IL.DQ
(AC150)
AC input logic low NOTE 2
V
REF
- 150
NOTE 2
V
REF
- 150
mV 1,2,8
V
REF
DQ
(DC)
Reference Voltage for DQ,
DM inputs
0.49*V
DD
0.51*V
DD
0.49*V
DD
0.51*V
DD
V3,4
- 11 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10.2 V
REF
Tolerances.
The dc-tolerance limits and ac-noise limits for the reference voltages V
REFCA
and V
REFDQ
are illustrate in Figure 1. It shows a valid reference voltage
V
REF
(t) as a function of time. (V
REF
stands for V
REFCA
and V
REFDQ
likewise).
V
REF
(DC) is the linear average of V
REF
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V
REF
. Fur-
thermore V
REF
(t) may temporarily deviate from V
REF
(DC) by no more than ± 1% V
DD
.
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements V
IH
(AC), V
IH
(DC), V
IL
(AC) and V
IL
(DC) are dependent on V
REF
.
"V
REF
" shall be understood as V
REF
(DC), as defined in Figure 1.
This clarifies, that dc-variations of V
REF
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for V
REF
(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
REF
ac-noise.
Timing and voltage effects due to ac-noise on V
REF
up to the specified limit (+/-1% of V
DD
) are included in DRAM timings and their associated deratings.
voltage
V
DD
V
SS
time
- 12 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK
use V
IH
/V
IL
(AC) of ADD/CMD and V
REFCA
; for DQS - DQS use V
IH
/V
IL
(AC) of DQs and V
REFDQ
; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK
, DQS, DQS need to be within the respective limits (V
IH
(DC) max, V
IL
(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
Symbol Parameter
DDR3-800/1066/1333/1600
unit NOTE
min max
V
IHdiff
differential input high +0.2 NOTE 3 V 1
V
ILdiff
differential input low NOTE 3 -0.2 V 1
V
IHdiff
(AC)
differential input high ac
2 x (V
IH
(AC) - V
REF
)
NOTE 3 V 2
V
ILdiff
(AC)
differential input low ac NOTE 3
2 x (V
IL
(AC) - V
REF
)
V2
Slew Rate [V/ns]
tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 350mV tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163 -
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
0.0
tDVAC
V
IH
.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
V
IH
.DIFF.AC.MIN
V
IL
.DIFF.MAX
V
IL
.DIFF.AC.MAX
- 13 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK
have to approximately reach V
SEH
min / V
SEL
max (approximately equal to the ac-levels ( V
IH
(AC) / V
IL
(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQS
have to reach V
SEH
min / V
SEL
max (approximately the ac-levels ( V
IH
(AC) / V
IL
(AC) ) for DQ signals) in every half-cycle proceeding and follow-
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
IH
150(AC)/V
IL
150(AC) is used for ADD/CMD
signals, then these ac-levels apply also for the single-ended signals CK and CK
.
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to V
REF
, the single-ended components of differential signals have a requirement
with respect to V
DD
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach V
SEL
max, V
SEH
min has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 4 ] Single-ended levels for CK, DQS, CK
, DQS
NOTE :
1. For CK, CK
use V
IH
/V
IL
(AC) of ADD/CMD; for strobes (DQS, DQS) use V
IH
/V
IL
(AC) of DQs.
2. V
IH
(AC)/V
IL
(AC) for DQs is based on V
REFDQ
; V
IH
(AC)/V
IL
(AC) for ADD/CMD is based on V
REFCA
; if a reduced ac-high or ac-low level is used for a signal group, then the
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK
, DQS, DQS need to be within the respective
limits (V
IH
(DC) max, V
IL
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
Symbol Parameter
DDR3-800/1066/1333/1600
Unit NOTE
Min Max
V
SEH
Single-ended high-level for strobes
(V
DD
/2)+0.175
NOTE3 V 1, 2
Single-ended high-level for CK, CK
(V
DD
/2)+0.175
NOTE3 V 1, 2
V
SEL
Single-ended low-level for strobes NOTE3
(V
DD
/2)-0.175
V1, 2
Single-ended low-level for CK, CK
NOTE3
(V
DD
/2)-0.175
V1, 2
V
DD
or V
DDQ
V
SEH
min
V
DD
/2 or V
DDQ
/2
V
SEL
max
V
SEH
V
SS
or V
SSQ
V
SEL
CK or DQS
time
- 14 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK
and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V
IX
is measured from the actual
cross point of true and complement signal to the mid level between of V
DD
and V
SS
.
Figure 4. V
IX
Definition
[ Table 5 ] Cross point voltage for differential input signals (CK, DQS)
NOTE :
1. Extended range for V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
SEL
/ V
SEH
of at least V
DD
/2
±250 mV, and the differential slew rate of CK-CK
is larger than 3 V/ ns.
10.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
10.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 6 ] Differential input slew rate definition
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK
Symbol Parameter
DDR3-800/1066/1333/1600
Unit NOTE
Min Max
V
IX
Differential Input Cross Point Voltage relative to V
DD
/2 for CK,CK
-150 150 mV
-175 175 mV 1
V
IX
Differential Input Cross Point Voltage relative to V
DD
/2 for DQS,DQS
-150 150 mV
Description
Measured
Defined by
From To
Differential input slew rate for rising edge (CK-CK
and DQS-DQS)
V
ILdiffmax
V
IHdiffmin
V
IHdiffmin
- V
ILdiffmax
Delta TRdiff
Differential input slew rate for falling edge (CK-CK
and DQS-DQS)
V
IHdiffmin
V
ILdiffmax
V
IHdiffmin
- V
ILdiffmax
Delta TFdiff
V
DD
CK, DQS
V
DD
/2
CK, DQS
V
SS
V
IX
V
IX
V
IX
V
IHdiffmin
0
V
ILdiffmax
delta TRdiff
delta TFdiff
- 15 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
11. AC & DC Output Measurement Levels
11.1 Single Ended AC and DC Output Levels
[ Table 7 ] Single Ended AC and DC output levels
NOTE : 1. The swing of +/-0.1 x V
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to V
TT
=V
DDQ
/2.
11.2 Differential AC and DC Output Levels
[ Table 8 ] Differential AC and DC output levels
NOTE : 1. The swing of +/-0.2xV
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to V
TT
=V
DDQ
/2 at each of the differential outputs.
11.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OL
(AC) and V
OH
(AC)
for single ended signals as shown in below.
[ Table 9 ] Single ended Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 10 ] Single ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
Figure 6. Single-ended output slew rate definition
Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE
V
OH
(DC) DC output high measurement level (for IV curve linearity) 0.8 x V
DDQ
V
V
OM
(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V
DDQ
V
V
OL
(DC) DC output low measurement level (for IV curve linearity) 0.2 x V
DDQ
V
V
OH
(AC) AC output high measurement level (for output SR) V
TT
+ 0.1 x V
DDQ
V1
V
OL
(AC) AC output low measurement level (for output SR) V
TT
- 0.1 x V
DDQ
V1
Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE
V
OHdiff
(AC) AC differential output high measurement level (for output SR) +0.2 x V
DDQ
V1
V
OLdiff
(AC) AC differential output low measurement level (for output SR) -0.2 x V
DDQ
V1
Description
Measured
Defined by
From To
Single ended output slew rate for rising edge
V
OL
(AC) V
OH
(AC)
V
OH
(AC)-V
OL
(AC)
Delta TRse
Single ended output slew rate for falling edge
V
OH
(AC) V
OL
(AC)
V
OH
(AC)-V
OL
(AC)
Delta TFse
Parameter Symbol
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Units
Min Max Min Max Min Max Min Max
Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 V/ns
V
OHdiff
(AC)
V
OLdiff
(AC)
delta TRdiffdelta TFdiff
V
TT
- 16 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
11.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OLdiff
(AC) and V
OH-
diff
(AC) for differential signals as shown in below.
[ Table 11 ] Differential Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 12 ] Differential Output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
Figure 7. Differential output slew rate definition
Description
Measured
Defined by
From To
Differential output slew rate for rising edge
V
OLdiff
(AC) V
OHdiff
(AC)
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TRdiff
Differential output slew rate for falling edge
V
OHdiff
(AC) V
OLdiff
(AC)
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TFdiff
Parameter Symbol
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Units
Min Max Min Max Min Max Min Max
Differential output slew rate SRQdiff 5 10 5 10 5 10 5 10 V/ns
V
OHdiff
(AC)
V
OLdiff
(AC)
delta TRdiffdelta TFdiff
V
TT
- 17 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
12. DIMM IDD specification definition
Symbol Description
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
3)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
3)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT
Signal: stable at 0
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable
at HIGH
; Pattern Details: Refer to Component Datasheet for detail pattern
IDD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
4)
; Self-Refresh Temperature Range (SRT): Normal
5)
; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: FLOATING
IDD6ET
Self-Refresh Current: Extended Temperature Range (optional)
6)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
4)
; Self-Refresh Temperature Range (SRT): Extended
5)
; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: FLOATING
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: CL-1; CS: High
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD8
RESET Low Current
RESET : Low; External clock : off; CK and CK
: LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
- 18 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
- 19 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
13. IDD SPEC Table
M471B1G73AH0 : 8GB (1Gx64) Module
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Symbol
CF8
(DDR3-1066@CL=7)
CH9
(DDR3-1333@CL=9)
Unit NOTE
IDD0 600 680 mA 1
IDD1 720 800 mA 1
IDD2P0(slow exit) 240 240 mA
IDD2P1(fast exit) 320 320 mA
IDD2N 400 480 mA
IDD2Q 400 400 mA
IDD3P 400 400 mA
IDD3N 520 600 mA
IDD4R 960 1120 mA 1
IDD4W 1040 1280 mA 1
IDD5B 1440 1600 mA 1
IDD6 240 240 mA
IDD7 1520 1880 mA 1
IDD8 240 240 mA
- 20 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
14. Input/Output Capacitance
14.1 2Rx8 2GB SODIMM
Parameter Symbol
M471B1G73AH0
Units NOTEDDR3-1066 DDR3-1333
Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS
, TDQS, TDQS)
CIO - TBD - TBD pF
Input capacitance (CK and CK)
CCK - TBD - TBD pF
Input capacitance (All other input-only pins) CI - TBD - TBD pF
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Samsung M471B1G73AH0 User manual

Samsung
Brand
Samsung
Model
M471B1G73AH0
Category
Memory modules
Type
User manual
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