Samsung M471B5273BH1-CF8 Specification

Brand: Samsung

Model: M471B5273BH1-CF8

Category: Memory modules

Type: Specification

Rev. 1.03 June 2009

1 of 29

DDR3 SDRAM

Unbuffered SoDIMM

DDR3 SDRAM Specification

204pin Unbuffered SODIMM based on 2Gb B-die

64-bit Non-ECC

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.03 June 2009

2 of 29

DDR3 SDRAM

Unbuffered SoDIMM

1.0 DDR3 Unbuffered SoDIMM Ordering Information .....................................................................5

2.0 Key Features ................................................................................................................................5

3.0 Address Configuration ................................................................................................................5

4.0 x64 DIMM Pin Configurations (Front side/Back Side) ..............................................................6

5.0 Pin Description ............................................................................................................................7

6.0 Input/Output Functional Description .........................................................................................8

7.0 Function Block Diagram: ............................................................................................................9

7.1 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ...................................................9

8.0 Absolute Maximum Ratings ......................................................................................................10

8.1 Absolute Maximum DC Ratings ....................................................................................................10

8.2 DRAM Component Operating Temperature Range ..........................................................................10

9.0 AC & DC Operating Conditions ................................................................................................10

9.1 Recommended DC Operating Conditions (SSTL-15) .......................................................................10

10.0 AC & DC Input Measurement Levels ......................................................................................11

10.1 AC & DC Logic Input Levels for Single-ended Signals ...................................................................11

10.2 V

REF

Tolerances. ......................................................................................................................12

10.3 AC and DC Logic Input Levels for Differential Signals ...................................................................13

10.3.1 Differential Signals Definition ..............................................................................................13

10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................13

10.3.3 Single-ended Requirements for Differential Signals ...............................................................14

10.3.4 Differential Input Cross Point Voltage ...................................................................................15

10.4 Slew Rate Definition for Single Ended Input Signals .....................................................................15

10.5 Slew rate definition for Differential Input Signals ..........................................................................15

11.0 AC & DC Output Measurement Levels ...................................................................................16

11.1 Single Ended AC and DC Output Levels ......................................................................................16

11.2 Differential AC and DC Output Levels ..........................................................................................16

11.3 Single-ended Output Slew Rate ..................................................................................................16

11.4 Differential Output Slew Rate .....................................................................................................17

12.0 IDD specification definition ....................................................................................................18

12.1 IDD SPEC Table ........................................................................................................................20

13.0 Input/Output Capacitance .......................................................................................................20

13.1 2Rx16 1GB SoDIMM ..................................................................................................................20

14.0 Electrical Characteristics and AC timing ..............................................................................21

14.1 Refresh Parameters by Device Density ........................................................................................21

14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................21

14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..............................................22

14.3.1 Speed Bin Table Notes .......................................................................................................23

Table Contents

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DDR3 SDRAM

Unbuffered SoDIMM

15.0 Timing Parameters for DDR3-1066 and DDR3-1333 .............................................................24

15.1 Jitter Notes ..............................................................................................................................27

15.2 Timing Parameter Notes ...........................................................................................................28

16.0 Physical Dimensions :............................................................................................................. 29

16.1 256Mbx8 based 512Mx64 Module (2 Ranks) .................................................................................29

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DDR3 SDRAM

Unbuffered SoDIMM

Revision History

Revision Month Year History

1.0 December 2008 - First Release

1.01 February 2009 - Corrected Module Physical Dimensions.

1.02 February 2009 - Added Tolerances to Physical Dimensions

1.03 June 2009 - Corrected Typo

Rev. 1.03 June 2009

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DDR3 SDRAM

Unbuffered SoDIMM

1.0 DDR3 Unbuffered SoDIMM Ordering Information

Note :

* ## : F8 / H9

** F8 : 1066Mbps 7-7-7, H9 : 1333Mbps 9-9-9

2.0 Key Features

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

DDQ

= 1.5V ± 0.075V

• 400 MHz f

for 800Mb/sec/pin, 533MHz f

for 1066Mb/sec/pin, 667MHz f

for 1333Mb/sec/pin

• 8 independent internal bank

• Programmable CAS

Latency: 6,7,8,9

• Programmable Additive Latency(Posted CAS

) : 0, CL - 2, or CL - 1 clock

• Programmable CAS

Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333)

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower than T

CASE

85°C, 3.9us at 85°C < T

CASE

< 95 °C

• Asynchronous Reset

3.0 Address Configuration

Part Number Density Organization Component Composition

Number of

Rank

Height

M471B5273BH1-CF8/H9 4GB 512Mx64 256Mx8(K4B2G0846B-HC##)*16 2 30mm

Speed

DDR3-1066 DDR3-1333

Unit

7-7-7 9-9-9

tCK(min) 1.875 1.5 ns

CAS Latency 79tCK

tRCD(min) 13.125 13.5 ns

tRP(min) 13.125 13.5 ns

tRAS(min) 37.5 36 ns

tRC(min) 50.625 49.5 ns

Organization Row Address Column Address Bank Address Auto Precharge

256x8(2Gb) based Module A0-A14 A0-A9 BA0-BA2 A10/AP

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DDR3 SDRAM

Unbuffered SoDIMM

4.0 x64 DIMM Pin Configurations (Front side/Back Side)

Note :

1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use

2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.

3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

REFDQ

139

140 DQ38

4DQ4 KEY 141 DQ34 142 DQ39

5DQ06DQ573CKE074CKE1

143

DQ35 144

7DQ18

145

146 DQ44

10 DQS077 NC 78

A15

147

DQ40 148 DQ45

11 DM0 12DQS079 BA2 80

A14

149

DQ41 150

151

152 DQS5

15 DQ2 16 DQ6 83 A12/BC

84 A11 153 DM5 154 DQS5

17 DQ3 18 DQ7 85 A9 86 A7 155

156

157DQ42158DQ46

21DQ822DQ1289A890A6159DQ43160DQ47

23DQ924DQ1391A592A4161

162

163DQ48164DQ52

27 DQS

1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53

29 DQS1 30 RESET

97 A1 98 A0 167

168

100

169

DQS

170

DM6

33 DQ10 34 DQ14 101 CK0 102 CK1 171

DQS6

172

35 DQ11 36 DQ15 103 CK0104CK1173

174 DQ54

105

106

175DQ50176DQ55

39 DQ16 40 DQ20

107 A10/AP 108 BA1 177 DQ51 178

41 DQ17 42 DQ21 109 BA0 110 RAS 179

180 DQ60

111

112

181DQ56182DQ61

45 DQS

246 DM2113 WE 114 S0 183 DQ57 184

47 DQS2 48

115 CAS 116 ODT0 185

186 DQS7

50 DQ22 117

118

187 DM7 188 DQS7

50 DQ18 52 DQ23

119

A13

120ODT1189

190

53 DQ19 54

121 S1 122 NC 191DQ58192DQ62

56 DQ28 123

124

193DQ59194DQ63

57 DQ24 58 DQ29

125 TEST 126

REFCA

195

196

59 DQ25 60

127

128

197 SA0 198 NC

62 DQS3 129 DQ32 130 DQ36 199

DDSPD

200 SDA

63 DM3 64 DQS3

131

DQ33 132 DQ37 201 SA1 202 SCL

133

134

203

204

67 DQ26 68 DQ30

135

DQS4136 DM4

69 DQ27 70 DQ31

137 DQS4 138

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DDR3 SDRAM

Unbuffered SoDIMM

5.0 Pin Description

*The V

and V

DDQ

pins are tied common to a single power-plane on these designs.

Pin Name Description Number Pin Name Description Number

CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64

0, CK1 Clock Inputs, negative line 2 DM0-DM7

Data Masks/ Data strobes,

Termination data strobes

CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8

RAS

Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8

CAS

Column Address Strobe 1 RESET Reset Pin 1

Write Enable 1 TEST

Logic Analyzer specific test pin (No connect

on SODIMM)

0, S1 Chip Selects 2

Core and I/O Power 18

A0-A9, A11,

A13-A15

Address Inputs 14

Ground 52

A10/AP Address Input/Autoprecharge 1

REFDQ

REFCA

Input/Output Reference 2

A12/BC

Address Input/Burst chop 1

DDSPD

SPD and Temp sensor Power 1

BA0-BA2 SDRAM Bank Addresses 3

Termination Voltage 2

ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3

SCL Serial Presence Detect (SPD) Clock Input 1 Total 204

SDA SPD Data Input/Output 1

SA0-SA1 SPD Address 2

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DDR3 SDRAM

Unbuffered SoDIMM

6.0 Input/Output Functional Description

Symbol Type Function

CK0-CK1

CK0

-CK1

Input

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and

falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-

tions is synchronized to the input clock.

CKE0-CKE1 Input

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,

CKE low initiates the Power Down mode or the Self Refresh mode.

0-S1 Input

Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is

selected by S

0; Rank 1 is selected by S1.

AS, CAS, WE Input

When sampled at the cross point of the rising edge of CK and falling edge of CK

, signals CAS, RAS, and WE define

the operation to be executed by the SDRAM.

BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.

ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.

A0-A9,

A10/AP,

A11

A12/BC

A13-A15

Input

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of

CK and falling edge of CK

. During a Read or Write command cycle, defines the column address when sampled at the

cross point of the rising edge of CK and falling edge of CK

. In addition to the column address, AP is used to invoke

autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-

BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,

AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-

charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-

charge.A12(BC

) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be

performed (HIGH, no burst chop; LOW, burst chopped)

DQ0-DQ63 I/O Data Input/Output pins.

DM0-DM7 Input

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input

data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.

DQS0-DQS7

DQS

0-DQS7

I/O

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is

sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3

SDRAMs and is sent at the leading edge of the data window. DQS

signals are complements, and timing is relative to

the crosspoint of respective DQS and DQS

DDSPD,

Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

REFDQ,

REFCA

Supply Reference voltage for SSTL15 inputs.

SDA I/O

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be

connected from the SDA bus line to V

DDSPD

on the system planar to act as a pull up.

SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.

TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules

RESET

Input RESET In Active Low This signal resets the DDR3 SDRAM

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DDR3 SDRAM

Unbuffered SoDIMM

7.0 Function Block Diagram:

7.1 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

RAS

CAS

CK1

CKE1

ODT1

A[0:N]

/BA[0:N]

CK0

CKE0

ODT0

DQS3

DM3

DQS

D11

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

DQ[24:31]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

Vtt

Rank0

Rank1

Note :

1. DQ wiring may differ from that shown

however ,DQ, DM, DQS and DQS

relationships are maintained as shown

D0 - D15

REFCA

DDSPD

SPD

CK0

REFDQ

D0 - D15

D0 - D15, SPD

CK1

CK0

CK1

RESET

D8 - D15

D0 - D7

D8 - D15

D0 - D7

D6D12D3D9

Address and Controllines

DQS

DQ[0:7]

DQS1

DM1

DQS

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240

Ω

± 1%

DQ[8:15]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS0

DM0

DQS

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

DQ[0:7]

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS2

DM2

DQS

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

DQ[16:23]

D10

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

D12

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS

D14

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240

Ω

± 1%

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS

D15

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS

D13

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

DQ[0:7]

240Ω

± 1%

RAS

CAS

CKE

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

DQS

DQ[0:7]

DQS4

DM4

DQ[32:39]

DQS6

DM6

DQ[48:55]

DQS7

DM7

DQ[56:63]

DQS5

DM5

DQ[40:47]

D7D5D10D8

D15D13D2D0

D14D4D11D1

Vtt

SA0

SA1

SCL

SDA

SCL

(SPD)

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DDR3 SDRAM

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8.0 Absolute Maximum Ratings

8.1 Absolute Maximum DC Ratings

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

3. V

and V

DDQ

must be within 300mV of each other at all times;and V

REF

must be not greater than 0.6 x V

DDQ

, When V

and V

DDQ

are less than

500mV; V

REF

may be equal to or less than 300mV.

8.2 DRAM Component Operating Temperature Range

Note :

1. Operating Temperature T

OPER

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the

JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-

perature must be maintained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-

teed in this range, but the following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component

with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with

Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7

= 0b)

9.0 AC & DC Operating Conditions

9.1 Recommended DC Operating Conditions (SSTL-15)

Note :

1. Under all conditions V

DDQ

must be less than or equal to V

2. V

DDQ

tracks with V

. AC parameters are measured with V

and V

DDQ

tied together.

Symbol Parameter Rating Units Notes

Voltage on V

pin relative to V

-0.4 V ~ 1.975 V V 1,3

DDQ

Voltage on V

DDQ

pin relative to V

-0.4 V ~ 1.975 V V 1,3

IN,

OUT

Voltage on any pin relative to V

-0.4 V ~ 1.975 V V 1

STG

Storage Temperature -55 to +100 °C 1, 2

Symbol Parameter rating Unit Notes

OPER

Operating Temperature Range 0 to 95 °C 1, 2, 3

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

Supply Voltage 1.425 1.5 1.575 V 1,2

DDQ

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

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10.0 AC & DC Input Measurement Levels

10.1 AC & DC Logic Input Levels for Single-ended Signals

Single Ended AC and DC input levels for Command and Address

Note :

1. For input only pins except RESET

, V

REF

= V

REFCA

(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The AC peak noise on V

REF

may not allow V

REF

to deviate from V

REF

(DC) by more than ± 1% V

(for reference : approx. ± 15mV)

4. For reference : approx. V

/2 ± 15mV

Single Ended AC and DC input levels for DQ and DM

Note :

1. For input only pins except RESET

, V

REF

= V

REFDQ

(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The AC peak noise on V

REF

may not allow V

REF

to deviate from V

REF

(DC) by more than ± 1% V

(for reference : approx. ± 15mV)

4. For reference : approx. V

/2 ± 15mV

5. Single ended swing requirement for DQS - DQS

is 350mV (peak to peak). Differential swing requirement for DQS - DQS is 700mV (peak to peak).

Symbol Parameter

DDR3-800/1066 DDR3-1333

Unit Notes

Min. Max. Min. Max.

IH.CA

(DC)

DC input logic high

REF

+ 100 V

REF

+ 100 V

mV 1

IL.CA

(DC)

DC input logic low

REF

- 100 V

REF

- 100

mV 1

IH.CA

(AC)

AC input logic high

REF

+ 175

REF

+ 175

-mV1,2

IL.CA

(AC)

AC input logic low -

REF

- 175

REF

- 175

mV 1,2

IH.CA

(AC150)

AC input logic high

REF

+150

REF

+150

-mV1,2

IL.CA

(AC150)

AC input logic low -

REF

-150

REF

-150

mV 1,2

REFCA

(DC)

Reference Voltage for ADD,

CMD inputs

0.49*V

0.51*V

0.49*V

0.51*V

V3,4

Symbol Parameter

DDR3-1066 DDR3-1333

Unit Notes

Min. Max. Min. Max.

IH.DQ

(DC100)

DC input logic high

REF

+ 100 V

REF

+ 100 V

mV 1

IL.DQ

(DC100)

DC input logic low

REF

- 100 V

REF

- 100

mV 1

IH.DQ

(AC175)

AC input logic high

REF

+ 175

REF

+ 150

- mV 1,2,5

IL.DQ

(AC175)

AC input logic low -

REF

- 175

REF

- 150

mV 1,2,5

IH.DQ

(AC150)

AC input logic high

REF

+ 150

Note - - mV 1,2,5

IL.DQ

(AC150)

AC input logic low Note 2

REF

- 150

- - mV 1,2,5

REF

(DC)

I/O Reference Voltage(DQ)

0.49*V

0.51*V

0.49*V

0.51*V

V3,4

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DDR3 SDRAM

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10.2 V

REF

Tolerances.

The dc-tolerance limits and ac-noise limits for the reference voltages V

REFCA

and V

REFDQ

are illustrate in Figure 1. It shows a valid reference voltage

REF

(t) as a function of time. (V

REF

stands for V

REFCA

and V

REFDQ

likewise).

REF

(DC) is the linear average of V

REF

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V

REF

. Fur-

thermore V

REF

(t) may temporarily deviate from V

REF

(DC) by no more than ± 1% V

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements V

(AC), V

(DC), V

(AC) and V

(DC) are dependent on V

REF

" shall be understood as V

REF

(DC), as defined in Figure 1.

This clarifies, that dc-variations of V

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

which setup and hold is measured. System timing and voltage budgets need to account for V

REF

(DC) deviations from the optimum position within the

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

REF

ac-noise.

Timing and voltage effects due to ac-noise on V

REF

up to the specified limit (+/-1% of V

) are included in DRAM timings and their associated deratings.

voltage

time

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DDR3 SDRAM

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10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

Notes:

1. Used to define a differential signal slew-rate.

2. for CK - CK

use V

(AC) of ADD/CMD and V

REFCA

; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use V

(AC) of DQs and V

REFDQ

; if a

reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (V

(DC) max, V

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Under-

sheet Specification"

Allowed time before ringback (tDVAC) for CK - CK

and DQS - DQS.

Symbol Parameter

DDR3-800/1066/1333

unit Note

min max

IHdiff

differential input high +0.2 note 3 V 1

ILdiff

differential input low note 3 -0.2 V 1

IHdiff

(AC)

differential input high ac

2 x (V

(AC)-V

REF

)

note 3 V 2

ILdiff

(AC)

differential input low ac note 3

2 x (V

REF

- V

(AC))

Slew Rate [V/ns]

tDVAC [ps] @ |V

IH/Ldiff

(AC)| = 350mV tDVAC [ps] @ |V

IH/Ldiff

(AC)| = 300mV

min max min max

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163 -

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

time

tDVAC

.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

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10.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for

single-ended signals.

CK and CK

have to approximately reach V

SEH

min / V

SEL

max (approximately equal to the ac-levels ( V

(AC) / V

(AC) ) for ADD/CMD signals) in every

half-cycle.

DQS, DQSL, DQSU, DQS

, DQSL have to reach V

SEH

min / V

SEL

max (approximately the ac-levels ( V

(AC) / V

(AC) ) for DQ signals) in every half-cycle

proceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

150(AC)/V

150(AC) is used for ADD/CMD

signals, then these ac-levels apply also for the single-ended signals CK and CK

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

REF

, the single-ended components of differential signals have a requirement

with respect to V

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

ended components of differential signals the requirement to reach V

SEL

max, V

SEH

min has no bearing on timing, but adds a restriction on the common

mode characteristics of these signals.

Single ended levels for CK, DQS, DQSL, DQSU, CK

, DQS, DQSL or DQSU

Notes:

1. For CK, CK

use V

(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V

(AC) of DQs.

2. V

(AC)/V

(AC) for DQs is based on V

REFDQ

; V

(AC)/V

(AC) for ADD/CMD is based on V

REFCA

; if a reduced ac-high or ac-low level is used for a

signal group, then the reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (V

(DC) max, V

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot

Specification"

Symbol Parameter

DDR3-800/1066/1333

Unit Notes

Min Max

SEH

Single-ended high-level for strobes

/2)+0.175

Note3 V 1, 2

Single-ended high-level for CK, CK

/2)+0.175

Note3 V 1, 2

SEL

Single-ended low-level for strobes Note3

/2)-0.175

V1, 2

Single-ended low-level for CK, CK

Note3

/2)-0.175

V1, 2

or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

or V

SSQ

SEL

CK or DQS

time

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10.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input

signals (CK, CK

and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V

is measured from the actual

cross point of true and complement signal to the mid level between of V

and V

Figure 4. V

Definition

Cross point voltage for differential input signals (CK, DQS)

Note :

1. Extended range for V

is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V

SEL

SEH

of at least V

/2 ±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.

10.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.

See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

10.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

Differential input slew rate definition

Note : The differential signal (i.e. CK - CK

and DQS - DQS) must be linear between these thresholds

Figure 5. Differential input slew rate definition for DQS, DQS

and CK, CK

Symbol Parameter

DDR3-800/1066/1333

Unit Notes

Min Max

Differential Input Cross Point Voltage relative to V

/2 for CK,CK

-150 150 mV

-175 175 mV 1

Differential Input Cross Point Voltage relative to V

/2 for DQS,DQS

-150 150 mV

Description

Measured

Defined by

From To

Differential input slew rate for rising edge (CK-CK

and DQS-DQS)

ILdiffmax

IHdiffmin

- V

ILdiffmax

Delta TRdiff

Differential input slew rate for falling edge (CK-CK

and DQS-DQS)

IHdiffmin

ILdiffmax

IHdiffmin

- V

ILdiffmax

Delta TFdiff

CK, DQS

IHdiffmin

ILdiffmax

delta TRdiff

delta TFdiff

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11.0 AC & DC Output Measurement Levels

11.1 Single Ended AC and DC Output Levels

Single Ended AC and DC output levels

Note : 1. The swing of +/-0.1 x V

DDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω

and an effective test load of 25Ω to V

DDQ

/2.

11.2 Differential AC and DC Output Levels

Differential AC and DC output levels

Note : 1. The swing of +/-0.2xV

DDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω

and an effective test load of 25Ω to V

DDQ

/2 at each of the differential outputs.

11.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) and V

(AC)

for single ended signals as shown in below.

Single ended Output slew rate definition

Note : Output slew rate is verified by design and characterization, and may not be subject to production test.

Single ended output slew rate

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output

se : Singe-ended Signals

For Ron = RZQ/7 setting

Figure 6. Single-ended output slew rate definition

Symbol Parameter DDR3-800/1066/1333 Units Notes

(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

DDQ

(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

DDQ

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

DDQ

(AC) AC output high measurement level (for output SR) V

+ 0.1 x V

DDQ

(AC) AC output low measurement level (for output SR) V

- 0.1 x V

DDQ

Symbol Parameter DDR3-800/1066/1333 Units Notes

OHdiff

(AC) AC differential output high measurement level (for output SR) +0.2 x V

DDQ

OLdiff

(AC) AC differential output low measurement level (for output SR) -0.2 x V

DDQ

Description

Measured

Defined by

From To

Single ended output slew rate for rising edge

(AC) V

(AC)

(AC)-V

(AC)

Delta TRse

Single ended output slew rate for falling edge

(AC) V

(AC)

(AC)-V

(AC)

Delta TFse

Parameter Symbol

DDR3-1066 DDR3-1333

Units

Min Max Min Max

Single ended output slew rate SRQse 2.5 5 2.5 5 V/ns

OH(AC)

OL(AC)

delta TRsedelta TFse

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11.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

OLdiff

(AC) and

OHdiff

(AC) for differential signals as shown in below.

Differential Output slew rate definition

Note : Output slew rate is verified by design and characterization, and may not be subject to production test.

Differential Output slew rate

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output

diff : Singe-ended Signals

Figure 7. Differential output slew rate definition

Description

Measured

Defined by

From To

Differential output slew rate for rising edge

OLdiff

(AC) V

OHdiff

(AC)

OHdiff

(AC)-V

OLdiff

(AC)

Delta TRdiff

Differential output slew rate for falling edge

OHdiff

(AC) V

OLdiff

(AC)

OHdiff

(AC)-V

OLdiff

(AC)

Delta TFdiff

Parameter Symbol

DDR3-1066 DDR3-1333

Units

Min Max Min Max

Differential output slew rate SRQse 5 10 5 10 V/ns

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

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12.0 IDD specification definition

Symbol Description

IDD0

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: AC Timing Table ; BL: 8

; AL: 0; CS: High between ACT and PRE; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer

and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

IDD1

Operating One Bank Active-Read-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: AC Timing Table ; BL: 8

; AL: 0; CS: High between ACT, RD and PRE; Command, Address,

Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and

RTT: Enabled in Mode Registers

; ODT Signal: stable at 0;

IDD2N

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;

Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

DD2NT

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;

Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: toggling

DDQ2NT

(optional)

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

IDD2P0

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:

FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Precharge

Power Down Mode: Slow Exit

IDD2P1

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data

IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Precharge

Power Down Mode: Fast Exit

IDD2Q

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:

FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

IDD3N

Active Standby Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling

according to Table 34 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

; ODT Sig-

nal: stable at 0

IDD3P

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:

FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

IDD4R

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially tog-

gling ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all

banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registers

; ODT

Signal: stable at 0

IDDQ4R

(optional)

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

IDD4W

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8

; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially tog-

gling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR com-

mands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at HIGH

IDD5B

Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: AC Timing Table ; BL: 8

; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: par-

tially toggling according to Table 38 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT:

Enabled in Mode Registers

; ODT Signal: stable at 0

IDD6

Self Refresh Current: Normal Temperature Range

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled

; Self-Refresh Temperature Range (SRT): Normal

; CKE: Low; External clock: Off; CK and CK:

LOW; CL: AC Timing Table ; BL: 8

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh opera-

tion; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: FLOATING

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a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

g) IDD current measure method and detail patterns are described on DDR3 component datasheet

Symbol Description

IDD6ET

Self-Refresh Current: Extended Temperature Range (optional)

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled

; Self-Refresh Temperature Range (SRT): Extended

; CKE: Low; External clock: Off; CK and CK:

LOW; CL: AC Timing Table ; BL: 8

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Tempera-

ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: FLOATING

IDD6TC

Auto Self-Refresh Current (optional)

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled

; Self-Refresh Temperature Range (SRT): Normal

; CKE: Low; External clock: Off; CK and CK:

LOW; CL: AC Timing Table ; BL: 8

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto

Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: FLOATING

IDD7

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: AC Timing Table; BL: 8

; AL: CL-1; CS: High between ACT and RDA; Com-

mand, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0;

Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Reg-

isters

; ODT Signal: stable at 0