Compaq 21264, EV68A User manual

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Compaq Computer Corporation
Shrewsbury, Massachusetts
21264/EV68A Microprocessor
Hardware Reference Manual
Part Number: DS–0038B–TE
This manual is directly derived from the internal 21264/EV68A Specifications, Revi-
sion 1.1. You can access this hardware reference manual in PDF format from the
following site:
ftp://ftp.compaq.com/pub/products/alphaCPUdocs
Revision/Update Information: Revision 1.1, March 2002
March 2002
The information in this publication is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL
ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAM-
AGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS
INFORMATION IS PROVIDED “AS IS” AND COMPAQ COMPUTER CORPORATION DISCLAIMS ANY
WARRANTIES, EXPRESS,IMPLIED OR STATUTORY AND EXPRESSLY DISCLAIMS THE IMPLIED WAR-
RANTIES OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST
INFRINGEMENT.
This publication contains information protected by copyright. No part of this publication may be photocopied or
reproduced in any form without prior written consent from Compaq Computer Corporation.
© Compaq Computer Corporation 2002.
All rights reserved. Printed in the U.S.A.
21264/EV68A Hardware Reference Manual
COMPAQ, the Compaq logo, the Digital logo, and VAX Registered in United States Patent and Trademark Office.
Pentium is a registered trademark of Intel Corporation.
Other product names mentioned herein may be trademarks and/or registered trademarks of their respective compa-
nies.
21264/EV68A Hardware Reference Manual
iii
Table of Contents
Preface
1 Introduction
1.1 TheArchitecture.......................................................... 11
1.1.1 Addressing........................................................... 12
1.1.2 Integer Data Types. . . .................................................. 12
1.1.3 Floating-PointDataTypes............................................... 12
1.2 21264/EV68A Microprocessor Features . . ...................................... 13
2 Internal Architecture
2.1 21264/EV68A Microarchitecture . . ............................................ 21
2.1.1 InstructionFetch,Issue,andRetireUnit.................................... 22
2.1.1.1 Virtual Program Counter Logic . . ...................................... 22
2.1.1.2 BranchPredictor................................................... 23
2.1.1.3 Instruction-StreamTranslationBuffer................................... 25
2.1.1.4 InstructionFetchLogic.............................................. 26
2.1.1.5 RegisterRenameMaps ............................................. 26
2.1.1.6 Integer Issue Queue ................................................ 26
2.1.1.7 Floating-Point Issue Queue .......................................... 27
2.1.1.8 Exception and Interrupt Logic . . . ...................................... 28
2.1.1.9 Retire Logic....................................................... 28
2.1.2 Integer Execution Unit .................................................. 28
2.1.3 Floating-PointExecutionUnit............................................. 210
2.1.4 ExternalCacheandSystemInterfaceUnit .................................. 211
2.1.4.1 VictimAddressFileandVictimDataFile................................ 211
2.1.4.2 I/OWriteBuffer.................................................... 211
2.1.4.3 Probe Queue...................................................... 211
2.1.4.4 DuplicateDcacheTagArray.......................................... 211
2.1.5 OnchipCaches........................................................ 211
2.1.5.1 InstructionCache.................................................. 211
2.1.5.2 DataCache....................................................... 212
2.1.6 MemoryReferenceUnit................................................. 212
2.1.6.1 LoadQueue ...................................................... 213
2.1.6.2 StoreQueue...................................................... 213
2.1.6.3 MissAddressFile.................................................. 213
2.1.6.4 DstreamTranslationBuffer........................................... 213
2.1.7 SROMInterface....................................................... 213
2.2 PipelineOrganization ...................................................... 213
2.2.1 PipelineAborts........................................................ 216
2.3 InstructionIssueRules..................................................... 216
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2.3.1 InstructionGroupDefinitions............................................. 217
2.3.2 EboxSlotting......................................................... 218
2.3.3 InstructionLatencies ................................................... 220
2.4 InstructionRetireRules..................................................... 221
2.4.1 Floating-PointDivide/SquareRootEarlyRetire............................... 222
2.5 RetireofOperateInstructionsintoR31/F31..................................... 222
2.6 LoadInstructionstoR31andF31............................................. 223
2.6.1 NormalPrefetch:LDBU,LDF,LDG,LDL,LDT,LDWU,HW_LDLInstructions....... 223
2.6.2 PrefetchwithModifyIntent:LDSInstruction ................................. 223
2.6.3 Prefetch,EvictNext:LDQandHW_LDQInstructions.......................... 224
2.7 SpecialCasesofAlphaInstructionExecution.................................... 224
2.7.1 LoadHitSpeculation................................................... 224
2.7.2 Floating-PointStoreInstructions.......................................... 226
2.7.3 CMOVInstruction...................................................... 226
2.8 MemoryandI/OAddressSpaceInstructions.................................... 227
2.8.1 MemoryAddressSpaceLoadInstructions .................................. 227
2.8.2 I/O Address Space Load Instructions. ...................................... 227
2.8.3 MemoryAddressSpaceStoreInstructions.................................. 228
2.8.4 I/OAddressSpaceStoreInstructions...................................... 229
2.9 MAFMemoryAddressSpaceMergingRules.................................... 230
2.10 InstructionOrdering........................................................ 230
2.11 ReplayTraps............................................................. 231
2.11.1 MboxOrderTraps..................................................... 231
2.11.1.1 Load-LoadOrderTrap .............................................. 231
2.11.1.2 Store-LoadOrderTrap.............................................. 231
2.11.2 OtherMboxReplayTraps............................................... 232
2.12 I/OWriteBufferandtheWMBInstruction....................................... 232
2.12.1 MemoryBarrier(MB/WMB/TBFillFlow).................................... 232
2.12.1.1 MBInstructionProcessing........................................... 233
2.12.1.2 WMBInstructionProcessing.......................................... 233
2.12.1.3 TBFillFlow....................................................... 234
2.13 Performance Measurement Support—Performance Counters . ...................... 235
2.14 Floating-PointControlRegister............................................... 235
2.15 AMASKandIMPLVERInstructionValues ...................................... 237
2.15.1 AMASK.............................................................. 238
2.15.2 IMPLVER............................................................ 238
2.16 DesignExamples ......................................................... 238
3 Hardware Interface
3.1 21264/EV68A Microprocessor Logic Symbol . . . ................................. 31
3.2 21264/EV68A Signal Names and Functions..................................... 33
3.3 PinAssignments.......................................................... 38
3.4 MechanicalSpecifications................................................... 317
3.5 21264/EV68A Packaging . .................................................. 318
4 Cache and External Interfaces
4.1 IntroductiontotheExternalInterfaces.......................................... 41
4.1.1 SystemInterface ...................................................... 43
4.1.1.1 CommandsandAddresses........................................... 44
4.1.2 Second-Level Cache (Bcache) Interface . . . ................................. 44
4.2 PhysicalAddressConsiderations............................................. 44
4.3 BcacheStructure.......................................................... 47
4.3.1 Bcache Interface Signals ................................................ 47
4.3.2 SystemDuplicateTagStores............................................. 47
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4.4 VictimDataBuffer......................................................... 48
4.5 Cache Coherency . . ....................................................... 48
4.5.1 Cache Coherency Basics................................................ 48
4.5.2 CacheBlockStates.................................................... 49
4.5.3 CacheBlockStateTransitions............................................ 410
4.5.4 UsingSysDcCommands................................................ 411
4.5.5 DcacheStatesandDuplicateTags........................................ 413
4.6 LockMechanism.......................................................... 414
4.6.1 In-OrderProcessingofLDx_L/STx_CInstructions ............................ 415
4.6.2 InternalEvictionofLDx_LBlocks.......................................... 415
4.6.3 LivenessandFairness.................................................. 415
4.6.4 ManagingSpeculativeStoreIssueswithMultiprocessorSystems ................ 416
4.7 SystemPort.............................................................. 416
4.7.1 SystemPortPins...................................................... 417
4.7.2 ProgrammingtheSystemInterfaceClocks.................................. 418
4.7.3 21264/EV68A-to-System Commands ...................................... 419
4.7.3.1 BankInterleaveonCacheBlockBoundaryMode ......................... 419
4.7.3.2 PageHitMode .................................................... 420
4.7.4 21264/EV68A-to-System Commands Descriptions . ........................... 421
4.7.5 ProbeResponse Commands (Command[4:0] = 00001). . ....................... 424
4.7.6 SysAckand21264/EV68A-to-SystemCommandsFlowControl.................. 425
4.7.7 System-to-21264/EV68A Commands ...................................... 426
4.7.7.1 Probe Commands (Four Cycles) ...................................... 426
4.7.7.2 Data Transfer Commands (Two Cycles)................................. 428
4.7.8 DataMovementInandOutofthe21264/EV68A.............................. 430
4.7.8.1 21264/EV68A Clock Basics .......................................... 430
4.7.8.2 FastDataMode ................................................... 431
4.7.8.3 FastDataDisableMode............................................. 433
4.7.8.4 SysDataInValid_LandSysDataOutValid_L.............................. 434
4.7.8.5 SysFillValid_L..................................................... 435
4.7.8.6 Data Wrapping . . .................................................. 436
4.7.9 NonexistentMemoryProcessing.......................................... 438
4.7.10 OrderingofSystemPortTransactions...................................... 440
4.7.10.1 21264/EV68A Commands and System Probes ........................... 440
4.7.10.2 System Probes and SysDc Commands ................................. 442
4.8 BcachePort.............................................................. 442
4.8.1 BcachePortPins...................................................... 443
4.8.2 BcacheClocking ...................................................... 444
4.8.2.1 SettingthePeriodoftheCacheClock.................................. 445
4.8.3 BcacheTransactions................................................... 447
4.8.3.1 BcacheDataReadandTagReadTransactions .......................... 447
4.8.3.2 BcacheDataWriteTransactions ...................................... 448
4.8.3.3 BubblesontheBcacheDataBus...................................... 449
4.8.4 PinDescriptions....................................................... 450
4.8.4.1 BcAdd_H[23:4] . . .................................................. 451
4.8.4.2 BcacheControlPins................................................ 451
4.8.4.3 BcDataInClk_HandBcTagInClk_H .................................... 453
4.8.5 BcacheBanking....................................................... 453
4.8.6 Disabling the Bcache for Debugging . ...................................... 453
4.9 Interrupts................................................................ 454
5 Internal Processor Registers
5.1 EboxIPRs............................................................... 53
5.1.1 CycleCounterRegister–CC............................................. 53
5.1.2 CycleCounterControlRegister–CC_CTL.................................. 53
5.1.3 VirtualAddressRegister–VA............................................ 54
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21264/EV68A Hardware Reference Manual
5.1.4 VirtualAddressControlRegister–VA_CTL ................................. 54
5.1.5 VirtualAddressFormatRegister–VA_FORM................................ 55
5.2 IboxIPRs................................................................ 56
5.2.1 ITBTagArrayWriteRegister–ITB_TAG................................... 56
5.2.2 ITBPTEArrayWriteRegister–ITB_PTE................................... 56
5.2.3 ITBInvalidateAllProcess(ASM=0)Register–ITB_IAP........................ 57
5.2.4 ITBInvalidateAllRegister–ITB_IA........................................ 57
5.2.5 ITBInvalidateSingleRegister–ITB_IS..................................... 57
5.2.6 ProfileMePCRegister–PMPC........................................... 58
5.2.7 ExceptionAddressRegister–EXC_ADDR.................................. 58
5.2.8 InstructionVirtualAddressFormatRegister—IVA_FORM...................... 59
5.2.9 InterruptEnableandCurrentProcessorModeRegister–IER_CM................ 59
5.2.10 SoftwareInterruptRequestRegister–SIRR................................. 510
5.2.11 InterruptSummaryRegister–ISUM....................................... 511
5.2.12 HardwareInterruptClearRegister–HW_INT_CLR........................... 512
5.2.13 ExceptionSummaryRegister–EXC_SUM.................................. 513
5.2.14 PAL Base Register – PAL_BASE . . . ...................................... 515
5.2.15 IboxControlRegister–I_CTL............................................ 515
5.2.16 IboxStatusRegister–I_STAT............................................ 518
5.2.17 IcacheFlushRegister–IC_FLUSH........................................ 521
5.2.18 IcacheFlushASMRegister–IC_FLUSH_ASM .............................. 521
5.2.19 ClearVirtual-to-PhysicalMapRegister–CLR_MAP........................... 521
5.2.20 SleepModeRegister–SLEEP........................................... 521
5.2.21 ProcessContextRegister–PCTX......................................... 521
5.2.22 PerformanceCounterControlRegister–PCTR_CTL.......................... 523
5.3 MboxIPRs............................................................... 525
5.3.1 DTBTagArrayWriteRegisters0and1–DTB_TAG0,DTB_TAG1............... 525
5.3.2 DTBPTEArrayWriteRegisters0and1–DTB_PTE0,DTB_PTE1............... 526
5.3.3 DTBAlternateProcessorModeRegister–DTB_ALTMODE..................... 526
5.3.4 DstreamTBInvalidateAllProcess(ASM=0)Register–DTB_IAP................ 527
5.3.5 DstreamTBInvalidateAllRegister–DTB_IA................................ 527
5.3.6 DstreamTBInvalidateSingleRegisters0and1–DTB_IS0,1................... 527
5.3.7 DstreamTBAddressSpaceNumberRegisters0and1–DTB_ASN0,1........... 528
5.3.8 Memory Management Status Register – MM_STAT ........................... 528
5.3.9 MboxControlRegister–M_CTL.......................................... 529
5.3.10 DcacheControlRegister–DC_CTL....................................... 530
5.3.11 DcacheStatusRegister–DC_STAT....................................... 531
5.4 CboxCSRsandIPRs...................................................... 532
5.4.1 CboxDataRegister–C_DATA........................................... 533
5.4.2 CboxShiftRegister–C_SHFT ........................................... 533
5.4.3 CboxWRITE_ONCEChainDescription .................................... 533
5.4.4 CboxWRITE_MANYChainDescription .................................... 538
5.4.5 CboxReadRegister(IPR)Description ..................................... 541
6 Privileged Architecture Library Code
6.1 PALcodeDescription....................................................... 61
6.2 PALmodeEnvironment..................................................... 62
6.3 RequiredPALcodeFunctionCodes........................................... 63
6.4 Opcodes Reserved for PALcode. . ............................................ 63
6.4.1 HW_LDInstruction..................................................... 63
6.4.2 HW_STInstruction..................................................... 64
6.4.3 HW_RETInstruction ................................................... 65
6.4.4 HW_MFPRandHW_MTPRInstructions.................................... 66
6.5 InternalProcessorRegisterAccessMechanisms................................. 67
6.5.1 IPR Scoreboard Bits. . .................................................. 68
6.5.2 HardwareStructureofExplicitlyWrittenIPRs................................ 68
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6.5.3 HardwareStructureofImplicitlyWrittenIPRs................................ 69
6.5.4 IPRAccessOrdering................................................... 69
6.5.5 CorrectOrderingofExplicitWritersFollowedbyImplicitReaders................. 610
6.5.6 CorrectOrderingofExplicitReadersFollowedbyImplicitWriters................. 611
6.6 PALshadow Registers...................................................... 611
6.7 PALcodeEmulationoftheFPCR............................................. 611
6.7.1 StatusFlags.......................................................... 612
6.7.2 MF_FPCR ........................................................... 612
6.7.3 MT_FPCR ........................................................... 612
6.8 PALcodeEntryPoints...................................................... 612
6.8.1 CALL_PALEntryPoints................................................. 612
6.8.2 PALcodeExceptionEntryPoints.......................................... 613
6.9 TranslationBuffer(TB)FillFlows............................................. 614
6.9.1 DTBFill ............................................................. 614
6.9.2 ITBFill.............................................................. 616
6.10 Performance Counter Support . . . ............................................ 617
6.10.1 GeneralPrecautions ................................................... 618
6.10.2 AggregateModeProgrammingGuidelines.................................. 618
6.10.2.1 AggregateModePrecautions......................................... 618
6.10.2.2 Operation ........................................................ 619
6.10.2.3 AggregateCountingModeDescription.................................. 620
6.10.2.3.1 Cyclecounting................................................. 620
6.10.2.3.2 Retiredinstructionscycles........................................ 620
6.10.2.3.3 Bcachemissorlonglatencyprobescycles........................... 620
6.10.2.3.4 Mboxreplaytrapscycles......................................... 620
6.10.2.4 Counter Modes for Aggregate Mode. . . ................................. 620
6.10.3 ProfileMeModeProgrammingGuidelines................................... 620
6.10.3.1 ProfileMeModePrecautions.......................................... 620
6.10.3.2 Operation ........................................................ 621
6.10.3.3 ProfileMe Counting Mode Description . ................................. 623
6.10.3.3.1 Cyclecounting................................................. 623
6.10.3.3.2 Inumretiredelaycycles.......................................... 623
6.10.3.3.3 Retiredinstructionscycles........................................ 623
6.10.3.3.4 Bcachemissorlonglatencyprobescycles........................... 623
6.10.3.3.5 Mboxreplaytrapscycles......................................... 623
6.10.3.4 CounterModesforProfileMeMode.................................... 624
7 Initialization and Configuration
7.1 Power-UpResetFlowandtheReset_LandDCOK_HPins......................... 71
7.1.1 Power Sequencing and Reset State for Signal Pins ........................... 73
7.1.2 ClockForwardingandSystemClockRatioConfiguration....................... 74
7.1.3 PLLRampUp......................................................... 76
7.1.4 BiSTandSROMLoadandtheTestStat_HPin............................... 76
7.1.5 ClockForwardResetandSystemInterfaceInitialization........................ 77
7.2 FaultResetFlow.......................................................... 78
7.3 EnergyStarCertificationandSleepModeFlow.................................. 79
7.4 WarmResetFlow......................................................... 711
7.5 ArrayInitialization ......................................................... 712
7.6 InitializationModeProcessing................................................ 712
7.7 ExternalInterfaceInitialization ............................................... 714
7.8 InternalProcessorRegisterPower-UpResetState............................... 714
7.9 IEEE1149.1TestPortReset................................................ 716
7.10 ResetStateMachine....................................................... 716
7.11 Phase-LockLoop(PLL)FunctionalDescription.................................. 719
7.11.1 DifferentialReferenceClocks............................................. 719
7.11.2 PLLOutputClocks..................................................... 719
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7.11.2.1 GCLK ........................................................... 719
7.11.2.2 Differential 21264/EV68A Clocks ...................................... 719
7.11.2.3 Nominal Operating Frequency . . ...................................... 719
7.11.2.4 Power-Up/ResetClocking............................................ 720
8 Error Detection and Error Handling
8.1 DataErrorCorrectionCode.................................................. 82
8.2 IcacheDataorTagParityError............................................... 82
8.3 DcacheTagParityError.................................................... 82
8.4 DcacheDataSingle-BitCorrectableECCError.................................. 83
8.4.1 LoadInstruction....................................................... 83
8.4.2 Store Instruction (Quadword or Smaller) . . . ................................. 84
8.4.3 DcacheVictimExtracts ................................................. 84
8.5 DcacheStoreSecondError ................................................. 84
8.6 DcacheDuplicateTagParityError............................................ 84
8.7 BcacheTagParityError.................................................... 85
8.8 ControllingBcacheBlockParityCalculation..................................... 85
8.9 BcacheDataSingle-BitCorrectableECCError .................................. 85
8.9.1 IcacheFillfromBcache................................................. 85
8.9.2 DcacheFillfromBcache................................................ 86
8.9.3 BcacheVictimRead.................................................... 87
8.9.3.1 BcacheVictimReadDuringaDcache/BcacheMiss ....................... 87
8.9.3.2 BcacheVictimReadDuringanECBInstruction........................... 87
8.10 Memory/SystemPortSingle-BitDataCorrectableECCError........................ 87
8.10.1 IcacheFillfromMemory................................................. 87
8.10.2 DcacheFillfromMemory................................................ 88
8.11 BcacheDataSingle-BitCorrectableECCErroronaProbe......................... 89
8.12 Double-BitFillErrors....................................................... 89
8.13 ErrorCaseSummary....................................................... 810
9 Electrical Data
9.1 ElectricalCharacteristics.................................................... 91
9.2 DCCharacteristics ........................................................ 92
9.3 Power Supply Sequencing and Avoiding Potential Failure Mechanisms ............... 95
9.4 ACCharacteristics......................................................... 96
10 Thermal Management
10.1 OperatingTemperature..................................................... 101
10.2 HeatSinkSpecifications.................................................... 103
10.3 ThermalDesignConsiderations .............................................. 106
11 Testability and Diagnostics
11.1 TestPins................................................................ 111
11.2 SROM/SerialDiagnosticTerminalPort......................................... 112
11.2.1 SROMLoadOperation.................................................. 112
11.2.2 SerialTerminalPort.................................................... 112
11.3 IEEE 1149.1 Port. . . ....................................................... 113
11.4 TestStat_HPin........................................................... 114
11.5 Power-UpSelf-TestandInitialization .......................................... 115
11.5.1 Built-inSelf-Test....................................................... 115
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11.5.2 SROMInitialization..................................................... 115
11.5.2.1 SerialInstructionCacheLoadOperation................................ 116
11.6 Notes on IEEE 1149.1 Operation and Compliance ............................... 117
A Alpha Instruction Set
A.1 AlphaInstructionSummary.................................................. A1
A.2 Reserved Opcodes . ....................................................... A8
A.2.1 Opcodes Reserved for Compaq........................................... A8
A.2.2 Opcodes Reserved for PALcode .......................................... A9
A.3 IEEEFloating-PointInstructions.............................................. A9
A.4 VAXFloating-PointInstructions............................................... A11
A.5 Independent Floating-Point Instructions . . ...................................... A11
A.6 OpcodeSummary......................................................... A12
A.7 RequiredPALcodeFunctionCodes........................................... A13
A.8 IEEEFloating-PointConformance ............................................ A14
B 21264/EV68A Boundary-Scan Register
B.1 Boundary-Scan Register. . .................................................. B1
B.1.1 BSDL Description of the Alpha 21264/EV68A Boundary-Scan Register . . .......... B1
C Serial Icache Load Predecode Values
D PALcode Restrictions and Guidelines
D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper............... D1
D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group ............... D8
D.3 Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group .......... D8
D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write . . .......... D9
D.5 Restriction 7 :ReplayTrap,InterruptCodeSequence,andSTF/ITOF............... D9
D.6 Restriction 9 : PALmode Istream Address Ranges . . . ........................... D10
D.7 Restriction 10:DuplicateIPRModeBits ....................................... D10
D.8 Restriction 11: Ibox IPR Update Synchronization ................................ D11
D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM D–11
D.10 Restriction13:DTBFillFlowCollision......................................... D11
D.11 Restriction14:HW_RET ................................................... D11
D.12 Guideline16:JSR-BADVA................................................. D12
D.13 Restriction17:MTPRtoDTB_TAG0/DTB_PTE0/DTB_TAG1/DTB_PTE1 ............. D12
D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block as
HW_MTPR .............................................................. D12
D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode D–12
D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable................................ D12
D.17 Restriction21:HW_RET/STALLAfterHW_MTPRASN0/ASN1...................... D12
D.18 Restriction22:HW_RET/STALLAfterHW_MTPRIS0/IS1.......................... D13
D.19 Restriction23:HW_ST/P/CONDITIONALDoesNotCleartheLockFlag............... D13
D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
....................................................................... D14
D.21 Restriction25:HW_MTPRITB_IAAfterReset................................... D14
D.22 Guideline 26: Conditional Branches in PALcode ................................. D14
D.23 Restriction27:Resetof‘Force-FailLockFlag’StateinPALcode..................... D15
D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads
....................................................................... D15
D.25 Guideline29:JSR,JMP,RET,andJSR_CORinPALcode......................... D15
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D.26 Restriction30:HW_MTPRandHW_MFPRtotheCboxCSR....................... D15
D.27 Restriction 31 : I_CTL[VA_48] Update . . . ...................................... D17
D.28 Restriction32:PCTR_CTLUpdate ........................................... D17
D.29 Restriction33:HW_LDPhysical/LockUse...................................... D18
D.30 Restriction34:WritingMultipleITBEntriesintheSamePALcodeFlow............... D18
D.31 Guideline 35:HW_INT_CLRUpdate......................................... D18
D.32 Restriction36:UpdatingI_CTL[SDE].......................................... D18
D.33 Restriction 37 : Updating VA_CTL[VA_48] ...................................... D18
D.34 Restriction38:UpdatingPCTR_CTL.......................................... D18
D.35 Guideline39:WritingMultipleDTBEntriesintheSamePALFlow.................... D19
D.36 Restriction40:ScrubbingaSingle-BitError..................................... D19
D.37 Restriction41:MTPRITB_TAG,MTPRITB_PTEMustbeintheSameFetchBlock..... D21
D.38 Restriction42:UpdatingVA_CTL,CC_CTL,orCCIPRs........................... D21
D.39 Restriction 43: No Trappable Instructions Along with HW_MTPR..................... D21
D.40 Restriction 44: Not Applicable to the 21264/EV68A ............................... D21
D.41 Restriction45: NoHW_JMPorJMPIntructionsinPALcode........................ D21
D.42 Restriction 46: Avoiding Livelocks in Speculative Load CRD Handlers ................ D22
D.43 Restriction47: CacheEvictionforSingle-BitCacheErrors......................... D22
D.44 Restriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity
....................................................................... D24
E 21264/EV68A-to-Bcache Pin Interface
E.1 ForwardingClockPinGroupings.............................................. E1
E.2 Late-WriteNon-BurstingSSRAMs ............................................ E2
E.3 Dual-DataRateSSRAMs................................................... E3
Glossary
Index
21264/EV68A Hardware Reference Manual
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Figures
2–1 21264/EV68A Block Diagram ................................................ 23
22 BranchPredictor.......................................................... 24
23 LocalPredictor ........................................................... 24
2–4 Global Predictor........................................................... 25
25 ChoicePredictor.......................................................... 25
2–6 Integer Execution Unit—Clusters 0 and 1 . ...................................... 29
27 Floating-PointExecutionUnits ............................................... 210
28 PipelineOrganization ...................................................... 214
2–9 Pipeline Timing for Integer Load Instructions . . . ................................. 224
210 PipelineTimingforFloating-PointLoadInstructions............................... 225
211 Floating-PointControlRegister............................................... 236
212 TypicalUniprocessorConfiguration ........................................... 239
213 TypicalMultiprocessorConfiguration.......................................... 239
3–1 21264/EV68A Microprocessor Logic Symbol . . . ................................. 32
32 PackageDimensions....................................................... 317
3–3 21264/EV68A Top View (Pin Down) ........................................... 318
3–4 21264/EV68A Bottom View (Pin Up)........................................... 319
4–1 21264/EV68A System and Bcache Interfaces . . ................................. 43
4–2 21264/EV68A Bcache Interface Signals . . ...................................... 47
43 CacheSubsetHierarchy.................................................... 49
4–4 System Interface Signals. . .................................................. 417
45 FastTransferTimingExample ............................................... 432
46 SysFillValid_LTiming...................................................... 436
51 CycleCounterRegister..................................................... 53
52 CycleCounterControlRegister............................................... 53
53 VirtualAddressRegister.................................................... 54
54 VirtualAddressControlRegister.............................................. 54
55 VirtualAddressFormatRegister(VA_48=0,VA_FORM_32=0).................... 55
56 VirtualAddressFormatRegister(VA_48=1,VA_FORM_32=0).................... 56
57 VirtualAddressFormatRegister(VA_48=0,VA_FORM_32=1).................... 56
58 ITBTagArrayWriteRegister ................................................ 56
59 ITBPTEArrayWriteRegister................................................ 57
510 ITBInvalidateSingleRegister................................................ 57
511 ProfileMePCRegister...................................................... 58
512 ExceptionAddressRegister................................................. 58
513 InstructionVirtualAddressFormatRegister(VA_48=0,VA_FORM_32=0)........... 59
514 InstructionVirtualAddressFormatRegister(VA_48=1,VA_FORM_32=0)........... 59
515 InstructionVirtualAddressFormatRegister(VA_48=0,VA_FORM_32=1)........... 59
516 InterruptEnableandCurrentProcessorModeRegister............................ 510
517 SoftwareInterruptRequestRegister........................................... 511
518 InterruptSummaryRegister ................................................. 511
519 HardwareInterruptClearRegister ............................................ 512
520 ExceptionSummaryRegister................................................ 514
521 PALBaseRegister........................................................ 515
522 IboxControlRegister....................................................... 516
523 IboxStatusRegister....................................................... 519
524 ProcessContextRegister................................................... 522
525 PerformanceCounterControlRegister......................................... 523
526 DTBTagArrayWriteRegisters0and1........................................ 525
527 DTBPTEArrayWriteRegisters0and1........................................ 526
528 DTBAlternateProcessorModeRegister ....................................... 526
529 DstreamTranslationBufferInvalidateSingleRegisters............................ 527
530 DstreamTranslationBufferAddressSpaceNumberRegisters0and1................ 528
5–31 Memory Management Status Register . . . ...................................... 528
532 MboxControlRegister...................................................... 529
533 DcacheControlRegister.................................................... 531
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21264/EV68A Hardware Reference Manual
534 DcacheStatusRegister..................................................... 532
535 CboxDataRegister........................................................ 533
536 CboxShiftRegister........................................................ 533
537 WRITE_MANYChainWriteTransactionExample................................ 539
61 HW_LDInstructionFormat.................................................. 64
62 HW_STInstructionFormat.................................................. 64
63 HW_RETInstructionFormat................................................. 66
64 HW_MFPRandHW_MTPRInstructionsFormat................................. 66
65 Single-MissDTBInstructionsFlowExample..................................... 614
66 ITBMissInstructionsFlowExample........................................... 616
7–1 Power-Up Timing Sequence ................................................. 73
7–2 Fault Reset Sequence of Operation ........................................... 79
73 SleepModeSequenceofOperation .......................................... 711
74 ExampleforInitializingBcache............................................... 713
7–5 21264/EV68A Reset State Machine State Diagram ............................... 717
101 Type1HeatSink.......................................................... 103
102 Type2HeatSink.......................................................... 104
103 Type3HeatSink.......................................................... 105
111 TestStat_HPinTimingDuringPower-UpBuilt-InSelf-Test(BiST) ................... 115
112 TestStat_HPinTimingDuringBuilt-InSelf-Initialization(BiSI)....................... 115
113 SROMContentMap....................................................... 116
21264/EV68A Hardware Reference Manual
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Tables
1–1 Integer Data Types . ....................................................... 12
21 PipelineAbortDelay(GCLKCycles)........................................... 216
22 InstructionName,Pipeline,andTypes......................................... 217
23 InstructionGroupDefinitionsandPipelineUnit................................... 218
24 InstructionClassLatencyinCycles............................................ 220
25 MinimumRetireLatenciesforInstructionClasses ................................ 221
26 InstructionsRetiredWithoutExecution......................................... 223
27 RulesforI/OAddressSpaceLoadInstructionDataMerging........................ 228
28 RulesforI/OAddressSpaceStoreInstructionDataMerging........................ 229
29 MAFMergingRules........................................................ 230
210 MemoryReferenceOrdering................................................. 230
211 I/OReferenceOrdering..................................................... 231
2–12 TB Fill Flow Example Sequence 1 ............................................ 234
2–13 TB Fill Flow Example Sequence 2 ............................................ 234
214 Floating-PointControlRegisterFields.......................................... 236
2–15 21264/EV68A AMASK Values................................................ 238
216 AMASKBitAssignments.................................................... 238
3–1 Signal Pin Types Definitions ................................................. 33
3–2 21264/EV68A Signal Descriptions ............................................ 33
3–3 21264/EV68A Signal Descriptions by Function. . ................................. 36
34 PinListSortedbySignalName............................................... 38
35 PinListSortedbyPGALocation.............................................. 312
3–6 Ground and Power (VSS and VDD) Pin List . . . ................................. 316
41 TranslationofInternalReferencestoExternalInterfaceReference................... 45
4–2 21264/EV68A-Supported Cache Block States . . ................................. 49
43 CacheBlockStateTransitions ............................................... 410
4–4 System Responses to 21264/EV68A Commands................................. 410
4–5 System Responses to 21264/EV68A Commands and Reactions..................... 411
46 SystemPortPins.......................................................... 417
47 ProgrammingValuesforSystemInterfaceClocks................................ 418
48 ProgramValuesforData-Sample/DriveCSRs................................... 418
49 ForwardedClocksandFrameClockRatio...................................... 419
410 BankInterleaveonCacheBlockBoundaryModeofOperation...................... 419
411 PageHitModeofOperation................................................. 420
4–12 21264/EV68A-to-System Command Fields Definitions. . ........................... 420
413 MaximumPhysicalAddressforShortBusFormat................................ 421
4–14 21264/EV68A-to-System Commands Descriptions................................ 421
415 ProgrammingINVAL_TO_DIRTY_ENABLE[1:0].................................. 423
416 ProgrammingSET_DIRTY_ENABLE[2:0]....................................... 424
4–17 21264/EV68A ProbeResponse Command ...................................... 424
4–18 ProbeResponse Fields Descriptions........................................... 425
4–19 System-to-21264/EV68A Probe Commands..................................... 426
4–20 System-to-21264/EV68A Probe Commands Fields Descriptions ..................... 427
4–21 Data Movement Selection by Probe[4:3]. . ...................................... 427
4–22 Next Cache Block State Selection by Probe[2:0] ................................. 427
423 DataTransferCommandFormat ............................................. 428
424 SysDc[4:0]FieldDescription................................................. 429
4–25 SYSCLK Cycles Between SysAddOut and SysData............................... 432
426 CboxCSRSYSDC_DELAY[4:0]Examples ..................................... 433
427 FourTimingExamples ..................................................... 434
4–28 Data Wrapping Rules ...................................................... 436
429 SystemWrapandDeliverData............................................... 437
430 WrapInterleaveOrder...................................................... 437
431 WrapOrderforDouble-PumpedDataTransfers.................................. 438
4–32 21264/EV68A Commands with NXM Addresses and System Response............... 439
4–33 21264/EV68A Response to System Probe and In-Flight Command Interaction.......... 441
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21264/EV68A Hardware Reference Manual
4–34 Rules for System Control of Cache Status Update Order........................... 442
435 RangeofMaximumBcacheClockRatios....................................... 443
436 BcachePortPins.......................................................... 443
437 BC_CPU_CLK_DELAY[1:0]Values........................................... 445
438 BC_CLK_DELAY[1:0]Values................................................ 445
439 ProgramValuestoSettheCacheClockPeriod(Single-Data)....................... 446
440 ProgramValuestoSettheCacheClockPeriod(Dual-DataRate).................... 446
441 Data-Sample/DriveCboxCSRs .............................................. 447
4–42 Programming the Bcache to Support Each Size of the Bcache ...................... 451
443 ProgrammingtheBcacheControlPins......................................... 451
444 ControlPinAssertionforRAM_TYPEA........................................ 451
445 ControlPinAssertionforRAM_TYPEB........................................ 452
446 ControlPinAssertionforRAM_TYPEC........................................ 452
447 ControlPinAssertionforRAM_TYPED........................................ 452
51 InternalProcessorRegisters................................................. 51
52 CycleCounterControlRegisterFieldsDescription................................ 54
53 VirtualAddressControlRegisterFieldsDescription............................... 55
54 ProfileMePCFieldsDescription.............................................. 58
55 IER_CMRegisterFieldsDescription........................................... 510
56 SoftwareInterruptRequestRegisterFieldsDescription............................ 511
57 InterruptSummaryRegisterFieldsDescription................................... 512
58 HardwareInterruptClearRegisterFieldsDescription.............................. 513
59 ExceptionSummaryRegisterFieldsDescription ................................. 514
510 PALBaseRegisterFieldsDescription ......................................... 515
511 IboxControlRegisterFieldsDescription........................................ 516
512 IboxStatusRegisterFieldsDescription ........................................ 519
513 IPRIndexBitsandRegisterFields............................................ 521
514 ProcessContextRegisterFieldsDescription.................................... 522
515 PerformanceCounterControlRegisterFieldsDescription.......................... 523
516 PerformanceCounterControlRegisterInputSelectFields.......................... 525
517 DTBAlternateProcessorModeRegisterFieldsDescription......................... 526
5–18 Memory Management Status Register Fields Description .......................... 528
519 MboxControlRegisterFieldsDescription....................................... 530
520 DcacheControlRegisterFieldsDescription..................................... 531
521 DcacheStatusRegisterFieldsDescription...................................... 532
522 CboxDataRegisterFieldsDescription......................................... 533
523 CboxShiftRegisterFieldsDescription......................................... 533
524 CboxWRITE_ONCEChainOrder ............................................ 534
525 CboxWRITE_MANYChainOrder ............................................ 539
526 CboxReadIPRFieldsDescription............................................ 541
61 RequiredPALcodeFunctionCodes........................................... 63
6–2 Opcodes Reserved for PALcode. . ............................................ 63
63 HW_LDInstructionFieldsDescriptions......................................... 64
64 HW_STInstructionFieldsDescriptions......................................... 65
65 HW_RETInstructionFieldsDescriptions ....................................... 66
66 HW_MFPRandHW_MTPRInstructionsFieldsDescriptions........................ 67
67 PairedInstructionFetchOrder ............................................... 69
68 PALcodeExceptionEntryLocations........................................... 613
6–9 IPRs Used for Performance Counter Support. . .................................. 618
610 AggregateModeReturnedIPRContents....................................... 619
611 AggregateModePerformanceCounterIPRInputSelectFields...................... 620
612 CMOVDecomposed....................................................... 621
613 ProfileMeModeReturnedIPRContents........................................ 622
614 ProfileMeModePCTR_CTLInputSelectFields.................................. 624
7–1 21264/EV68A Reset State Machine Major Operations . . ........................... 71
7–2 Signal Pin Reset State . . . .................................................. 73
73 PinSignalNamesandInitializationState....................................... 75
7–4 Power-Up Flow Signals and Their Constraints . ................................. 77
75 EffectonIPRsAfterFaultReset.............................................. 78
21264/EV68A Hardware Reference Manual
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7–6 Effect on IPRs After Transition Through Sleep Mode . . . ........................... 710
7–7 Signals and Constraints for the Sleep Mode Sequence . ........................... 711
78 EffectonIPRsAfterWarmReset............................................. 711
79 WRITE_MANYChainCSRValuesforBcacheInitialization......................... 712
710 InternalProcessorRegistersatPower-UpResetState ............................ 714
7–11 21264/EV68A Reset State Machine State Descriptions . ........................... 717
7–12 Differential Reference Clock Frequencies in Full-Speed Lock . ...................... 720
8–1 21264/EV68A Error Detection Mechanisms ..................................... 81
82 64-BitDataandCheckBitECCCode.......................................... 82
83 ErrorCaseSummary....................................................... 810
91 MaximumElectricalRatings................................................. 91
9–2 Signal Types ............................................................. 92
93 VDD(I_DC_POWER)...................................................... 93
9–4 Input DC Reference Pin (I_DC_REF) .......................................... 93
9–5 Input Differential Amplifier Receiver (I_DA)...................................... 93
9–6 Input Differential Amplifier Clock Receiver (I_DA_CLK) . ........................... 93
97 PinType:Open-DrainOutputDriver(O_OD).................................... 94
98 Bidirectional,DifferentialAmplifierReceiver,Open-DrainOutputDriver(B_DA_OD) ..... 94
99 PinType:Open-DrainDriverforTestPins(O_OD_TP)............................ 94
910 Bidirectional,DifferentialAmplifierReceiver,Push-PullOutputDriver(B_DA_PP) ....... 94
911 Push-PullOutputDriver(O_PP).............................................. 95
912 Push-PullOutputClockDriver(O_PP_CLK)..................................... 95
913 ACSpecifications ......................................................... 97
101 OperatingTemperatureatHeatSinkCenter(Tc)................................. 101
10–2 qca at Various Airflows for 21264/EV68A . ...................................... 102
10–3 Maximum Ta for 21264/EV68A @ 750 MHz and @ 1.7 V with Various Airflows ......... 102
10–4 Maximum Ta for 21264/EV68A @ 833 MHz and @ 1.7 V with Various Airflows ......... 102
10–5 Maximum Ta for 21264/EV68A @ 875 MHz and @ 1.7 V with Various Airflows ......... 102
10–6 Maximum Ta for 21264/EV68A @ 940 MHz and @ 1.7 V with Various Airflows ......... 102
111 DedicatedTestPortPins.................................................... 111
11–2 IEEE 1149.1 Instructions and Opcodes . . ...................................... 113
113 TAPControllerStateMachine................................................ 114
114 IcacheBitFieldsinanSROMLine............................................ 117
A1 InstructionFormatandOpcodeNotation ....................................... A1
A2 ArchitectureInstructions.................................................... A2
A–3 Opcodes Reserved for Compaq . . ............................................ A8
A–4 Opcodes Reserved for PALcode. . ............................................ A9
A–5 IEEE Floating-Point Instruction Function Codes. ................................. A9
A6 VAXFloating-PointInstructionFunctionCodes .................................. A11
A–7 Independent Floating-Point Instruction Function Codes ............................ A12
A8 OpcodeSummary......................................................... A12
A9 KeytoOpcodeSummaryUsedinTableA8.................................... A13
A10 RequiredPALcodeFunctionCodes........................................... A13
A–11 Exceptional Input and Output Conditions ...................................... A15
E1 BcacheForwardingClockPinGroupings...................................... E1
E2 Late-WriteNon-BurstingSSRAMsDataPinUsage............................... E2
E3 Late-WriteNon-BurstingSSRAMsTagPinUsage................................ E2
E4 Dual-DataRateSSRAMDataPinUsage....................................... E3
E5 Dual-DataRateSSRAMTagPinUsage........................................ E4
21264/EV68A Hardware Reference Manual
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Preface
Audience
This manual is for system designers and programmers who use the Alpha 21264/
EV68A microprocessor (referred to as the 21264/EV68A).
Content
This manual contains the following chapters and appendixes:
Chapter 1, Introduction, introduces the 21264/EV68A and provides an overview of the
Alpha architecture.
Chapter 2, Internal Architecture, describes the major hardware functions and the inter-
nal chip architecture. It describes performance measurement facilities, coding rules, and
design examples.
Chapter 3, Hardware Interface, lists and describes the internal hardware interface sig-
nals, and provides mechanical data and packaging information, including signal pin
lists.
Chapter 4, Cache and External Interfaces, describes the external bus functions and
transactions, lists bus commands, and describes the clock functions.
Chapter 5, Internal Processor Registers, lists and describes the internal processor regis-
ter set.
Chapter 6, Privileged Architecture Library Code, describes the privileged architecture
library code (PALcode).
Chapter 7, Initialization and Configuration, describes the initialization and configura-
tion sequence.
Chapter 8, Error Detection and Error Handling, describes error detection and error han-
dling.
Chapter 9, Electrical Data, provides electrical data and describes signal integrity issues.
Chapter 10, Thermal Management, provides information about thermal management.
Chapter 11, Testability and Diagnostics, describes chip and system testability features.
Appendix A, Alpha Instruction Set, summarizes the Alpha instruction set.
Appendix B, 21264/EV68A Boundary-Scan Register, presents the BSDL description
of the 21264/EV68A boundary-scan register.
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21264/EV68A Hardware Reference Manual
Appendix C, Serial Icache Load Predecode Values, provides a pointer to the Alpha
Motherboards Software Developers Kit (SDK), which contains this information.
Appendix D, PALcode Restrictions and Guidelines, lists restrictions and guidelines
that must be adhered to when generating PALcode.
Appendix E, 21264/EV68A-to-Bcache Pin Interface, provides the pin interface
between the 21264/EV68A and Bcache SSRAMs.
The Glossary lists and defines terms associated with the 21264/EV68A.
An Index is provided at the end of the document.
Documentation Included by Reference
The companion volume to this manual, the Alpha Architecture Reference Manual,
Fourth Edition, can be accessed from the following website: ftp.compaq.com/
pub/products/alphaCPUdocs.
21264/EV68A Hardware Reference Manual
xix
Terminology and Conventions
This section defines the abbreviations, terminology, and other conventions used
throughout this document.
Abbreviations
Binary Multiples
The abbreviations K, M, and G (kilo, mega, and giga) represent binary multiples
and have the following values.
For example:
Register Access
The abbreviations used to indicate the type of access to register fields and bits have
the following definitions:
K
=2
10
(1024)
M
=2
20
(1,048,576)
G
=2
30
(1,073,741,824)
2KB = 2 kilobytes
=2× 2
10
bytes
4MB = 4 megabytes
=4× 2
20
bytes
8GB = 8 gigabytes
=8× 2
30
bytes
2K pixels = 2 kilopixels
=2× 2
10
pixels
4M pixels = 4 megapixels
=4× 2
20
pixels
Abbreviation Meaning
IGN Ignore
Bitsandfieldsspecifiedareignoredonwrites.
MBZ Must Be Zero
Software must never place a nonzero value in bits and fields specified as
MBZ. A nonzero read produces an Illegal Operand exception. Also, MBZ
fields are reserved for future use.
RAZ Read As Zero
Bits and fields return a zero when read.
RC Read Clears
Bits and fields are cleared when read. Unless otherwise specified, such bits
cannot be written.
RES Reserved
Bits and fields are reserved by Compaq and should not be used; however,
zeros can be written to reserved fields that cannot be masked.
RO Read Only
Thevaluemaybereadbysoftware.Itiswrittenbyhardware.Softwarewrite
operations are ignored.
RO,n Read Only, and takes the value n at power-on reset.
Thevaluemaybereadbysoftware.Itiswrittenbyhardware.Softwarewrite
operations are ignored.
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21264/EV68A Hardware Reference Manual
Sign extension
SEXT(x) means x is sign-extended to the required size.
Addresses
Unless otherwise noted, all addresses and offsets are hexadecimal.
Aligned and Unaligned
The terms aligned and naturally aligned are interchangeable and refer to data objects
that are powers of two in size. An aligned datum of size 2n is stored in memory at a
byte address that is a multiple of 2n; that is, one that has n low-order zeros. For ex-
ample, an aligned 64-byte stack frame has a memory address that is a multiple of 64.
A datum of size 2n is unaligned if it is stored in a byte address that is not a multiple of
2n.
Bit Notation
Multiple-bit fields can include contiguous and noncontiguous bits contained in square
brackets ([]). Multiple contiguous bits are indicated by a pair of numbers separated by a
colon [:]. For example, [9:7,5,2:0] specifies bits 9,8,7,5,2,1, and 0. Similarly, single bits
are frequently indicated with square brackets. For example, [27] specifies bit 27. See
also Field Notation.
Caution
Cautions indicate potential damage to equipment or loss of data.
RW Read/Write
Bits and fields can be read and written.
RW,n Read/Write, and takes the value n at power-on reset.
Bits and fields can be read and written.
W1C Write One to Clear
If read operations are allowed to the register, then the value may be read by
software. If it is a write-only register, then a read operation by software
returns an UNPREDICTABLE result. Software write operations of a 1 cause
the bit to be cleared by hardware. Software write operations of a 0 do not
modify the state of the bit.
W1S Write One to Set
If read operations are allowed to the register, then the value may be read by
software. If it is a write-only register, then a read operation by software
returns an UNPREDICTABLE result. Software write operations of a 1 cause
the bit to be set by hardware. Software write operations of a 0 do not modify
the state of the bit.
WO Write Only
Bits and fields can be written but not read.
WO,n Write Only, and takes the value n at power-on reset.
Bits and fields can be written but not read.
Abbreviation Meaning
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