Microchip Technology TC7129 General Description Manual

Brand: Microchip Technology

Model: TC7129

Type: General Description Manual

 2004 Microchip Technology Inc. DS21459C-page 1

TC7129

Features

• Count Resolution: ±19,999

• Resolution on 200 mV Scale: 10µV

• True Differential Input and Reference

• Low Power Consumption: 500µA at 9V

• Direct LCD Driver for 4-1/2 Digits, Decimal Points,

Low Battery Indicator, and Continuity Indicator

• Overrange and Underrange Outputs

• Range Select Input: 10:1

• High Common Mode Rejection Ratio: 110 dB

• External Phase Compensation Not Required

Applications

• Full-Featured Multimeters

• Digital Measurement Devices

Device Selection Table

General Description

The TC7129 is a 4-1/2 digit Analog-to-Digital Converter

(ADC) that directly drives a multiplexed Liquid Crystal

Display (LCD). Fabricated in high-performance, low-

power CMOS, the TC7129 ADC is designed specifi-

cally for high-resolution, battery-powered digital multi-

meter applications. The traditional dual-slope method

of A/D conversion has been enhanced with a succes-

sive integration technique to produce readings accu-

rate to better than 0.005% of full-scale and resolution

down to 10 µV per count.

The TC7129 includes features important to multimeter

applications. It detects and indicates low battery condi-

tion. A continuity output drives an annunciator on the

display and can be used with an external driver to sound

an audible alarm. Overrange and underrange outputs,

along with a range-change input, provide the ability to

create auto-ranging instruments. For snapshot read-

ings, the TC7129 includes a latch-and-hold input to

freeze the present reading. This combination of features

makes the TC7129 the ideal choice for full-featured

multimeter and digital measurement applications.

Typical Application

Package

Code

Layout

Package

Temperature

Range

TC7129CPL Normal 40-Pin PDIP 0°C to +70°C

TC7129CKW Formed 44-Pin PQFP 0°C to +70°C

TC7129CLW – 44-Pin PLCC 0°C to +70°C

TC7129

1234567

1011

13141516171819

3837

3534

323130

27262524232221

Low Battery Continuity

V+

5 pF

120 kHz

10 pF

0.1 µF

kΩ

0.1

µF

100 kΩ

1 µF

0.1 µF

150 kΩ

10 kΩ

V+

–

*Note: RC network between pins 26 and 28 is not required.

330 kΩ

4-1/2 Digit Analog-to-Digital Converters with

On-Chip LCD Drivers

TC7129

DS21459C-page 2  2004 Microchip Technology Inc.

Package Types

18 19 20 21 23 24

6543 1442

43 42 41 40

25 26 27 28

3214

3115

3016

2917

TC7129CLW

, E

, DP

, C

, BATT

, G

, D

, E

, DP

, C

MINUS

, G

, D

, E

, DP

, C

, G

, D

, E

, DP

REF LO

REF HI

IN HI

IN LO

BUFF

REF

COMMON

CONTINUITY

INT OUT

, G

, D

, C

, CONT

ANNUNCIATOR

OSC3

OSC1

OSC2

RANGE

DGND

DISP

/OR

/UR

LATCH/HOLD

V+

V-

INT IN

TC7129CKW

12 13 14 15 17 18

44 43 42 41 39 3840

37 36 35 34

19 20 21 22

, G

, D

, C

, CONT

ANNUNCIATOR

OSC3

OSC1

OSC2

RANGE

DGND

REF LO

REF HI

IN HI

IN LO

BUFF

REF

COMMON

CONTINUITY

INT OUT

, E

, DP

, C

, BATT

, G

, D

, E

, DP

, C

MINUS

, G

, D

, E

, DP

, C

, G

, D

, E

, DP

DISP

/OR

/UR

LATCH/HOLD

V+

V-

INT IN

TC7129CPL

40-Pin PDIP

44-Pin QFP 44-Pin PLCC

OSC2

RANGE

DGND

REF LO

REF HI

IN HI

IN LO

BUFF

REF

COMMON

CONTINUITY

INT OUT

INT IN

V+

V-

/UR

OSC1

OSC3

ANNUNICATOR

, C

, CONT

, G

, D

, E

, DP

, C

, LO BATT

, G

, D

, E

, DP

, C

MINUS

, G

, D

, E

, DP

, C

, G

, D

, E

, DP

DISP

/OR

Display

Output

Lines

LATCH/HOLD

 2004 Microchip Technology Inc. DS21459C-page 3

TC7129

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (V+ to V-).......................................15V

Reference Voltage (REF HI or REF LO)........ V+ to V–

Input Voltage (IN HI or IN LO) (Note 1).......... V+ to V–

DISP

.......................................... V+ to (DGND – 0.3V)

Digital Input (Pins 1, 2, 19, 20,

21, 22, 27, 37, 39, 40).......................... DGND to V+

Analog Input (Pins 25, 29, 30) ....................... V+ to V–

Package Power Dissipation (T

≤ 70°C)

Plastic DIP .....................................................1.23W

PLCC .............................................................1.23W

Plastic QFP....................................................1.00W

Operating Temperature Range ...............0°C to +70°C

Storage Temperature Range..............-65°C to +150°C

*Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device

at these or any other conditions above those indicated in the

operation sections of the specifications is not implied.

Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability.

TC7129 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: V+ to V– = 9V, V

REF

= 1V, T

= +25°C, f

CLK

= 120 kHz, unless otherwise indicated.

Pin numbers refer to 40-pin DIP.

Symbol Parameter Min Typ Max Unit Test Conditions

Input

Zero Input Reading –0000 0000 +0000 Counts V

= 0V, 200 mV scale

Zero Reading Drift — ±0.5 — µV/°C V

= 0V, 0°C < T

< +70°C

Ratiometric Reading 9996 — 10000 Counts V

= V

REF

= 1000 mV,

Range = 2V

Range Change Accuracy 0.9999 1.0000 1.0001 Ratio V

= 1V on High Range,

= 0.1V on Low Range

RE Rollover Error — 1 2 Counts V

– = V

+ = 199 mV

NL Linearity Error — 1 — Counts 200mV Scale

CMRR Common Mode Rejection Ratio — 110 — dB V

= 1V, V

= 0V,

200 mV scale

CMVR Common Mode Voltage Range — (V-) +

1.5

—VV

= 0V

— (V+) – 1 — V 200 mV scale

Noise (Peak-to-Peak Value not

Exceeded 95% of Time)

— 14—µV

P-P

= 0V

200 mV scale

Input Leakage Current — 1 10 pA V

= 0V, pins 32, 33

Scale Factor Temperature

Coefficient

— 2 7 ppm/°C V

= 199 mV,

0°C < T

< +70°C

External V

REF

= 0 ppm/°C

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400 µA. Currents above

this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.

Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

TC7129

DS21459C-page 4  2004 Microchip Technology Inc.

Power

COM

Common Voltage 2.8 3.2 3.5 V V+ to pin 28

Common Sink Current — 0.6 — mA ∆Common = +0.1V

Common Source Current — 10 — µA ∆Common = -0.1V

DGND Digital Ground Voltage 4.5 5.3 5.8 V V+ to pin 36, V+ to V– = 9V

Sink Current — 1.2 — mA ∆DGND = +0.5V

Supply Voltage Range 6 9 12 V V+ to V–

Supply Current Excluding

Common Current

— 0.8 1.3 mA V+ to V– = 9V

CLK

Clock Frequency — 120 360 kHz

DISP

Resistance — 50 — kΩ V

DISP

to V+

Low Battery Flag Activation

Voltage

6.3 7.2 7.7 V V+ to V–

Digital

Continuity Comparator Threshold

Voltages

100 200 — mV V

OUT

pin 27 = High

— 200 400 mV V

OUT

pin 27 = Low

Pull-down Current — 2 10 µA Pins 37, 38, 39

“Weak Output” Current

Sink/Source

— 3/3—µA Pins 20, 21 sink/source

— 3/9—µA Pin 27 sink/source

Pin 22 Source Current — 40 — µA

Pin 22 Sink Current — 3 — µA

TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: V+ to V– = 9V, V

REF

= 1V, T

= +25°C, f

CLK

= 120 kHz, unless otherwise indicated.

Pin numbers refer to 40-pin DIP.

Symbol Parameter Min Typ Max Unit Test Conditions

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400 µA. Currents above

this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.

Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

 2004 Microchip Technology Inc. DS21459C-page 5

TC7129

2.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin No.

40-Pin PDIP

Pin No.

44-Pin PQFP

Pin No.

44-Pin PLCC

Symbol Function

1 40 2 OSC1 Input to first clock inverter.

2 41 3 OSC3 Output of second clock inverter.

3 42 4 ANNUNCIATOR Backplane square wave output for driving annunciators.

443 5B

, C

, CONT Output to display segments.

544 6A

, G

, D

Output to display segments.

617F

, E

, DP

Output to display segments.

728B

, C

LO BATT

Output to display segments.

839A

, G

, D

Output to display segments.

9410F

, E

, DP

Output to display segments.

10 5 11 B

, C

, MINUS Output to display segments.

11 7 13 A

, G

, D

Output to display segments.

12 8 14 F

, E

, DP

Output to display segments.

13 9 15 B

, C

, BC

Output to display segments.

14 10 16 A

, D

, G

Output to display segments.

15 11 17 F

, E

, DP

Output to display segments.

16 12 18 BP

Backplane #3 output to display.

17 13 19 BP

Backplane #2 output to display.

18 14 20 BP

Backplane #1 output to display.

19 15 21 V

DISP

Negative rail for display drivers.

20 16 22 DP

/OR Input: When high, turns on most significant decimal point.

Output: Pulled high when result count exceeds ±19,999.

21 18 24 DP

/UR Input: Second-most significant decimal point on when high.

Output: Pulled high when result count is less than ±1000.

22 19 25 LATCH

/HOLD Input: When floating, ADC operates in Free Run mode. When

pulled high, the last displayed reading is held. When pulled low,

the result counter contents are shown incrementing during the

de-integrate phase of cycle.

Output: Negative going edge occurs when the data latches are

updated. Can be used for converter status signal.

23 20 26 V– Negative power supply terminal.

24 21 27 V+ Positive power supply terminal and positive rail for display

drivers.

25 22 28 INT IN Input to integrator amplifier.

26 23 29 INT OUT Output of integrator amplifier.

27 24 30 CONTINUITY Input: When low, continuity flag on the display is off. When high,

continuity flag is on.

Output: High when voltage between inputs is less than +200 mV.

Low when voltage between inputs is more than +200 mV.

28 25 31 COMMON Sets common mode voltage of 3.2V below V+ for DE, 10X, etc.

Can be used as pre-regulator for external reference.

29 26 32 C

REF

+ Positive side of external reference capacitor.

30 27 33 C

REF

– Negative side of external reference capacitor.

31 29 35 BUFFER Output of buffer amplifier.

32 30 36 IN LO Negative input voltage terminal.

33 31 37 IN HI Positive input voltage terminal.

34 32 38 REF HI Positive reference voltage.

35 33 39 REF LO Negative reference voltage

TC7129

DS21459C-page 6  2004 Microchip Technology Inc.

36 34 40 DGND Internal ground reference for digital section. See Section 4.2.1

“±5V Power Supply”.

37 35 41 RANGE 3 µA pull-down for 200 mV scale. Pulled high externally for 2V

scale.

3 8 3 6 4 2 D P

Internal 3 µA pull-down. When high, decimal point 2 will be on.

39 37 43 DP

Internal 3 µA pull-down. When high, decimal point 1 will be on.

40 38 44 OSC2 Output of first clock inverter. Input of second clock inverter.

— 6,17, 28, 39 12, 23, 34, 1 NC No connection.

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)

Pin No.

40-Pin PDIP

Pin No.

44-Pin PQFP

Pin No.

44-Pin PLCC

Symbol Function

 2004 Microchip Technology Inc. DS21459C-page 7

TC7129

3.0 DETAILED DESCRIPTION

(All pin designations refer to 40-pin PDIP.)

The TC7129 is designed to be the heart of a high-

resolution analog measurement instrument. The only

additional components required are a few passive

elements: a voltage reference, a LCD and a power

source. Most component values are not critical;

substitutes can be chosen based on the information

given below.

The basic circuit for a digital multimeter application is

shown in Figure 3-1. See Section 4.0 “Typical Appli-

cations”, for variations. Typical values for each

component are shown. The sections below give

component selection criteria.

3.1 Oscillator (X

OSC

, C

, R

)

The primary criterion for selecting the crystal oscillator

is to choose a frequency that achieves maximum rejec-

tion of line frequency noise. To do this, the integration

phase should last an integral number of line cycles.

The integration phase of the TC7129 is 10,000 clock

cycles on the 200 mV range and 1000 clock cycles on

the 2V range. One clock cycle is equal to two oscillator

cycles. For 60 Hz rejection, the oscillator frequency

should be chosen so that the period of one line cycle

equals the integration time for the 2V range.

EQUATION 3-1:

This equation gives an oscillator frequency of 120 kHz.

A similar calculation gives an optimum frequency of

100 kHz for 50 Hz rejection.

The resistor and capacitor values are not critical; those

shown work for most applications. In some situations,

the capacitor values may have to be adjusted to

compensate for parasitic capacitance in the circuit. The

capacitors can be low-cost ceramic devices.

Some applications can use a simple RC network

instead of a crystal oscillator. The RC oscillator has

more potential for jitter, especially in the least

significant digit. See Section 4.5 “RC Oscillator”.

3.2 Integrating Resistor (R

INT

)

The integrating resistor sets the charging current for

the integrating capacitor. Choose a value that provides

a current between 5 µA and 20 µA at 2V, the maximum

full-scale input. The typical value chosen gives a

charging current of 13.3 µA:

EQUATION 3-1:

Too high a value for R

INT

increases the sensitivity to

noise pickup and increases errors due to leakage

current. Too low a value degrades the linearity of the

integration, leading to inaccurate readings.

1/60 second = 16.7 msec =

1000 clock cycles *2 OSC cycles/clock cycle

OSC Frequency

CHARGE

150 kΩ

13.3 µA

TC7129

DS21459C-page 8  2004 Microchip Technology Inc.

Figure 3-1: Standard Circuit.

3.3 Integrating Capacitor (C

INT

)

The charge stored in the integrating capacitor during

the integrate phase is directly proportional to the input

voltage. The primary selection criterion for C

INT

is to

choose a value that gives the highest voltage swing

while remaining within the high-linearity portion of the

integrator output range. An integrator swing of 2V is the

recommended value. The capacitor value can be

calculated using the following equation:

EQUATION 3-1:

Using the values derived above (assuming 60 Hz

operation), the equation becomes:

EQUATION 3-2:

The capacitor should have low dielectric absorption to

ensure good integration linearity. Polypropylene and

Tef lo n

capacitors are usually suitable. A good

measurement of the dielectric absorption is to connect

the reference capacitor across the inputs by

connecting:

Pin-to-Pin:

20 → 33 (C

REF

+ to IN HI)

30 → 32 (C

REF

– to IN LO)

A reading between 10,000 and 9998 is acceptable;

anything lower indicates unacceptably high dielectric

absorption.

3.4 Reference Capacitor (C

REF

)

The reference capacitor stores the reference voltage

during several phases of the measurement cycle. Low

leakage is the primary selection criterion for this com-

ponent. The value must be high enough to offset the

effect of stray capacitance at the capacitor terminals. A

value of at least 1 µF is recommended.

1234567

1011

13141516171819

3837

3534

323130

27262524232221

Low Battery Continuity

V+

5 pF

120

kHz

10 pF

0.1 µF

kΩ

0.1

µF

100 kΩ

INT

0.1 µF

V+

– +

330 kΩ

Crystal

REF

1 µF

10 kΩ

BIAS

150 kΩ

INT

OSC1

OSC3

ANNUNC

DISP

/OR

Display Drive Outputs

/UR

LATCH/

HOLD

V–

V+

INT IN

INT OUT

CONTINUITY

COMMON

REF

–

BUFF

IN LO

IN HI

REF HI

REF LO

DGND

RANGE

OSC2

TC7129

INT

x I

INT

SWING

Where t

INT

is the integration time.

INT

= 0.1 µA

16.7 msec x 13.3 µA

 2004 Microchip Technology Inc. DS21459C-page 9

TC7129

3.5 Voltage Reference

REF

, R

REF

, R

BIAS

, C

)

The reference potentiometer (R

REF

) provides an

adjustment for adjusting the reference voltage; any

value above 20 kΩ is adequate. The bias resistor

BIAS

) limits the current through D

REF

to less than

150 µA. The reference filter capacitor (C

) forms an

RC filter with R

BIAS

to help eliminate noise.

3.6 Input Filter (R

, C

)

For added stability, an RC input noise filter is usually

included in the circuit. The input filter resistor value

should not exceed 100 kΩ. A typical RC time constant

value is 16.7 msec to help reject line frequency noise.

The input filter capacitor should have low leakage for a

high-impedance input.

3.7 Battery

The typical circuit uses a 9V battery as a power source.

However, any value between 6V and 12V can be used.

For operation from batteries with voltages lower than

6V and for operation from power supplies, see

Section 4.2 “Powering the TC7129”.

4.0 TYPICAL APPLICATIONS

4.1 TC7129 as a Replacement Part

The TC7129 is a direct pin-for-pin replacement part for

the ICL7129. Note, however, that the ICL7129 requires

a capacitor and resistor between pins 26 and 28 for

phase compensation. Since the TC7129 uses internal

phase compensation, these parts are not required and,

in fact, must be removed from the circuit for stable

operation.

4.2 Powering the TC7129

While the most common power source for the TC7129

is a 9V battery, there are other possibilities. Some of

the more common ones are explained below.

4.2.1 ±5V Power Supply

Measurements are made with respect to power supply

ground. DGND (pin 36) is set internally to about 5V less

than V

+ (pin 24); it is not intended to be a power supply

input and must not be tied directly to power supply

ground. It can be used as a reference for external logic,

as explained in Section 4.3 “Connecting to External

Logic”, (see Figure 4-1).

Figure 4-1: Powering the TC7129 From

a ±5V Power Supply.

4.2.2 Low Voltage Battery Source

A battery with voltage between 3.8V and 6V can be

used to power the TC7129 when used with a voltage

doubler circuit, as shown in Figure 4-2. The voltage

doubler uses the TC7660 DC-to-DC voltage converter

and two external capacitors.

Figure 4-2: Powering the TC7129 From

a Low-Voltage Battery.

V–

V+

REF HI

REF LO

IN HI

COMMON

IN LO

DGND

–

-5V

0.1 µF

+5V

0.1 µF

TC7129

0.1 µF

V–

TC7129

V+

REF HI

REF LO

IN HI

COMMON

IN LO

DGND

3.8V

10 µF

–

TC7660

TC7129

DS21459C-page 10  2004 Microchip Technology Inc.

4.2.3 +5V Power Supply

Measurements are made with respect to power supply

ground. COMMON (pin 28) is connected to REF LO

(pin 35). A voltage doubler is needed, since the supply

voltage is less than the 6V minimum needed by the

TC7129. DGND (pin 36) must be isolated from power

supply ground (see Figure 4-3).

Figure 4-3: Powering the TC7129 From

a +5V Power Supply.

4.3 Connecting to External Logic

External logic can be directly referenced to DGND

(pin 36), provided that the supply current of the external

logic does not exceed the sink current of DGND

(Figure 4-4). A safe value for DGND sink current is

1.2 mA. If the sink current is expected to exceed this

value, a buffer is recommended (see Figure 4-5).

Figure 4-4: External Logic Referenced

Directly to DGND.

Figure 4-5: External Logic Referenced

to DGND with Buffer.

4.4 Temperature Compensation

For most applications, V

DISP

(pin 19) can be connected

directly to DGND (pin 36). For applications with a wide

temperature range, some LCDs require that the drive

levels vary with temperature to maintain good viewing

angle and display contrast. Figure 4-6 shows two

circuits that can be adjusted to give temperature com-

pensation of about 10 mV/°C between V+ (pin 24) and

DISP

. The diode between DGND and V

DISP

should

have a low turn-on voltage because V

DISP

cannot

exceed 0.3V below DGND.

V–

V+

DGND

10 µF

–

TC7660

V+

GND

0.1 µF

+5V

TC7129

External

Logic

DGND

LOGIC

TC7129

V-

–

External

Logic

LOGIC

DGND

V+

TC7129

V–

 2004 Microchip Technology Inc. DS21459C-page 11

TC7129

Figure 4-6: Temperature Compensating Circuits.

4.5 RC Oscillator

For applications in which 3-1/2 digit (100 µV) resolution

is sufficient, an RC oscillator is adequate. A recom-

mended value for the capacitor is 51 pF. Other values

can be used as long as they are sufficiently larger than

the circuit parasitic capacitance. The resistor value is

calculated as:

EQUATION 4-1:

For 120 kHz frequency and C = 51 pF, the calculated

value of R is 75 kΩ. The RC oscillator and the crystal

oscillator circuits are shown in Figure 4-7.

Figure 4-7: Oscillator Circuits.

4.6 Measuring Techniques

Two important techniques are used in the TC7129: suc-

cessive integration and digital auto-zeroing. Succes-

sive integration is a refinement to the traditional dual-

slope conversion technique.

4.7 Dual-Slope Conversion

A dual-slope conversion has two basic phases: inte-

grate and de-integrate. During the integrate phase, the

input signal is integrated for a fixed period of time; the

integrated voltage level is thus proportional to the input

voltage. During the de-integrate phase, the integrated

voltage is ramped down at a fixed slope, and a counter

counts the clock cycles until the integrator voltage

crosses zero. The count is a measurement of the time

to ramp the integrated voltage to zero and is, therefore,

proportional to the input voltage being measured. This

count can then be scaled and displayed as a measure-

ment of the input voltage. Figure 4-8 shows the phases

of the dual-slope conversion.

Figure 4-8: Dual-Slope Conversion.

The dual-slope method has a fundamental limitation.

The count can only stop on a clock cycle, so that mea-

surement accuracy is limited to the clock frequency. In

addition, a delay in the zero-crossing comparator can

add to the inaccuracy. Figure 4-9 shows these errors in

an actual measurement.

TC7129

–

1N4148

5 kΩ

75 kΩ

200 kΩ

39 kΩ

V–

V+

DISP

DGND

TC7129

2N2222

39 kΩ

V–

V+

DISP

DGND

20 kΩ

18 kΩ

R =

0.45

Freq * C

TC7129

1 40 2

270 k

Ω

10 pF

V+

120 kHz

5 pF

V+

1 40 2

51 pF

75 k

Ω

De-integrate

Zero

Crossing

Time

Integrate

TC7129

DS21459C-page 12  2004 Microchip Technology Inc.

Figure 4-9: Accuracy Errors in Dual-Slope Conversion.

Figure 4-10: Integration Waveform.

Integrate

De-integrate

Time

Clock Pulses

Overshoot due to zero-crossing between

clock pulses

Integrator Residue Voltage

Overshoot caused by comparato

delay of 1 clock pulse

INT

Integrate

De-integrate

REST X10

Zero Integrate

and Latch

REST X10

Zero Integrate

Integrator

Residual Voltage

TC7129

Note: Shaded area greatly expanded in time and amplitude.

 2004 Microchip Technology Inc. DS21459C-page 13

TC7129

4.8 Successive Integration

The successive integration technique picks up where

dual-slope conversion ends. The overshoot voltage

shown in Figure 4-9 (called the “integrator residue

voltage”) is measured to obtain a correction to the initial

count. Figure 4-10 shows the cycles in a successive

integration measurement.

The waveform shown is for a negative input signal. The

sequence of events during the measurement cycle is

shown in Table 4-1.

TABLE 4-1: MEASUREMENT CYCLE

SEQUENCE

4.9 Digital Auto-Zeroing

To eliminate the effect of amplifier offset errors, the

TC7129 uses a digital auto-zeroing technique. After the

input voltage is measured as described above, the

measurement is repeated with the inputs shorted

internally. The reading with inputs shorted is a

measurement of the internal errors and is subtracted

from the previous reading to obtain a corrected

measurement. Digital auto-zeroing eliminates the need

for an external auto-zeroing capacitor used in other

ADCs.

4.10 Inside the TC7129

Figure 4-11 shows a simplified block diagram of the

TC7129.

Phase Description

INT

Input signal is integrated for fixed time (1000 clock

cycles on 2V scale, 10,000 on 200 mV).

Integrator voltage is ramped to zero. Counter

counts up until zero-crossing to produce reading

accurate to 3-1/2 digits. Residue represents an

overshoot of the actual input voltage.

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and inverted.

Integrator voltage is ramped to zero. Counter

counts down until zero-crossing to correct reading

to 4-1/2 digits. Residue represents an undershoot

of the actual input voltage.

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and inverted.

Integrator voltage is ramped to zero. Counter

counts up until zero-crossing to correct reading to

5-1/2 digits. Residue is discarded.

TC7129

DS21459C-page 14  2004 Microchip Technology Inc.

Figure 4-11: TC7129 Functional Block Diagram.

Figure 4-12: Integrator Block Diagram.

Low Battery Continuity

Segment Drives

Backplane

Drives

Latch, Decode Display Multiplexer

Up/Down Results Counter

Sequence Counter/Decoder

Control Logic

Analog Section

OSC1

OSC2

OSC3

RANGE

L/H

CONT

V+

V–

DGND

COMMON IN

BUFF

UR/DP

OR/DP

REF HI

REF LO

INT OUT

INT IN

Annunciator

Drive

DISP

TC7129

Common

REF HI

Buffer

Integrator

ZI, X10

Comparator 1

200 mV

REF

INT

IN HI

–

REF LO

IN LO

–

DE- DE+

DE+

DE–

100 pF

–

Continuity

INT

Continuity

Comparator

500 k

Ω

REST

To Display Driver

Comparator 2

To Digital

Section

TC7129

INT

X10

 2004 Microchip Technology Inc. DS21459C-page 15

TC7129

4.11 Integrator Section

The integrator section includes the integrator, compar-

ator, input buffer amplifier and analog switches (see

Table 4-2) used to change the circuit configuration

during the separate measurement phases described

earlier. (See Figure 4-12).

The buffer amplifier has a common mode input voltage

range from 1.5V above V– to 1V below V+. The integra-

tor amplifier can swing to within 0.3V of the rails.

However, for best linearity, the swing is usually limited

to within 1V. Both amplifiers can supply up to 80 µA of

output current, but should be limited to 20 µA for good

linearity.

4.12 Continuity Indicator

A comparator with a 200 mV threshold is connected

between IN HI (pin 33) and IN LO (pin 32). Whenever

the voltage between inputs is less than 200mV, the

CONTINUITY output (pin 27) will be pulled high,

activating the continuity annunciator on the display.

The continuity pin can also be used as an input to drive

the continuity annunciator directly from an external

source (see Figure 4-13).

A schematic of the input/output nature of this pin is also

shown in Figure 4-14.

Figure 4-13: Continuity Indicator Circuit.

Figure 4-14: Input/Output Pin Schematic.

4.13 Common and Digital Ground

The common and digital ground (DGND) outputs are

generated from internal zener diodes. The voltage

between V+ and DGND is the internal supply voltage

for the digital section of the TC7129. Common can

source approximately 12 µA; DGND has essentially no

source capability (see Figure 4-15).

TABLE 4-2: SWITCH LEGENDS

Label Description

Label Meaning.

DE Open during all de-integrate phases.

DE– Closed during all de-integrate phases when

input voltage is negative.

DE+ Closed during all de-integrate phases when

input voltage is positive.

INT

Closed during the first integrate phase

(measurement of the input voltage).

INT

Closed during the second integrate phase

(measurement of the amplifier offset).

INT Open during both integrate phases.

REST Closed during the rest phase.

ZI Closed during the zero integrate phase.

X10 Closed during the X10 phase.

X10 Open during the X10 phase.

COM

Buffer

200 mV

IN HI

–

IN LO

–

CONT

500 k

Ω

To Display Driver

(Not Latched)

TC7129

500 kΩ

/OR, Pin 20

/UR, Pin 21

LATCH/HOLD Pin 22

CONTINUITY, Pin 27

TC7129

DS21459C-page 16  2004 Microchip Technology Inc.

Figure 4-15: Digital Ground (DGND) and

Common Outputs.

4.14 Low Battery

The low battery annunciator turns on when supply volt-

age between V– and V+ drops below 6.8V. The internal

zener diode has a threshold of 6.3V. When the supply

voltage drops below 6.8V, the transistor tied to V– turns

off pulling the “Low Battery” point high.

4.15 Sequence and Results Counter

A sequence counter and associated control logic pro-

vide signals that operate the analog switches in the

integrator section. The comparator output from the inte-

grator gates the results counter. The results counter is

a six-section up/down decade counter that holds the

intermediate results from each successive integration.

4.16 Overrange and Underrange

Outputs

When the results counter holds a value greater than

±19,999, the DP

/OR output (Pin 20) is driven high.

When the results counter value is less than ±1000, the

/UR output (Pin 21) is driven high. Both signals are

valid on the falling edge of LATCH

/HOLD (L/H) and do

not change until the end of the next conversion cycle.

The signals are updated at the end of each conversion,

unless the L

/H input (Pin 22) is held high. Pins 20 and

21 can also be used as inputs for external control of

decimal points 3 and 4. Figure 4-14 shows a schematic

of the input/output nature of these pins.

4.17 LATCH/Hold

The L/H output goes low during the last 100 cycles of

each conversion. This pulse latches the conversion

data into the display driver section of the TC7129. This

pin can also be used as an input. When driven high, the

display will not be updated; the previous reading is

displayed. When driven low, the display reading is not

latched; the sequence counter reading will be

displayed. Since the counter is counting much faster

than the backplanes are being updated, the reading

shown in this mode is somewhat erratic.

4.18 Display Driver

The TC7129 drives a triplexed LCD with three back-

planes. The LCD can include decimal points, polarity

sign and annunciators for continuity and low battery.

Figure 4-16 shows the assignment of the display

segments to the backplanes and segment drive lines.

The backplane drive frequency is obtained by dividing

the oscillator frequency by 1200. This results in a back-

plane drive frequency of 100 Hz for 60 Hz operation

(120 kHz crystal) and 83.3 Hz for 50 Hz operation

(100 kHz crystal).

Backplane waveforms are shown in Figure 4-17.

These appear on outputs BP

, BP

(pins 16, 17

and 18). They remain the same, regardless of the seg-

ments being driven.

Other display output lines (pins 4 through 15) have

waveforms that vary depending on the displayed

values. Figure 4-18 shows a set of waveforms for the

A, G, D outputs (pins 5, 8, 11 and 14) for several

combinations of “ON” segments.

The ANNUNCIATOR DRIVE output (pin 3) is a square

wave, running at the backplane frequency (100 Hz or

83.3 Hz) with a peak-to-peak voltage equal to DGND

voltage. Connecting an annunciator to pin 3 turns it on;

connecting it to its backplane turns it off.

–

12 µA

TC7129

Logic

Section

3.2V

V+

V–

COM

DGND

 2004 Microchip Technology Inc. DS21459C-page 17

TC7129

Figure 4-16: Display Segment Assignments.

Figure 4-17: Backplane Waveforms.

Figure 4-18: Typical Display Output

Waveforms.

Low Battery

Low Battery Continuity

MINUS

Continuity

Low Battery

Backplane

Connections

Continuity

DISP

b Segment

Line

All Off

a Segment

d, g Off

a, g On

d Off

All On

TC7129

DS21459C-page 18  2004 Microchip Technology Inc.

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Package marking data not available a this time.

5.2 Taping Forms

User Direction of Feed

P, Pitch

S tandard R eel Component Orientation

Reverse Reel Component Orientation

W, Width

of Carrier

Tape

Pin 1

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

PIN 1

Standard Reel Component Orientation

for TR Suffix Device

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PQFP 24 mm 16 mm 500 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

Note: Drawing does not represent total number of pins.

 2004 Microchip Technology Inc. DS21459C-page 19

TC7129

40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)

1510515105

Mold Draft Angle Bottom

1510515105

Mold Draft Angle Top

17.2716.5115.75.680.650.620eBOverall Row Spacing §

0.560.460.36.022.018.014BLower Lead Width

1.781.270.76.070.050.030B1Upper Lead Width

0.380.290.20.015.012.008

Lead Thickness

3.433.303.05.135.130.120LTip to Seating Plane

52.4552.2651.942.0652.0582.045DOverall Length

14.2213.8413.46.560.545.530E1Molded Package Width

15.8815.2415.11.625.600.595EShoulder to Shoulder Width

0.38.015A1Base to Seating Plane

4.063.813.56.160.150.140A2Molded Package Thickness

4.834.454.06.190.175.160ATop to Seating Plane

2.54.100

Pitch

4040

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

§ Significant Characteristic

TC7129

DS21459C-page 20  2004 Microchip Technology Inc.

44-Lead Plastic Leaded Chip Carrier (LW) – Square (PLCC)

CH2 x 45° CH1 x 45°

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.530.510.33.021.020.013B

0.810.740.66.032.029.026B1Upper Lead Width

0.330.270.20.013.011.008

Lead Thickness

1111n1Pins per Side

16.0015.7514.99.630.620.590

Footprint Length

16.0015.7514.99.630.620.590E2Footprint Width

16.6616.5916.51.656.653.650D1Molded Package Length

16.6616.5916.51.656.653.650E1Molded Package Width

17.6517.5317.40.695.690.685DOverall Length

17.6517.5317.40.695.690.685EOverall Width

0.250.130.00.010.005.000CH2Corner Chamfer (others)

1.271.141.02.050.045.040CH1Corner Chamfer 1

0.860.740.61.034.029.024

Side 1 Chamfer Height

0.51.020A1Standoff §

Molded Package Thickness

4.574.394.19.180.173.165AOverall Height

1.27.050

Pitch

4444

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

#leads=n1

35°

.145 .153 .160 3.68 3.87 4.06

.028 .035 0.71 0.89

Lower Lead Width

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

§ Significant Characteristic

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Microchip Technology TC7129 General Description Manual

Microchip Technology TC7129 General Description Manual

Microchip Technology TC7129 General Description Manual

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