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Copyright © 2013-2014 ARM. All rights reserved.
ARM DDI 0500D (ID021414)
ARM® Cortex®-A53 MPCore Processor
Revision: r0p2
Technical Reference Manual
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. ii
ID021414 Non-Confidential
ARM Cortex-A53 MPCore Processor
Technical Reference Manual
Copyright © 2013-2014 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
09 August 2013 A Confidential Release for r0p0
05 November 2013 B Confidential Release for r0p1
10 January 2014 C Confidential Release for r0p2
14 February 2014 D Non-Confidential Second release for r0p2
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Contents
ARM Cortex-A53 MPCore Processor Technical
Reference Manual
Preface
About this book .......................................................................................................... vii
Feedback .................................................................................................................... xi
Chapter 1 Introduction
1.1 About the Cortex-A53 processor ............................................................................. 1-2
1.2 Compliance .............................................................................................................. 1-3
1.3 Features ................................................................................................................... 1-5
1.4 Interfaces ................................................................................................................. 1-6
1.5 Implementation options ............................................................................................ 1-7
1.6 Test features ............................................................................................................ 1-9
1.7 Product documentation and design flow ................................................................ 1-10
1.8 Product revisions ................................................................................................... 1-12
Chapter 2 Functional Description
2.1 About the Cortex-A53 processor functions .............................................................. 2-2
2.2 Interfaces ................................................................................................................. 2-7
2.3 Clocking and resets ................................................................................................. 2-9
2.4 Power management ............................................................................................... 2-16
Chapter 3 Programmers Model
3.1 About the programmers model ................................................................................ 3-2
3.2 ARMv8-A architecture concepts .............................................................................. 3-4
Chapter 4 System Control
4.1 About system control ............................................................................................... 4-2
Contents
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4.2 AArch64 register summary ...................................................................................... 4-3
4.3 AArch64 register descriptions ................................................................................ 4-14
4.4 AArch32 register summary .................................................................................. 4-135
4.5 AArch32 register descriptions .............................................................................. 4-157
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................................ 5-2
5.2 TLB organization ...................................................................................................... 5-3
5.3 TLB match process .................................................................................................. 5-4
5.4 External aborts ......................................................................................................... 5-5
Chapter 6 Level 1 Memory System
6.1 About the L1 memory system .................................................................................. 6-2
6.2 Cache behavior ........................................................................................................ 6-3
6.3 Support for v8 memory types ................................................................................... 6-6
6.4 L1 Instruction memory system ................................................................................. 6-7
6.5 L1 Data memory system .......................................................................................... 6-9
6.6 Data prefetching .................................................................................................... 6-12
6.7 Direct access to internal memory .......................................................................... 6-13
Chapter 7 Level 2 Memory System
7.1 About the L2 memory system .................................................................................. 7-2
7.2 Snoop Control Unit .................................................................................................. 7-3
7.3 ACE master interface ............................................................................................... 7-6
7.4 CHI master interface .............................................................................................. 7-13
7.5 Additional memory attributes ................................................................................. 7-17
7.6 Optional integrated L2 cache ................................................................................. 7-18
7.7 ACP ....................................................................................................................... 7-19
Chapter 8 Cache Protection
8.1 Cache protection behavior ....................................................................................... 8-2
8.2 Error reporting .......................................................................................................... 8-4
Chapter 9 Generic Interrupt Controller CPU Interface
9.1 About the GIC CPU Interface .................................................................................. 9-2
9.2 GIC programmers model ......................................................................................... 9-3
Chapter 10 Generic Timer
10.1 About the Generic Timer ........................................................................................ 10-2
10.2 Generic Timer functional description ..................................................................... 10-3
10.3 Generic Timer register summary ........................................................................... 10-4
Chapter 11 Debug
11.1 About debug .......................................................................................................... 11-2
11.2 Debug register interfaces ....................................................................................... 11-4
11.3 AArch64 debug register summary ......................................................................... 11-6
11.4 AArch64 debug register descriptions ..................................................................... 11-8
11.5 AArch32 debug register summary ....................................................................... 11-15
11.6 AArch32 debug register descriptions ................................................................... 11-17
11.7 Memory-mapped register summary ..................................................................... 11-21
11.8 Memory-mapped register descriptions ................................................................ 11-25
11.9 Debug events ....................................................................................................... 11-36
11.10 External debug interface ...................................................................................... 11-37
11.11 ROM table ............................................................................................................ 11-41
Chapter 12 Performance Monitor Unit
12.1 About the PMU ...................................................................................................... 12-2
12.2 PMU functional description .................................................................................... 12-3
Contents
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12.3 AArch64 PMU register summary ........................................................................... 12-5
12.4 AArch64 PMU register descriptions ....................................................................... 12-7
12.5 AArch32 PMU register summary ......................................................................... 12-14
12.6 AArch32 PMU register descriptions ..................................................................... 12-16
12.7 Memory-mapped register summary ..................................................................... 12-23
12.8 Memory-mapped register descriptions ................................................................ 12-26
12.9 Events .................................................................................................................. 12-36
12.10 Interrupts .............................................................................................................. 12-40
12.11 Exporting PMU events ......................................................................................... 12-41
Chapter 13 Embedded Trace Macrocell
13.1 About the ETM ....................................................................................................... 13-2
13.2 ETM trace unit generation options and resources ................................................. 13-3
13.3 ETM trace unit functional description ..................................................................... 13-5
13.4 Reset ..................................................................................................................... 13-7
13.5 Modes of operation and execution ......................................................................... 13-8
13.6 ETM trace unit register interfaces .......................................................................... 13-9
13.7 ETM register summary ........................................................................................ 13-10
13.8 ETM register descriptions .................................................................................... 13-13
13.9 Interaction with debug and performance monitoring unit ..................................... 13-76
Chapter 14 Cross Trigger
14.1 About the cross trigger ........................................................................................... 14-2
14.2 Trigger inputs and outputs ..................................................................................... 14-3
14.3 Cortex-A53 CTM .................................................................................................... 14-4
14.4 Cross trigger register summary ............................................................................. 14-5
14.5 Cross trigger register descriptions ......................................................................... 14-8
Appendix A Signal Descriptions
A.1 About the signal descriptions ................................................................................... A-2
A.2 Clock signals ............................................................................................................ A-3
A.3 Reset signals ........................................................................................................... A-4
A.4 Configuration signals ............................................................................................... A-5
A.5 Generic Interrupt Controller signals ......................................................................... A-6
A.6 Generic Timer signals .............................................................................................. A-8
A.7 Power management signals .................................................................................... A-9
A.8 L2 error signals ...................................................................................................... A-11
A.9 ACE and CHI interface signals .............................................................................. A-12
A.10 CHI interface signals .............................................................................................. A-13
A.11 ACE interface signals ............................................................................................ A-17
A.12 ACP interface signals ............................................................................................ A-22
A.13 External debug interface ........................................................................................ A-25
A.14 ATB interface signals ............................................................................................. A-28
A.15 Miscellaneous ETM trace unit signals ................................................................... A-29
A.16 CTI interface signals .............................................................................................. A-30
A.17 PMU interface signals ............................................................................................ A-31
A.18 DFT and MBIST interface signals .......................................................................... A-32
Appendix B Cortex-A53 Processor AArch32 unpredictable Behaviors
B.1 Use of R15 by Instruction ........................................................................................ B-3
B.2 unpredictable instructions within an IT Block ........................................................... B-4
B.3 Load/Store accesses crossing page boundaries ..................................................... B-5
B.4 ARMv8 Debug unpredictable behaviors .................................................................. B-6
B.5 Other unpredictable behaviors ............................................................................... B-11
Appendix C Revisions
Preface
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About this book
This book is for the Cortex-A53 MPCore processor. This is a cluster device that has between
one and four cores.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for
example, r1p2, where:
rm Identifies the major revision of the product, for example, r1.
pn Identifies the minor revision or modification status of the product, for example,
p2.
Intended audience
This book is written for system designers, system integrators, and programmers who are
designing or programming a System-on-Chip (SoC) that uses the Cortex-A53 processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the Cortex-A53 processor and descriptions of the
major features.
Chapter 2 Functional Description
Read this for a description of the functionality of the Cortex-A53 processor.
Chapter 3 Programmers Model
Read this for a description of the programmers model.
Chapter 4 System Control
Read this for a description of the system registers and programming information.
Chapter 5 Memory Management Unit
Read this for a description of the Memory Management Unit (MMU).
Chapter 6 Level 1 Memory System
Read this for a description of the Level 1 (L1) memory system.
Chapter 7 Level 2 Memory System
Read this for a description of the Level 2 (L2) memory system.
Chapter 8 Cache Protection
Read this for a description of the cache protection.
Chapter 9 Generic Interrupt Controller CPU Interface
Read this for a description of the Generic Interrupt Controller (GIC) CPU
Interface.
Chapter 10 Generic Timer
Read this for a description of the Generic Timer.
Preface
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Chapter 11 Debug
Read this for a description of the debug registers and shows examples of how to
use them.
Chapter 12 Performance Monitor Unit
Read this for a description of the Performance Monitor Unit (PMU).
Chapter 13 Embedded Trace Macrocell
Read this for a description of the Embedded Trace Macrocell (ETM) for the
Cortex-A53 processor.
Chapter 14 Cross Trigger
Read this for a description of the cross trigger interfaces.
Appendix A Signal Descriptions
Read this for a description of the signals in the Cortex-A53 processor.
Appendix B Cortex-A53 Processor AArch32 unpredictable Behaviors
Read this for a description of specific Cortex-A53 processor UNPREDICTABLE
behaviors.
Appendix C Revisions
Read this for a description of the technical changes between released issues of this
book.
Glossary
The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for
those terms. The ARM® Glossary does not contain terms that are industry standard unless the
ARM meaning differs from the generally accepted meaning.
See ARM® Glossary, http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html.
Conventions
This book uses the conventions that are described in:
•Typographical conventions.
•Timing diagrams on page ix.
•Signals on page ix.
Typographical conventions
The following table describes the typographical conventions:
Typographical conventions
Style Purpose
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive
lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
Preface
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Timing diagrams
The figure Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are UNDEFINED, so the bus or signal can assume any value within
the shaded area at that time. The actual level is unimportant and does not affect normal
operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This section lists publications by ARM and by third parties.
See Infocenter,
http://infocenter.arm.com
, for access to ARM documentation.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM® Glossary.
For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Typographical conventions (continued)
Style Purpose
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Preface
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ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
•ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
(ARM DDI 0406).
•ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
(ARM DDI 0487).
•ARM® Cortex®-A53 MPCore Processor Advanced SIMD and Floating-point Extension
Technical Reference Manual (ARM DDI 0502).
•ARM® Cortex®-A Series Programmer’s Guide (ARM DEN 0013).
•ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and
ACE-Lite (ARM IHI 0022).
•ARM® AMBA® APB Protocol Specification (ARM IHI 0024).
•ARM® CoreSight™ Architecture Specification (ARM IHI 0029).
•ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 (ARM IHI 0031).
•ARM® AMBA® 4 ATB Protocol Specification (ARM IHI 0032).
•ARM® Generic Interrupt Controller Architecture Specification (ARM IHI 0048).
•ARM® ETM™ Architecture Specification, ETMv4 (ARM IHI 0064).
The following confidential books are only available to licensees:
•ARM® Cortex™-A53 MPCore Processor Cryptography Extension Technical Reference
Manual (ARM DDI 0501).
•ARM® Cortex®-A53 MPCore Processor Configuration and Sign-off Guide
(ARM DII 0281).
•ARM® Cortex®-A53 MPCore Processor Integration Manual (ARM DIT 0036).
•ARM® AMBA® 5 CHI Protocol Specification (ARM IHI 0050).
•ARMv8 Debug Implementation Envelope
•ARMv8 AArch32 UNPREDICTABLE behaviors
Other publications
This section lists relevant documents published by third parties:
•ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic.
Note
ARM floating-point terminology is largely based on the earlier ANSI/IEEE Std 754-1985
issue of the standard. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A
architecture profile for more information.
Preface
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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to
. Give:
• The title.
• The number, ARM DDI 0500D.
• The page numbers to which your comments apply.
• A concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Note
ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the
quality of the represented document when used with any other PDF reader.
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Chapter 1
Introduction
This chapter introduces the Cortex-A53 processor and its features. It contains the following
sections:
•About the Cortex-A53 processor on page 1-2.
•Compliance on page 1-3.
•Features on page 1-5.
•Interfaces on page 1-6.
•Implementation options on page 1-7.
•Test fea tures on page 1-9.
•Product documentation and design flow on page 1-10.
•Product revisions on page 1-12.
Introduction
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1.1 About the Cortex-A53 processor
The Cortex-A53 processor is a mid-range, low-power processor that implements the ARMv8-A
architecture. The Cortex-A53 processor has one to four cores, each with an L1 memory system
and a single shared L2 cache.
Figure 1-1 shows an example of a Cortex-A53 MPCore configuration with four cores and either
an ACE or a CHI interface.
Figure 1-1 Example Cortex-A53 processor configuration
See About the Cortex-A53 processor functions on page 2-2 for more information about the
functional components.
Core 3*
Core 2*
Core 1*
AXI slave interface
Core 0
Timer events
Counter
ICDT*, nIRQ, nFIQ
PMU
ATB
Debug
Core
Trace
Debug
Interrupt
Timer ACP*
Power
management
Test
ACE or CHI
master interface
Power control
DFT
MBIST
Cortex-A53 processor
* Optional
APB debug
Clocks
Resets
Configuration
Master
interface
ICCT*, nVCPUMNTIRQ
Introduction
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1.2 Compliance
The Cortex-A53 processor complies with, or implements, the specifications described in:
•ARM architecture.
•Interconnect architecture.
•Generic Interrupt Controller architecture on page 1-4.
•Generic Timer architecture on page 1-4.
•Debug architecture on page 1-4.
•Embedded Trace Macrocell architecture on page 1-4.
This TRM complements architecture reference manuals, architecture specifications, protocol
specifications, and relevant external standards. It does not duplicate information from these
sources.
1.2.1 ARM architecture
The Cortex-A53 processor implements the ARMv8-A architecture. This includes:
• Support for both AArch32 and AArch64 Execution states.
• Support for all exception levels, EL0, EL1, EL2, and EL3, in each execution state.
• The A32 instruction set, previously called the ARM instruction set.
• The T32 instruction set, previously called the Thumb instruction set.
• The A64 instruction set.
The Cortex-A53 processor supports the following architecture extensions:
• Optional Advanced SIMD and Floating-point Extension for integer and floating-point
vector operations.
Note
— The Advanced SIMD architecture, its associated implementations, and supporting
software, are commonly referred to as NEON technology.
— To perform floating-point operations, you must implement the Advanced SIMD and
Floating-point Extension. There is no software API library for floating-point in the
ARMv8-A architecture.
— You cannot implement floating-point without Advanced SIMD.
• Optional ARMv8 Cryptography Extensions.
Note
You cannot implement the Cryptography Extensions without Advanced SIMD and
Floating-point.
See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for
more information.
1.2.2 Interconnect architecture
The Cortex-A53 bus interface natively supports one of:
• AMBA 4 ACE bus architecture. See the ARM® AMBA® AXI and ACE Protocol
Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.
• AMBA 5 CHI bus architecture. See the ARM® AMBA® 5 CHI Protocol Specification.
Introduction
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1.2.3 Generic Interrupt Controller architecture
The Cortex-A53 processor implements the Generic Interrupt Controller (GIC) v4 architecture.
The Cortex-A53 processor includes only the GIC CPU Interface. See the ARM® Generic
Interrupt Controller Architecture Specification.
1.2.4 Generic Timer architecture
The Cortex-A53 processor implements the ARM Generic Timer architecture. See the ARM®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
1.2.5 Debug architecture
The Cortex-A53 processor implements the ARMv8 Debug architecture. The CoreSight Cross
Trigger Interface (CTI) enables the debug logic, the Embedded Trace Macrocell (ETM), and the
Performance Monitor Unit (PMU), to interact with each other and with other CoreSight
components. For more information, see the:
•ARM® CoreSight™ Architecture Specification.
•ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
1.2.6 Embedded Trace Macrocell architecture
The Cortex-A53 processor implements the ETMv4 architecture. See the ARM® ETM™
Architecture Specification, ETMv4.
Introduction
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1.3 Features
The Cortex-A53 processor includes the following features:
• Full implementation of the ARMv8-A architecture instruction set with the architecture
options listed in ARM architecture on page 1-3.
• In-order pipeline with symmetric dual-issue of most instructions.
•Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU).
•Level 2 (L2) memory system providing cluster memory coherency, optionally including
an L2 cache.
Introduction
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1.4 Interfaces
The Cortex-A53 processor has the following external interfaces:
• Memory interface that implements either an ACE or CHI interface.
• Optional Accelerator Coherency Port (ACP) that implements an AXI slave interface.
• Debug interface that implements an APB slave interface.
• Trace interface that implements an ATB interface.
•CTI.
•Design for Test (DFT).
•Memory Built-In Self Test (MBIST).
• Q-channel, for power management.
See Interfaces on page 2-7 for more information on each of these interfaces.
Introduction
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1.5 Implementation options
Table 1-1 lists the implementation options at build time for the Cortex-A53 processor.
Note
• The L1 duplicate tags in the SCU are protected by the CPU cache protection.
• There is no option to implement floating-point without Advanced SIMD.
• There is no option to implement the Cryptography Extension without the Advanced
SIMD and Floating-point Extension.
Table 1-1 Cortex-A53 processor implementation options
Feature Range of options
Number of cores Up to four cores.
L1 Instruction cache size • 8K.
•16K.
•32K.
•64K.
L1 Data cache size • 8K.
•16K.
•32K.
•64K.
L2 cache Included or not.
L2 cache size • 128K.
•256K.
•512K.
• 1024K.
• 2048K.
L2 data RAM input latency • 1 cycle.
• 2 cycles.
L2 data RAM output latency • 2 cycles.
• 3 cycles.
SCU-L2 cache protection Included or not.
Advanced SIMD and Floating-point Extension Included or not.
Cryptography Extension Included or not.
CPU cache protectiona
a. Not implemented if the L2 cache is implemented and SCU-L2 cache protection
is not implemented.
Included or not.
AMBA 5 CHI or AMBA 4 ACE interface • AMBA 5 CHI.
• AMBA 4 ACE.
Accelerator Coherency Port (ACP)b
b. Not implemented if the Cortex-A53 processor does not include an L2 cache.
Included or not.
v7 or v8 Debug memory map • v8 Debug memory map.
• v7 Debug memory map.
Introduction
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• All cores share a common L2 cache.
1.5.1 Processor configuration
All cores in a cluster have identical configurations, that were determined during the build
configuration. These configurations cannot be changed by software:
• Either all of the cores have L1 cache protection, or none have.
• Either all of the cores have Advanced SIMD and Floating-point Extensions, or none have.
• Either all of the cores have Cryptography Extensions, or none have.
• All cores must have the same size L1 caches as each other.
Introduction
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1.6 Test features
The Cortex-A53 processor provides test signals that enable the use of both ATPG and MBIST
to test the processor and its memory arrays. See Appendix A Signal Descriptions for more
information.
/
