XMOS XS1-L1 is a hardware reference design for a USB audio interface using the XMOS XS1-L1 event-driven processor. The XS1-L1 can implement a complete USB 2.0 high-speed device compliant with release 2.0 of the audio USB device class. Here is a brief overview of its capabilities:
-
Audio capabilities:
- Streams bit-perfect audio data up to 24-bit @ 192kHz
- Supports standard sample rates: 44.1kHz, 48kHz, 88.2kHz, 96kHz, 192kHz
- Optical S/PDIF digital audio output
- Stereo line-level audio input and output
-
Other features:
- USB bus-powered, no external power supply required
XMOS XS1-L1 is a hardware reference design for a USB audio interface using the XMOS XS1-L1 event-driven processor. The XS1-L1 can implement a complete USB 2.0 high-speed device compliant with release 2.0 of the audio USB device class. Here is a brief overview of its capabilities:
-
Audio capabilities:
- Streams bit-perfect audio data up to 24-bit @ 192kHz
- Supports standard sample rates: 44.1kHz, 48kHz, 88.2kHz, 96kHz, 192kHz
- Optical S/PDIF digital audio output
- Stereo line-level audio input and output
-
Other features:
- USB bus-powered, no external power supply required
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 2/18
1 Introduction
The USB Audio 2.0 Reference Design, XS1-L1 Edition (hereafter "the board") is a
hardware reference design for a USB audio interface using the XMOS XS1-L1 event-
driven processor. It contains a single XS1-L1 device enabling implementation of a
complete USB 2.0 high-speed device compliant with release 2.0 of the audio USB
device class.
A block diagram of the design is shown below:
XMOS
XS1-L1-128
XSYS
Debug
24 bit 192kHz
Stereo Audio
CODEC
CS4270
USB
Transciever
USB3318
13MHz
Oscillator
1Mbit
FLASH
USB
Series B
Receptacle
3.3V LDO
1.8V LDO
1.0V DC-DC
4.3V LDO
User
LEDs
Push-Button
Switches Audio Master
Clock Oscillator
Produces
24.576MHz
or
11.2896MHz
Passive
LPF
Passive
LPF
3.5mm
Stereo
TRS Jack
3.5mm
Stereo
TRS Jack
Optical
Digital Audio
Transmitter
USB
High Speed
480Mb/s ULPI
+5V VBus
CODEC
Analogue
Supply
L1 Core
Supply
+3V3D
I2S
Analog Out
1Vrms at
Full Scale
Analog In
2Vrms for
Full Scale
SPIJTA G
Resync
MCLK
S/PDIF
The XS1-L1 event-driven processor communicates with the USB host via a ULPI USB
transceiver at the 480Mb/s high-speed rate. The XS1-L1 controls the streaming of
audio data over the USB connection and direct I
2
S interface to the audio CODEC. Multi-
ple additional functions (e.g. Mixers/DSP etc.) can be implemented by modifications
to the standard software.
Some key features of the board are listed below:
•USB bus-powered. No external power supply required
•Streams bit perfect audio data up to 24-bit @ 192kHz
•Supports standard sample rates - 44.1kHz, 48kHz, 88.2kHz, 96kHz, 192kHz
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 3/18
•
USB endpoints use the asynchronous synchronisation mode to allow an external
low jitter audio master clock to be used
•Optical digital audio output (S/PDIF)
•Stereo line level audio input and output
•
XMOS XSYS debug header for easy programming/debug from the host using the
XMOS XTAG2 debug adapter
•Two push-button switches and two LEDs for programmable use
The diagram below shows the layout of the main components on the board:
H
B
M
N
B
J
L
I
I
KC
F
E
E
D
H
G
A
AXS1-L1 Device HPush-Button Switch
BUSB Connector/Transceiver IGreen User LED
CAudio CODEC JUSB Power LED
DOptical digital output KAudio Clocking
E3.5mm Stereo Jack L1V0 Core Supply
FSPI FLASH M4V3 Analogue Supply
GXSYS Debug Interface N13MHz Oscillator
The rest of this document provides a detailed description of each of the main circuit
components.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 4/18
2 XS1-L1 Device [A]
The board is based on a single XS1-L1 device in a 128 pin TQFP package.
The XS1-L1 consists of a single XCore, which comprises an event-driven multi-
threaded processor with tightly integrated general purpose I/O pins and 64 KBytes
of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
The processor has time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports is provided in
Programming XC on XMOS Devices.
2.1 Clocking
A discrete 13MHz oscillator is used to feed the XS1-L1 reference clock input and
also the USB3318 USB transceiver. The L1 has the MODE1 and MODE0 pins wired
to ground which sets the internal XS1-L1 PLL multiplication factor to 30.75. This
results in a core clock frequency of 399.75MHz and an I/O reference clock frequency
of 99.9375MHz.
2.2 Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide a
reset to the L1. This ensures the device will be reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset over
the XSYS debug interface.
2.3 Boot
The boot mode of the device is set by the MODE3 and MODE2 pins which are
connected together on the board. With MODE3 and MODE2 both high (default), the
device will boot from the 1Mb SPI FLASH on the board. With MODE3 and MODE2 both
low, the device will not boot from SPI FLASH allowing boot instead via JTAG over the
XSYS debug link.
Without anything connected to the XSYS interface, the board will boot from SPI FLASH.
With the XTAG2 connected to the XSYS interface, the host can control the boot mode
of the device by way of the TRST_N line.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 5/18
3 USB Connector and Transceiver [B]
The board uses a standard USB series B receptacle as its USB connector. The
high-speed USB signals are connected to an SMSC
®
USB3318 USB transceiver which
provides a ULPI connection to the XS1-L1.
On power-up, a pulldown resistor holds the transceiver in reset until the XS1-L1 is
ready to begin accepting USB traffic. The USB transceiver reset pin is connected to
bit zero of port 32A so this can be controlled by software.
The transceiver uses the 13MHz clock provided by a discrete oscillator on the board
which doubles as the reference clock for the XS1-L1.
The I/O pins for the USB transceiver are mapped to ports on the XS1-L processor as
described in the port map shown later in this document.
4 Audio CODEC [C]
The board uses a 24 bit, 192kHz stereo audio CODEC (Cirrus Logic® CS4270).
The CODEC is configured to operate in stand-alone mode meaning that no serial
configuration interface is required. The digital audio interface is set to I
2
S mode with
all clocks being inputs (slave mode).
The CODEC has three internal modes depending on the sampling rate used. These
change the oversampling ratio used internally in the CODEC. The three modes are
shown below:
CODEC mode CODEC sample rate range
Single speed 4-54kHz
Double speed 50-108kHz
Quad speed 100-216kHz
In stand-alone mode, the CODEC automatically determines which mode to operate in
based on the input clock rates.
The internal master clock dividers are set using the MDIV pins. MDIV1 is tied low
and MDIV2 is controlled by the L1 on bit 2 of port 32A.
With MDIV2 low, the master clock must be 256Fs in single speed mode, 128Fs in
double speed mode and 64Fs in quad speed mode. This allows an 11.2896MHz
master clock to be used for sample rates of 44.1, 88.2 and 176.4kHz.
With MDIV2 high, the master clock must be 512Fs in single speed mode, 256Fs
in double speed mode and 128Fs in quad speed mode. This allows a 24.576MHz
master clock to be used for sample rates of 48, 96 and 192kHz.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 6/18
These master clock frequencies were chosen due to the easy availability of crystals
at these frequencies.
The reset pin on the CODEC is mapped to bit 1 of port 32A on the processor.
4.1 Audio IO
Two 3.5mm Tip Ring Sleeve (TRS) audio jacks are provided for stereo audio input
and output. The layout of the audio jacks is displayed below:
OUT
IN
A simple passive ac-coupling and low pass filter circuit is used on input and output.
The circuit is configured so that the audio output will produce approximately 1V
RMS
(0dBV) for a digital full scale signal. Due to the output coupling capacitors, the
output impedance falls with frequency and is approximately 1k
Ω
@ 35Hz falling to
576Ω@ 1kHz.
The input circuit contains an attenuator such that a 2V
RMS
(+6dBV) signal will produce
a full scale digital output. The input impedance is approximately 8kΩ.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 7/18
5 Optical digital output [D]
An optical digital audio transmitter is used to provide a digital audio output in
IEC60958 consumer mode (S/PDIF) format. The S/PDIF signal is generated from a
1-bit port on the processor as defined in the port map. The data stream from the L1
is reclocked using the external master clock to synchronise the data into the audio
clock domain. This is achieved using a simple external D-type flip-flop.
6 SPI Flash Memory [F]
The board contains a 1Mbit FLASH memory device which is connected via a standard
Serial Peripheral Interface (SPI).
The FLASH is connected to four 1-bit ports as shown in the port map. These are the
standard ports the processor will try to boot from in boot from SPI mode.
Three of these ports are shared with I
2
S digital audio signals therefore the FLASH
cannot be accessed at the same time as digital audio is playing. When accessing the
SPI FLASH, the CODEC is held in reset and it ignores the three inputs shared with SPI
signals. When digital audio is playing, the FLASH is deselected by holding its chip
select (slave select) line inactive. In this mode, the FLASH will ignore other input
signals and set its output high impedance therefore it does not affect the shared
signals. The slave select signal is only active when booting the device therefore and
is held inactive while audio is playing.
The XMOS development tools include the XFLASH utility for programming compiled
programs into the flash memory. Software may also access the FLASH memory at
run-time by interfacing with the above ports. Note that, as mentioned, this can not
happen simultaneously with audio IO.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 8/18
7 XSYS Interface [G]
A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory and selection of boot mode. A 20-way
IDC header is used as the physical connector and the pinout of this is shown below:
Signal Pin Description
TRST_N 3 JTAG Test Reset. Active low.
TMS 7 JTAG Test Mode Select.
TCK 9 JTAG Test Clock.
TD1 5 JTAG Test Data. From debug adapter to XS1-L1.
TD2 13 JTAG Test Data. From XS1-L1 to debug adapter.
SRST_N 15 System Reset. Active low. Resets XS1-L1 device.
DEBUG 11 XS1-L1 DEBUG Interrupt line.
GND 4, 8, 12, 16, 20 Ground.
NC 1, 2, 6, 10, 14, 17, 18, 19 These pins are not connected.
On power on, the XS1-L1 boots from the on-board flash memory. With the XTAG2
connected, the XS1-L1 can be reset and then booted from a program on the host PC.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 9/18
8 Push-Button Switches [H]
The board provides two push-button switches whose states can be sampled at any
time by software. The layout of these switches is shown below:
A
B
The switches are connected to two 1-bit ports, the mapping of which can be seen in
the port map.
The port will go logic low when the button is pressed.
9 User LEDs [I]
The board provides two user LEDs that can be driven by software. The layout of
these LEDs is shown below:
B
A
The LEDs are connected to two bits of port 32A as shown in the port map. Setting
the relevant bit high will turn the LED on.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 10/18
10 Power
The board is a high-power bus-powered USB device. This means all the power used
by the board is derived from the nominally +5V VBus supply from the USB connector
and that the device will use more than 100mA from the VBus line when configured.
The board will use approximately 150mA when fully configured and operating.
Simple Low drop out (LDO) linear regulators are used to generate the global 3.3V
supply and the 1.8V supply required by the USB3318 USB transceiver.
A low noise LDO regulator is used to generate the analogue supply for the Audio
CODEC. The CODEC offers higher audio performance at higher supply voltages so the
voltage for this supply is set at 4.3V. This allows some headroom between the 4.5V
minimum VBus voltage and the approx 100mV dropout of the LDO + RC pre-filter.
A low cost buck switching regulator is used to generate the 1.0V core supply for
the XS1-L1. A ferrite bead is used on the +5V VBus input to prevent switching noise
propagating down the USB cable.
When the board is correctly connected to a USB source the USB Power LED is illumi-
nated.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 11/18
11 Audio Clocking [K]
The audio USB endpoints are configured in asynchronous mode. This means that the
board acts as the audio clock master and the host as the slave. This has the benefit
that a simple crystal oscillator can be used to generate the audio master clock which
typically results in lower jitter and consequently higher quality audio.
Two crystal oscillators are used on the board to support the two standard sample rate
base frequencies (44.1 and 48kHz). The crystal oscillators are built using discrete
components for low cost and easy availability however standard canned oscillators
could also be used. The oscillator design is a simple Pierce oscillator using an
unbuffered inverter as the amplifying component. The MCLK_SEL signal selects which
of the two oscillators is enabled, only one is enabled at any one time to avoid any
interference from the unused clock.
The behaviour of this select signal is shown below:
MCLK_SEL Audio master clock frequency
0 11.2896MHz
1 24.576MHz
The audio master clock is connected to a 1-bit port of the XS1-L1 so that all of the I
2
S
outputs are synchronised with it. This also allows the S/PDIF output to be generated
from a buffered 1-bit port clocked by the audio master clock input.
The MCLK_SEL signal is mapped to bit 2 of port 32A on the processor as shown in
the port map.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 12/18
12 Test Points
The board provides 18 through-hole test points as defined in the table below:
Test Point Port Signal
1 P1I0 CODEC_ADC_DATA
2 P1D0 SPI_MOSI / CODEC_DAC_DATA
3 P1A0 SPI_MISO / CODEC_SCLK
4 P1C0 SPI_CLK / CODEC_LRCK
5 NA CODEC_MCLK
6 P32A2 MCLK_SEL
7 P32A1 CODEC_RST_N
8 NA GND
9 P1L0 SPDIF_TX
10 NA SPDIF_OUT
11 P32A6 XD55
12 P32A7 XD56
13 P32A8 XD57
14 P32A9 XD58
15 P32A10 XD61
16 NA 3V3
17 NA 5V
18 NA 4V3A
13 Printed Circuit Board
The PCB is a two layer design in a credit card form factor with dimensions of 86 x
54mm. The mounting holes are 3.2mm in diameter.
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 13/18
14 Port Map
The table below provides a full description of the port to signal mappings used on
the board.
Pin Port Processor
1b 4b 8b 32b
XD0 P1A0 SPI_MISO / CODEC_SCLK
XD1 P1B0 SPI_SS
XD10 P1C0 SPI_CLK / CODEC_LRCK
XD11 P1D0 SPI_MOSI / CODEC_DAC_DATA
XD12 P1E0 ULPI_STP
XD13 P1F0 ULPI_NXT
XD14 P4C0 P8B0
ULPI_DATA[0:7]
XD15 P4C1 P8B1
XD16 P4D0 P8B2
XD17 P4D1 P8B3
XD18 P4D2 P8B4
XD19 P4D3 P8B5
XD20 P4C2 P8B6
XD21 P4C3 P8B7
XD22 P1G0 ULPI_DIR
XD23 P1H0 ULPI_CLK
XD24 P1I0 CODEC_ADC_DATA
XD25 P1J0 SWITCH_A
XD34 P1K0 SWITCH_B
XD35 P1L0 SPDIF_TX
XD36 P1M0 MCLK_IN
XD49 P32A0 USB_PHY_RST_N
XD50 P32A1 CODEC_RST_N
XD51 P32A2 MCLK_SEL
XD52 P32A3 LED_A
XD53 P32A4 LED_B
XD55 P32A6 TESTPOINT
XD56 P32A7 TESTPOINT
XD57 P32A8 TESTPOINT
XD58 P32A9 TESTPOINT
XD61 P32A10 TESTPOINT
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 14/18
15 Schematics
A
XC-6 USB AUDIO
SEPT 14 2009
TOP_LEVEL
11
A3
SHEET NAME
PROJECT NAME
REV
DATE
SIZE
OFSHEET
Copyright (c) 2009 XMOS Ltd.
PTH_M3
MTH1
MTH2
PTH_M3
PTH_M3
MTH3
MTH4
PTH_M3
FM1
FM2
FM3
L1_128_USB
X0D55
X0D54
X0D53
X0D52
X0D51
X0D50
X0D36
X0D35
X0D25
X0D34
X0D24
X0D11
X0D10
X0D0
CLK
X0D63
X0D62
X0D61
X0D58
X0D57
X0D56
X0D66
X0D65
X0D64
1 BIT
PORTS
32 BIT
PORT
TOTX147PL
J2
3
2
1GND
VCC
IN
KSC421J
SWA
1B 2B
2A1A
10K
R3
+3V3
R4
10K
+3V3
KSC421J
SWB
1B 2B
2A1A
TP1
TP2
TP3
TP4
CLOCK_GEN
CLK_13M
MCLK_SEL
MCLK
MCLK_BUF1
MCLK_BUF2
CODEC
SDOUT
MDIV2
RST_N
SDIN
SCLK
LRCK
MCLK
NC7SZ175
U1
2
4
56
1
3D
CP
C_N VCC
Q
GND
D Q
C
+3V3+3V3
+3V3
C1
100N
TP5
TP6
LEDB
GREEN
+3V3
R1
1K
100N
C2
+3V3
33RR5
TP7
TP8
TP9
TP10
TP11
1K
R2
GREEN
LEDA
TP12
TP13
TP14
TP15
TP16
+3V3
TP17
+5V
+4V3A
TP18
SWITCHB
SWITCHB
NC
NC
NC
NC
NC NC
NCNC
SWITCHA
SWITCHA
SPDIF_OUT
SPDIF_MCLK
SPDIF_MCLK
DAC_DATADAC_DATA
CLK_13M
SCLKSCLK LRCKLRCK
CODEC_RST_NCODEC_RST_N
SPDIF_TX
SPDIF_TX
ADC_DATAADC_DATA
MCLK_SELMCLK_SEL
MCLK_SEL
MCLK_SEL
CODEC_MCLKCODEC_MCLK
CODEC_MCLK
XCORE_MCLK
XCORE_MCLK
LEDA
LEDA
LEDB
LEDB
X0D66
X0D65
X0D64
X0D63
X0D62
X0D61
X0D58
X0D57
NC
X0D55
X0D56
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 15/18
A
XC-6 USB AUDIO
SEPT 14 2009 1 1
L1_128_USB
SHEET NAME
PROJECT NAME
REV
DATE
SIZE
OFSHEET
A2
Copyright (c) 2009 XMOS Ltd.
XS1_L1_128TQFP
U3
18
56
58
63
62
61
21
55
53
52
51
42
25CLK
DEBUG
MODE0
MODE1
MODE2
MODE3
RST_N
TCK
TDI
TDO
TMS
TRST_N
RESERVED
CONFIG
+1V0
C7
1N
NCP303LSN09
U8
4
2
3
1
5CD
RST_OUT
GND
INPUT
NC
47K
R8
X0D50
X0D51
X0D52
X0D53
GREEN
D3
X0D54
X0D55
1K
R11
100N
C9
C10
100N
C11
100N 100N
C12C13
100N
C14
100N
100N
C15 C16
100N
C17
100N 100N
C18
100N
C19
+3V3
+1V0
C20
100N
XS1_L1_128TQFP
U3
24
46
45
22
19
20
23
108
101
123
120
93
79
73
64
103
111
116
99
92
91
88
80
78
71
66
65
60
57
54
43
41
40
39
17
129
32
26
15
1
44
50
77
74
68
59
49
29
12
83
48
47
PLL_AGND
PLL_AVDD
VDD_83
VDD_12
VDD_29
VDD_49
VDD_59
VDD_68
VDD_74
VDD_77
VDDIO_50
VDDIO_44
VDDIO_1
VDDIO_15
VDDIO_26
VDDIO_32
GND_PAD
GND_17
GND_39
GND_40
GND_41
GND_43
GND_54
GND_57
GND_60
GND_65
GND_66
GND_71
GND_78
GND_80
GND_88
GND_91
GND_92
GND_99
GND_116
VDDIO_111
VDDIO_103
VDDIO_64
VDDIO_73
VDDIO_79
VDDIO_93
VDDIO_120
VDD_123
VDD_101
VDD_108
PCU_GATE
PCU_WAKE
PCU_VDD
PCU_VDDIO
OTP_VDDIO
OTP_VPP
PCU_CLK
POWER
4R7
R18
+1V0
1U
C3
+3V3
+1V0
+3V3+1V0
+3V3
XS1_L1_128TQFP
U3
67
112
114
117
119
121
122
124
125
127
3
38
35
33
31
13
11
9
8
6
4
95
97
98
100
75
76
81
82
69
70
72
102
104
105
109
84
85
86
87
89
94
90
96
106
107
110
113
115
118
126
128
2
5
7
10
14
16
27
28
30
34
36
37
X0D0
X0D1
X0D2
X0D3
X0D4
X0D5
X0D6
X0D7
X0D8
X0D9
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
X0D34
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
X0D49
X0D50
X0D51
X0D52
X0D53
X0D54
X0D55
X0D56
X0D57
X0D58
X0D61
X0D62
X0D63
X0D64
X0D65
X0D66
X0D67
X0D68
X0D69
X0D70
X0D35
IO
HEADER_RA
J4
20
18
19
17
1
16
14
1211
13
15
3
5
7
9
2
4
6
8
10
+3V3
+5V
CLK
X0D0
X0D10
X0D11
X0D24
X0D34
1MBIT
AT25FS010
U4
1
62
5
4
8
3
7HOLD_N
WP_N
VCC
GND
SI
SO
SCK
CS_N
+3V3
+3V3
R12
10K
+3V3
+3V3
100N
C21
+5V
R9
47K
+3V3
X0D66
X0D65
X0D64
X0D63
X0D62
X0D61
X0D58
X0D57
X0D56
4U7
C4
+5V
2U2
C26
+3V3
NCP699SN33
U6
4
51
3
2GND
EN
VIN VOUT
NC
10K
R13
U7
NCP1521B
4
51
3
2GND
EN
VIN LX
FB
6K8
R7
330P
C6
L1
2U2 C8
10U
+1V0
100N
C22
X0D25
X0D35
X0D36
100N
C23
+3V3
U2
USB3318
19
8
9
10
11
13
14
15
17
21
121
7
22
23
16
20
18
4
2
3
5
6
25
24
RBIAS
GND
DP
DM
VBAT
VBUS
VDD33
NXT
STP
DATA0
REFCLK
RESETB
CPEN
ID CLKOUT
VDD18
VDDIO DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DIR
DNP
R17
10N
C5
8K06
R6
+1V8 +3V3
C24
100N
USB_B
J3
6
4
5
2
1
3
DP
VBUS
DM
S1
GND
S2
100N
C25
NCP699SN18
U5
4
51
3
2GND
EN
VIN VOUT
NC 2U2
C27
10K
R14
+1V8+5V
1700mA
330R
FB1
+5V
1K
R10
TRST_N
TRST_N
TD2
TD2
TD1
TD1
TMS
TMS
TCK
TCK
NC
PHY_RST_N
PHY_RST_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ULPI_DATA0
ULPI_DATA0
ULPI_DIR
ULPI_DIR
NC NC
ULPI_DATA7
ULPI_DATA7
ULPI_DATA6
ULPI_DATA6
ULPI_DATA5
ULPI_DATA5
ULPI_DATA4
ULPI_DATA4
ULPI_DATA3
ULPI_DATA3
ULPI_DATA2
ULPI_DATA2
ULPI_DATA1
ULPI_DATA1
NC
X0D1
X0D1
NC
NC
NC
USB_DM
USB_DP
ULPI_NXT
ULPI_NXT
ULPI_STP
ULPI_STP
ULPI_CLK
ULPI_CLK
X0D0
X0D0
X0D10
X0D10
X0D11
X0D11
NC
NC
CLK
CLK
CLK
SRST_N
SRST_N
SRST_N
DEBUG
DEBUG
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
XSYS2
SPI FLASH
USB_VBUS
USB PHY
ALL MODE PINS HAVE INTERNAL PULLUPS
MODE[3:2] = 11 ==> BOOT FROM SPI
MODE[1:0] = 00 ==> PLL_MULT = 30.75 ==> 13MHZ REFCLK
MODE[3:2] = 00 ==> BOOT FROM JTAG (DON'T BOOT)
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 16/18
XC-6 USB AUDIO
SEPT 14 2009
CLOCK_GEN
11
AA3
SHEET NAME
PROJECT NAME
REV
DATE
SIZE
OFSHEET
Copyright (c) 2009 XMOS Ltd.
+3V3
NC7WZU04
U10
3 4
NC7WZU04
U10
2
5
1 6
C30
100N100N
C31
+3V3
+3V3
MCLK
Q1
BSS138
2
1
3D
G
S
R23
10K
33P
C32
R19
2M2
R28
470R
C33
33P
Q2
BSS138
2
1
3D
G
S
R24
10K
C34
33P
2M2
R20
X2
24M576
HC49US
33P
C35
BSS138
Q3
2
1
3D
G
S
10K
R25
11M2896
HC49US
X3
1K
R22
+3V3
MCLK_SEL
NC7SZ157
U11
2
4
56
1
3I0
I1
S VCC
Q
GND
0
1
U9
NC7SZU04
3
5
2 4
+3V3
13M
ABLS2
X1
2M2
R21
470R
R29
C36
33P
C37
33P
CLK_13M
1700mA
330R
FB2
MECH1
CRYSTAL_INSULATOR
R26 33R
NC7WZ17
U12
1
4
6
2
5
3A2
VCC
GND
Y1
Y2
A1
+3V3
33R
R27 MCLK_BUF1
MCLK_BUF2
C29
100N
1U
C28
CRYSTAL_INSULATOR
MECH2
24M576
24M576
11M2896
11M2896
CLK_13M
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 17/18
A
XC-6 USB AUDIO
SEPT 14 2009
CODEC
11
A3
SHEET NAME
PROJECT NAME
REV
DATE
SIZE
OFSHEET
Copyright (c) 2009 XMOS Ltd.
C54
100N
C43
10U
+4V3A
100N
C55
+3V3
SDOUT
MDIV2
RST_N
SDIN
SCLK
LRCK
+3V3
10K
R37
C41
10U
10K
R35
2N2
C49
R36
10K
C50
2N2
R42
470R
10U
C42
C44
10U
R39
4K7
R32
3K3
C46
220P
3K3
R33
4K7
R40
470R
R41
220P
C45
10U
C39
10U
C40C51
100N 100N
C52
47U
C48
+3V3
47K
R34
+4V3A
1R
R30
CS4270U13
7
9
10
11
14
16
15
19
18
21
24
8
5
22
23
17
20
6
12
3
1
13
4
2LRCK
SCLK
MDIV2
SDIN
MCLK
MDIV1
DGND
AGND
VQ
AOUTB
AOUTA
VD
VLC
MUTEB_N
MUTEA_N
FILTP
VA
AINA
AINB
RST_N
I2S/LJ_N
M0
M1
SDOUT
MCLK
100P
C47
6K8
R31
2K7
R38
100N
C53
+4V3A
TPS73001
U14
5
2 4
1 6
3EN
OUTIN
NRGND
FB
2U2
C56
4U7
C38
+5V
SJ-3523-SMT
J5
3
2
1
J6
SJ-3523-SMT
3
2
1
NC
NC
MDIV PINS SELECT CLOCK RATIOS. SEE PAGE 23 OF DATASHEET.
I2S/LJ_N PULLED HIGH : I2S INTERFACE FORMAT.
M1 = 0 : NOT USED IN STAND ALONE SLAVE MODE
M0 = 0 : DE-EMPHASIS OFF
SDOUT PULLED LOW BY 47K - SLAVE MODE
CODEC DEFAULTS TO STAND ALONE MODE
4V3A LDO REGULATOR
VOUT = 1.225 * (1 + 6K8/2K7) = 4.31V
VREF = 1.225V
www.xmos.com
USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 18/18
16 Related Documents
The following documents provide more information on designing with the USB Audio
2.0 Reference Design, XS1-L1 Edition:
•
Programming XC on XMOS Devices: explains how to program XMOS event-driven
processor devices using the XC language.
•
XCore XS1 Architecture Tutorial: provides an overview of the XS1 instruction
set architecture.
•XS1 XSystem-L: provides an introduction on how to boot the XS1-L devices.
•
XMOS Tools User Guide: explains how to use the XMOS Tools to program XMOS
event-driven processor devices.
The most up-to-date information on the board, including schematics and product
datasheets, is available from:
•http://www.xmos.com/usbaudio2/
Disclaimer
XMOS Ltd. is the owner or licensee of this design, code, or Information (collectively,
the “Information”) and is providing it to you “AS IS” with no warranty of any kind,
express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the Information, or any particular implementation thereof, is
or will be free from any claims of infringement and again, shall have no liability in
relation to any such claims.
www.xmos.com
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XMOS XS1-L1 is a hardware reference design for a USB audio interface using the XMOS XS1-L1 event-driven processor. The XS1-L1 can implement a complete USB 2.0 high-speed device compliant with release 2.0 of the audio USB device class. Here is a brief overview of its capabilities:
-
Audio capabilities:
- Streams bit-perfect audio data up to 24-bit @ 192kHz
- Supports standard sample rates: 44.1kHz, 48kHz, 88.2kHz, 96kHz, 192kHz
- Optical S/PDIF digital audio output
- Stereo line-level audio input and output
-
Other features:
- USB bus-powered, no external power supply required
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