MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 1
Preliminary—Subject to Change Without Notice
MPC563XM Microcontroller
Reference Manual
Devices Supported:
MPC5634M
MPC5633M
MPC5632M
MPC563XRM
Rev. 1
25 Jul 2008
MPC563XM Reference Manual, Rev. 1
2 Freescale Semiconductor
Preliminary—Subject to Change Without Notice
MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 3
Preliminary—Subject to Change Without Notice
Chapter 1
Introduction
1.1 The MPC563XM Microcontroller Family ......................................................................................23
1.2 MPC563XM Device Summary .......................................................................................................23
1.3 MPC563XM Blocks ........................................................................................................................24
1.3.1 Block Diagram ..................................................................................................................24
1.3.2 Block Summary ................................................................................................................25
1.4 MPC563XM Features .....................................................................................................................26
1.4.1 Feature List .......................................................................................................................26
1.4.2 e200z335 Core ..................................................................................................................35
1.4.3 Crossbar ............................................................................................................................37
1.4.4 eDMA ...............................................................................................................................37
1.4.5 Interrupt Controller ...........................................................................................................38
1.4.6 FMPLL ..............................................................................................................................39
1.4.7 Calibration EBI .................................................................................................................40
1.4.8 SIU ....................................................................................................................................41
1.4.9 ECSM ................................................................................................................................41
1.4.10 Flash ..................................................................................................................................42
1.4.11 SRAM ...............................................................................................................................43
1.4.12 BAM .................................................................................................................................43
1.4.13 eMIOS ...............................................................................................................................43
1.4.14 eTPU .................................................................................................................................44
1.4.15 eQADC .............................................................................................................................46
1.4.16 DSPI ..................................................................................................................................48
1.4.17 eSCI ..................................................................................................................................50
1.4.18 FlexCAN ...........................................................................................................................51
1.4.19 System Timers ...................................................................................................................52
1.4.20 Software Watchdog Timer (SWT) ....................................................................................53
1.4.21 Nexus Port Controller .......................................................................................................53
1.4.22 JTAG .................................................................................................................................55
Chapter 2
Memory Map
2.1 Introduction .....................................................................................................................................57
2.2 Memory Map ...................................................................................................................................57
Chapter 3
Signal Descriptions
3.1 Device Pin Assignments ..................................................................................................................63
3.1.1 144 LQFP ..........................................................................................................................63
3.1.2 Ballmap: 208 MAPBGA ...................................................................................................65
3.2 External Signal Summary ................................................................................................................66
3.3 Detailed Signal Descriptions ...........................................................................................................76
3.3.1 Reset / Configuration ........................................................................................................76
3.3.2 Calibration External Bus Interface (EBI) .........................................................................76
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3.3.3 Nexus Port Controller (NPC) ............................................................................................78
3.3.4 JTAG .................................................................................................................................79
3.3.5 FlexCAN ...........................................................................................................................80
3.3.6 eSCI ..................................................................................................................................80
3.3.7 DSPI ..................................................................................................................................81
3.3.8 eQADC .............................................................................................................................82
3.3.9 eTPU .................................................................................................................................85
3.3.10 eMIOS ...............................................................................................................................88
3.3.11 Clock Synthesizer .............................................................................................................89
3.3.12 Power / Ground .................................................................................................................90
Chapter 4
Resets
4.1 Reset Sources ..................................................................................................................................93
4.2 Reset Vector .....................................................................................................................................94
4.3 Reset Pins ........................................................................................................................................94
4.3.1 RESET ..............................................................................................................................94
4.3.2 RSTOUT ...........................................................................................................................94
4.4 Clock Quality Monitor Gating Signal .............................................................................................95
4.5 Reset Source Descriptions ...............................................................................................................95
4.5.1 Power-on Reset .................................................................................................................98
4.5.2 External Reset ...................................................................................................................98
4.5.3 Loss of Lock .....................................................................................................................98
4.5.4 Loss of Clock ....................................................................................................................99
4.5.5 Watchdog Timer/Debug Reset ..........................................................................................99
4.5.6 Software Watchdog Timer Reset ......................................................................................99
4.5.7 Checkstop Reset ..............................................................................................................100
4.5.8 JTAG Reset .....................................................................................................................100
4.5.9 Software System Reset ...................................................................................................100
4.5.10 Software External Reset ..................................................................................................101
4.6 Reset Registers in the SIU .............................................................................................................101
4.7 Reset Configuration .......................................................................................................................101
4.7.1 Reset Configuration Half Word (RCHW) .......................................................................101
4.7.2 Reset Configuration Timing ............................................................................................103
4.7.3 Reset Weak Pull Up/Down Configuration ......................................................................104
Chapter 5
Operating Modes
5.1 Overview .......................................................................................................................................105
5.2 Modes of Operation .......................................................................................................................105
5.2.1 Normal Mode ..................................................................................................................105
5.2.2 Debug Mode ...................................................................................................................105
5.2.3 Low Power Modes ..........................................................................................................105
5.3 Modes and Clock Architecture ......................................................................................................106
5.3.1 Block Diagrams ..............................................................................................................106
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5.3.2 Clock Architecture ..........................................................................................................110
Chapter 6
e200z335 (Z335) Core
6.1 Introduction ...................................................................................................................................115
6.2 Features .........................................................................................................................................115
6.3 Location of Detailed Documentation ............................................................................................116
Chapter 7
Direct Memory Access (DMA)
7.1 Information Specific to This Device .............................................................................................117
7.1.1 Device-Specific Features ................................................................................................117
7.1.2 Channel Assignments .....................................................................................................117
7.2 Introduction ...................................................................................................................................118
7.2.1 Overview .........................................................................................................................119
7.2.2 Features ...........................................................................................................................120
7.3 Memory Map/Register Definition .................................................................................................125
7.3.1 Register Descriptions ......................................................................................................127
7.4 Functional Description ..................................................................................................................151
7.4.1 DMA Microarchitecture .................................................................................................151
7.4.2 DMA Basic Data Flow ...................................................................................................152
7.4.3 DMA Performance ..........................................................................................................155
7.5 Initialization/Application Information ..........................................................................................158
7.5.1 DMA Initialization ..........................................................................................................158
7.5.2 DMA Programming Errors .............................................................................................159
7.5.3 DMA Arbitration Mode Considerations .........................................................................160
7.5.4 DMA Transfer .................................................................................................................161
7.5.5 TCD Status ......................................................................................................................164
7.5.6 Channel Linking .............................................................................................................165
7.5.7 Dynamic Programming ...................................................................................................166
7.5.8 Hardware Request Release Timing .................................................................................167
Chapter 8
Multi-Layer AHB Crossbar Switch (XBAR)
8.1 Information Specific to This Device .............................................................................................169
8.1.1 Device-Specific Block Diagram .....................................................................................169
8.1.2 Device-Specific Features ................................................................................................169
8.1.3 Device-Specific Register Information ............................................................................170
8.2 Introduction ...................................................................................................................................171
8.2.1 Overview .........................................................................................................................171
8.2.2 Features ...........................................................................................................................173
8.2.3 Limitations ......................................................................................................................173
8.2.4 General Operation ...........................................................................................................173
8.3 XBAR Registers ............................................................................................................................174
8.3.1 Register Summary ...........................................................................................................174
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8.3.2 XBAR Register Descriptions ..........................................................................................177
8.3.3 Coherency .......................................................................................................................185
8.4 Function .........................................................................................................................................185
8.4.1 Arbitration .......................................................................................................................185
8.4.2 Priority Assignment ........................................................................................................187
8.4.3 Master Port Functionality ...............................................................................................188
8.4.4 Slave Port Functionality ..................................................................................................191
8.5 Initialization/Application Information ..........................................................................................198
8.6 Interface .........................................................................................................................................198
8.6.1 Overview .........................................................................................................................199
8.6.2 Master Ports ....................................................................................................................199
8.6.3 Slave Ports ......................................................................................................................200
Chapter 9
Peripheral Bridge (PBRIDGE)
9.1 PBRIDGE Features .......................................................................................................................201
9.2 PBRIDGE Modes of Operation .....................................................................................................201
9.3 PBRIDGE Block Diagram ............................................................................................................201
9.4 PBRIDGE Signal Description .......................................................................................................201
9.5 PBRIDGE Functional Description ................................................................................................202
9.5.1 Read Cycles ....................................................................................................................202
9.5.2 Write Cycles ....................................................................................................................202
9.6 PBRIDGE Registers ......................................................................................................................202
Chapter 10
Flash Memory (C90FL)
10.1 Introduction ...................................................................................................................................203
10.2 Platform Flash (PFlash) Memory Controller ................................................................................203
10.2.1 Controller Overview .......................................................................................................203
10.2.2 Features ...........................................................................................................................203
10.2.3 Modes of Operation ........................................................................................................204
10.2.4 Block Diagram ................................................................................................................204
10.2.5 Signal Description ...........................................................................................................204
10.2.6 Functional Description ....................................................................................................204
10.2.7 Memory Map and Register Definition ............................................................................208
10.2.8 C90FL Register Descriptions ..........................................................................................209
10.3 Flash Memory Block (C90FL) ......................................................................................................214
10.3.1 C90FL Block Overview ..................................................................................................214
10.3.2 C90FL Block Features ....................................................................................................215
10.3.3 C90FL Modes of Operation ............................................................................................216
10.3.4 C90FL Block Diagram ....................................................................................................216
10.3.5 C90FL Flash EEPROM Functional Description ............................................................217
10.3.6 C90FL Memory Map and Register Definition ...............................................................219
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Chapter 11
Flash Memory (LC)
11.1 Introduction ...................................................................................................................................243
11.2 Block Diagram ..............................................................................................................................243
11.3 Overview .......................................................................................................................................243
11.4 Features .........................................................................................................................................244
11.4.1 FBIU features ..................................................................................................................244
11.4.2 Flash memory array features ...........................................................................................244
11.5 Modes of Operation .......................................................................................................................245
11.5.1 User Mode .......................................................................................................................245
11.5.2 Stop Mode .......................................................................................................................245
11.6 Memory Map/Register Description ...............................................................................................245
11.6.1 Flash Memory Map .........................................................................................................245
11.6.2 Register Descriptions ......................................................................................................248
11.7 Functional Description ..................................................................................................................279
11.7.1 Basic Interface Protocol ..................................................................................................279
11.7.2 Access Protections ..........................................................................................................280
11.7.3 Read Cycles - Buffer Miss ..............................................................................................280
11.7.4 Read Cycles - Buffer Hit .................................................................................................280
11.7.5 Write Cycles ....................................................................................................................280
11.7.6 Error Termination ............................................................................................................280
11.7.7 Access Pipelining ............................................................................................................281
11.7.8 Flash Error Response Operation .....................................................................................281
11.7.9 Bank0 Page Read Buffers and Prefetch Operation .........................................................281
11.7.10Read-While-Write Functionality .....................................................................................283
11.7.11Wait-State Emulation ......................................................................................................284
11.7.12Flash Memory Array: User Mode ...................................................................................285
Chapter 12
General-Purpose Static RAM (SRAM)
12.1 Overview .......................................................................................................................................299
12.2 Features .........................................................................................................................................299
12.3 Modes of Operation .......................................................................................................................299
12.3.1 Normal (Functional) Mode .............................................................................................299
12.3.2 Standby Mode .................................................................................................................299
12.4 Block Diagram ..............................................................................................................................299
12.5 External Signal Description ..........................................................................................................300
12.6 Functional Description ..................................................................................................................300
12.6.1 Access Timing .................................................................................................................300
12.7 Module Memory Map ...................................................................................................................301
12.8 Register Descriptions ....................................................................................................................301
Chapter 13
External Bus Interface (EBI)
13.1 Information Specific to This Device .............................................................................................303
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13.1.1 Device-Specific Features ................................................................................................303
13.1.2 Unsupported Features .....................................................................................................303
13.1.3 Device-Specific Register Information ............................................................................303
13.2 Introduction ...................................................................................................................................303
13.2.1 Overview .........................................................................................................................304
13.2.2 Features ...........................................................................................................................305
13.2.3 Modes of Operation ........................................................................................................305
13.3 External Signal Description ..........................................................................................................308
13.3.1 Overview .........................................................................................................................308
13.3.2 Detailed Signal Descriptions ..........................................................................................308
13.3.3 Signal Function/Direction by Mode ...............................................................................313
13.3.4 Signal Pad Configuration by Mode ................................................................................313
13.3.5 Signal Output Buffer Enable Logic by Mode .................................................................314
13.4 Memory Map/Register Definition .................................................................................................315
13.4.1 Register Descriptions ......................................................................................................316
13.5 Functional Description ..................................................................................................................324
13.5.1 External Bus Interface Features ......................................................................................324
13.5.2 External Bus Operations .................................................................................................330
13.6 Initialization/Application Information ..........................................................................................397
13.6.1 Booting from External Memory .....................................................................................397
13.6.2 Running with SDR (Single Data Rate) Burst Memories ................................................397
13.6.3 Running with Asynchronous Memories .........................................................................398
13.6.4 Connecting an MCU to Multiple Memories ...................................................................400
13.6.5 Address Decoding Example for External Master Accesses ............................................401
13.6.6 EBI Operation with Reduced Pinout MCUs ...................................................................402
13.6.7 Address/Data Multiplexing Connection Examples .........................................................404
13.6.8 Summary of Differences from MPC5xx .........................................................................408
Chapter 14
Interrupt Controller (INTC)
14.1 Information Specific to This Device .............................................................................................411
14.1.1 Device-Specific Features ................................................................................................411
14.1.2 Device-Specific Register Information ............................................................................411
14.2 Introduction ...................................................................................................................................411
14.2.1 Module Overview ...........................................................................................................411
14.2.2 Block Diagram ................................................................................................................412
14.2.3 Features ...........................................................................................................................413
14.3 Modes of Operation .......................................................................................................................414
14.3.1 Normal Mode ..................................................................................................................414
14.3.2 Debug Mode ...................................................................................................................415
14.3.3 Stop Mode .......................................................................................................................415
14.3.4 Factory Test Mode ..........................................................................................................415
14.4 External Signal Description ..........................................................................................................416
14.5 Memory Map/Register Definition .................................................................................................416
14.5.1 Memory Map ..................................................................................................................416
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14.5.2 Register Information .......................................................................................................416
14.5.3 INTC Block Configuration Register (INTC_BCR) ........................................................417
14.5.4 INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0) ...........................418
14.5.5 INTC Current Priority Register for Processor 1 (INTC_CPR_PRC1) ...........................419
14.5.6 INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0) ..........420
14.5.7 INTC Interrupt Acknowledge Register for processor 1 (INTC_IACKR_PRC1) ...........421
14.5.8 INTC End of Interrupt Register for Processor 0 (INTC_EOIR_PRC0) .........................421
14.5.9 INTC End of Interrupt Register for processor 1 (INTC_EOIR_PRC1) .........................422
14.5.10INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7) .422
14.5.11INTC Priority Select Registers (INTC_PSR0_3 - INTC_PSR508_511) ........................424
14.6 Functional Description ..................................................................................................................425
14.6.1 Interrupt Request Sources ...............................................................................................425
14.6.2 Priority Management ......................................................................................................426
14.6.3 Handshaking with Processor ...........................................................................................428
14.6.4 Reserved Spaces in Memory Map ..................................................................................431
14.7 Initialization/Application Information ..........................................................................................432
14.7.1 Initialization Flow ...........................................................................................................432
14.7.2 Interrupt Exception Handler ...........................................................................................432
14.7.3 Code Compression’s Impact on Vector Table .................................................................434
14.7.4 ISR, RTOS, and Task Hierarchy .....................................................................................434
14.7.5 Order of Execution ..........................................................................................................434
14.7.6 Priority Ceiling Protocol .................................................................................................435
14.7.7 Selecting Priorities According to Request Rates and Deadlines ....................................436
14.7.8 Software Setable Interrupt Requests ...............................................................................437
14.7.9 Lowering Priority Within an ISR ....................................................................................438
14.7.10Negating an Interrupt Request Outside of its ISR ..........................................................438
14.7.11Examining LIFO contents ...............................................................................................439
Chapter 15
Interrupts
15.1 Introduction ...................................................................................................................................441
15.2 Interrupt Vectors ............................................................................................................................441
15.2.1 External Input .................................................................................................................441
15.2.2 Critical Input ...................................................................................................................443
15.3 Interrupt Summary ........................................................................................................................443
Chapter 16
System Integration Unit (SIU)
16.1 Overview .......................................................................................................................................465
16.2 Features .........................................................................................................................................465
16.3 Modes of Operation .......................................................................................................................466
16.3.1 Normal Mode ..................................................................................................................466
16.3.2 Debug Mode ...................................................................................................................466
16.4 Block Diagram ..............................................................................................................................466
16.5 Signal Description .........................................................................................................................467
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16.6 Detailed Signal Descriptions .........................................................................................................468
16.6.1 RESET — Reset Input ....................................................................................................468
16.6.2 RSTOUT — Reset Output ..............................................................................................468
16.6.3 GPIO[0:213] — General Purpose I/O Pins .....................................................................468
16.6.4 BOOTCFG1 (BOOTCFG1_IRQ[3]_ETRIG[1]_GPIO[212]) — Boot Configuration Pin ..
469
16.6.5 WKPCFG (WKPCFG_NMI_GPIO[213]) — I/O Pin Weak Pull Up Reset Configuration
Pin 469
16.6.6 IRQ[0:15] — External Interrupt Request Input Pins ......................................................469
16.7 Functional Description ..................................................................................................................469
16.7.1 System Configuration .....................................................................................................469
16.7.2 Reset Control ..................................................................................................................470
16.7.3 External Interrupt ............................................................................................................470
16.7.4 GPIO Operation ..............................................................................................................471
16.7.5 Internal Multiplexing ......................................................................................................471
16.8 Memory Map .................................................................................................................................473
16.9 Register Descriptions ....................................................................................................................475
16.9.1 MCU ID Register 2 (SIU_MIDR2) ................................................................................475
16.9.2 MCU ID Register (SIU_MIDR) .....................................................................................477
16.9.3 Reset Status Register (SIU_RSR) ...................................................................................478
16.9.4 System Reset Control Register (SIU_SRCR) .................................................................480
16.9.5 External Interrupt Status Register (SIU_EISR) ..............................................................481
16.9.6 DMA/Interrupt Request Enable Register (SIU_DIRER) ................................................482
16.9.7 DMA/Interrupt Request Select Register (SIU_DIRSR) .................................................483
16.9.8 Overrun Status Register (SIU_OSR) ..............................................................................484
16.9.9 Overrun Request Enable Register (SIU_ORER) ............................................................484
16.9.10IRQ Rising-Edge Event Enable Register (SIU_IREER) ................................................485
16.9.11External IRQ Falling-Edge Event Enable Register (SIU_IFEER) .................................485
16.9.12External IRQ Digital Filter Register (SIU_IDFR) ..........................................................486
16.9.13Pad Configuration Registers (SIU_PCR) .......................................................................487
16.9.14GPIO Pin Data Output Registers (SIU_GPDO83_86 - SIU_GPDO230_232) ...............533
16.9.15GPO Data Output Registers (SIU_GPDO350 - SIU_GPDO413) ..................................534
16.9.16GPIO Pin Data Input Registers (SIU_GPDI83_86 - SIU_GPDI_232) ..........................535
16.9.17eQADC Trigger Input Select Register (SIU_ETISR) .....................................................536
16.9.18External IRQ Input Select Register (SIU_EIISR) ..........................................................538
16.9.19DSPI Input Select Register (SIU_DISR) ........................................................................542
16.9.20MUX Select Register 3 (SIU_ISEL3) ............................................................................545
16.9.21Chip Configuration Register (SIU_CCR) .......................................................................546
16.9.22External Clock Control Register (SIU_ECCR) ..............................................................547
16.9.23Compare A High Register ...............................................................................................548
16.9.24Compare A Low Register ...............................................................................................548
16.9.25Compare B High Register ...............................................................................................549
16.9.26Compare B Low Register ...............................................................................................549
16.9.27System Clock Register (SIU_SYSDIV) .........................................................................550
16.9.28Halt Register (SIU_HLT) ................................................................................................551
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16.9.29Halt Acknowledge Register (SIU_HLTACK) ................................................................552
Chapter 17
Frequency-Modulated Phase Locked Loop (FMPLL)
17.1 Information Specific to This Device .............................................................................................555
17.1.1 Device-Specific Features ................................................................................................555
17.1.2 Device-Specific Register Field Reset Values ..................................................................555
17.2 Introduction ...................................................................................................................................555
17.2.1 Overview .........................................................................................................................555
17.2.2 Features ...........................................................................................................................556
17.2.3 Modes of Operation ........................................................................................................557
17.3 External Signal Description ..........................................................................................................558
17.3.1 Detailed Signal Descriptions ..........................................................................................558
17.4 Memory Map and Register Definition ..........................................................................................559
17.4.1 Memory Map ..................................................................................................................559
17.4.2 Register Descriptions ......................................................................................................560
17.5 Functional Description ..................................................................................................................569
17.5.1 Input Clock Frequency ....................................................................................................569
17.5.2 Clock Configuration .......................................................................................................569
17.5.3 Lock Detection ................................................................................................................570
17.5.4 Loss-of-Clock Detection .................................................................................................570
17.5.5 Frequency Modulation ....................................................................................................574
Chapter 18
Error Correction Status Module (ECSM)
18.1 Overview .......................................................................................................................................577
18.2 Features .........................................................................................................................................577
18.3 Module Memory Map ...................................................................................................................577
18.4 Register Descriptions ....................................................................................................................578
18.4.1 Platform ECC Registers ..................................................................................................578
Chapter 19
System Timer Module (STM)
19.1 Information Specific to This Device .............................................................................................591
19.1.1 Device-Specific Features ................................................................................................591
19.2 Introduction ...................................................................................................................................591
19.2.1 Overview .........................................................................................................................591
19.2.2 Features ...........................................................................................................................591
19.2.3 Modes of Operation ........................................................................................................591
19.3 External Signal Description ..........................................................................................................591
19.4 Memory Map and Register Definition ..........................................................................................592
19.4.1 Memory Map ..................................................................................................................592
19.4.2 Register Descriptions ......................................................................................................592
19.5 Functional Description ..................................................................................................................596
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Chapter 20
Software Watchdog Timer (SWT)
20.1 Information Specific to This Device .............................................................................................597
20.1.1 Device-Specific Features ................................................................................................597
20.1.2 Reset Assertion ...............................................................................................................597
20.1.3 Default Configuration .....................................................................................................597
20.2 Introduction ...................................................................................................................................598
20.2.1 Overview .........................................................................................................................598
20.2.2 Features ...........................................................................................................................598
20.2.3 Modes of Operation ........................................................................................................598
20.3 External Signal Description ..........................................................................................................598
20.4 Memory Map and Register Definition ..........................................................................................598
20.4.1 Memory Map ..................................................................................................................599
20.4.2 Register Descriptions ......................................................................................................599
20.5 Functional Description ..................................................................................................................604
Chapter 21
Boot Assist Module (BAM)
21.1 Overview .......................................................................................................................................607
21.2 Features .........................................................................................................................................607
21.3 Modes of Operation .......................................................................................................................607
21.3.1 Normal Mode ..................................................................................................................607
21.3.2 Debug Mode ...................................................................................................................607
21.3.3 Internal Boot Mode .........................................................................................................608
21.3.4 Serial Boot Mode ............................................................................................................608
21.3.5 Calibration Bus Boot Mode ............................................................................................608
21.4 Memory Map .................................................................................................................................608
21.5 Functional Description ..................................................................................................................608
21.5.1 BAM Program Flow Chart .............................................................................................608
21.5.2 BAM Program Operation ................................................................................................609
21.5.3 Reset Configuration Half Word (RCHW) .......................................................................611
21.5.4 Internal Boot Mode .........................................................................................................613
21.5.5 Serial Boot Mode ............................................................................................................614
21.5.6 Booting from the Calibration bus ...................................................................................620
Chapter 22
Configurable Enhanced Modular IO Subsystem (eMIOS200)
22.1 Information Specific to This Device .............................................................................................623
22.1.1 Device-Specific Features ................................................................................................623
22.1.2 Device-Specific Channel Information ............................................................................623
22.1.3 Device-Specific Register Information ............................................................................625
22.2 Introduction ...................................................................................................................................626
22.2.1 Overview .........................................................................................................................627
22.2.2 Features ...........................................................................................................................627
22.2.3 Modes of Operation ........................................................................................................627
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22.3 External Signal Description ..........................................................................................................628
22.3.1 Overview .........................................................................................................................628
22.3.2 Detailed Signal Descriptions ..........................................................................................628
22.4 Memory Map/Register Definition .................................................................................................629
22.4.1 Memory Map ..................................................................................................................629
22.4.2 Register Descriptions ......................................................................................................631
22.5 Functional Description ..................................................................................................................654
22.5.1 Unified Channel (UC) .....................................................................................................657
22.5.2 Wheel Speed Channel (WSC) .........................................................................................703
22.5.3 IP Bus Interface Unit (BIU) ............................................................................................710
22.5.4 Red Line Client submodule (REDC) ..............................................................................711
22.5.5 Global Clock Prescaler Submodule (GCP) .....................................................................711
22.6 Initialization/Application Information ..........................................................................................712
22.6.1 Considerations ................................................................................................................712
22.6.2 Application Information .................................................................................................712
Chapter 23
Enhanced Time Processing Unit (eTPU)
23.1 Introduction ...................................................................................................................................717
23.1.1 Overview .........................................................................................................................718
23.1.2 Features ...........................................................................................................................723
23.1.3 Modes of Operation ........................................................................................................727
23.2 External Signal Description ..........................................................................................................729
23.2.1 Overview .........................................................................................................................729
23.2.2 Detailed Signal Descriptions ..........................................................................................730
23.3 Memory Map/Register Definition .................................................................................................731
23.3.1 Memory Map ..................................................................................................................731
23.3.2 System Configuration Registers .....................................................................................735
23.3.3 Time Base Registers ........................................................................................................745
23.3.4 Engine Related Registers ................................................................................................750
23.3.5 Channel Registers Layout ...............................................................................................752
23.3.6 Global Channel Registers ...............................................................................................753
23.3.7 Channel Configuration and Control Registers ................................................................760
23.4 Functional Description ..................................................................................................................766
23.4.1 Functions and Threads ....................................................................................................766
23.4.2 Host Interface ..................................................................................................................781
23.4.3 Scheduler ........................................................................................................................787
23.4.4 Parameter Sharing and Coherency ..................................................................................794
23.4.5 Enhanced Channels .........................................................................................................798
23.4.6 Time Bases ......................................................................................................................842
23.4.7 EAC - eTPU Angle Counter ...........................................................................................849
23.4.8 Microengine ....................................................................................................................868
23.4.9 Microinstruction Set .......................................................................................................885
23.4.10Test and Development Support .......................................................................................917
23.5 Initialization/Application Information ..........................................................................................924
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23.5.1 Configuration Sequence ..................................................................................................924
23.5.2 Reset Options ..................................................................................................................925
23.5.3 Multiple Parameter Coherency Methods ........................................................................926
23.5.4 Programming Hints and Caveats ....................................................................................927
23.5.5 Estimating Worst Case Latency ......................................................................................928
23.5.6 Endianness ......................................................................................................................944
23.6 Appendices ....................................................................................................................................944
23.6.1 Microcycle and I/O Timing .............................................................................................944
23.6.2 Initialization Code Example ...........................................................................................949
23.6.3 Predefined Channel Mode Summary ..............................................................................952
23.6.4 MISC Algorithm .............................................................................................................955
Chapter 24
Enhanced Queued Analog-to-Digital Converter (EQADC)
24.1 Information Specific to This Device .............................................................................................957
24.1.1 Device-Specific Features ................................................................................................957
24.1.2 Device-Specific Pin Configuration Features ..................................................................957
24.2 Introduction ...................................................................................................................................958
24.2.1 Module Overview ...........................................................................................................958
24.2.2 Block Diagram ................................................................................................................959
24.2.3 Features ...........................................................................................................................960
24.3 Modes of Operation .......................................................................................................................962
24.3.1 Normal Mode ..................................................................................................................962
24.3.2 Streaming Mode ..............................................................................................................962
24.3.3 Debug Mode ...................................................................................................................963
24.3.4 Stop Mode .......................................................................................................................964
24.3.5 Factory Test Mode ..........................................................................................................965
24.4 External Signal Description ..........................................................................................................965
24.4.1 Overview .........................................................................................................................965
24.4.2 Detailed Signal Descriptions ..........................................................................................968
24.5 Memory Map/Register Definition .................................................................................................971
24.5.1 EQADC Memory Map ....................................................................................................971
24.5.2 EQADC Register Descriptions .......................................................................................973
24.5.3 On-Chip ADC Registers ...............................................................................................1004
24.6 Functional Description ................................................................................................................1015
24.6.1 Overview .......................................................................................................................1015
24.6.2 Data Flow in EQADC ...................................................................................................1016
24.6.3 Command/Result Queues .............................................................................................1032
24.6.4 EQADC Command FIFOs ............................................................................................1032
24.6.5 EQADC Result FIFOs ..................................................................................................1061
24.6.6 On-Chip ADC Configuration and Control ....................................................................1065
24.6.7 Internal/External Multiplexing .....................................................................................1074
24.6.8 EQADC DMA/Interrupt Request .................................................................................1080
24.6.9 EQADC Synchronous Serial Interface (SSI) Sub-Block ..............................................1083
24.6.10EQADC Parallel Side Interface (PSI) Sub-Block .........................................................1088
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24.6.11Analog Sub-Block .........................................................................................................1091
24.6.12Supported EQADC Configurations ..............................................................................1095
24.7 Initialization/Application Information ........................................................................................1097
24.7.1 Multiple Queues Control Setup Example .....................................................................1097
24.7.2 EQADC/DMAC Interface ............................................................................................1101
24.7.3 Sending Immediate Command Setup Example ............................................................1103
24.7.4 Modifying Queues ........................................................................................................1104
24.7.5 CQueue and RQueues Usage ........................................................................................1105
24.7.6 ADC Result Calibration ................................................................................................1107
24.7.7 EQADC Versus QADC .................................................................................................1109
Chapter 25
Decimation Filter
25.1 Information Specific to This Device ...........................................................................................1115
25.1.1 Device-Specific Features ..............................................................................................1115
25.2 Introduction .................................................................................................................................1115
25.2.1 Overview .......................................................................................................................1115
25.2.2 Features .........................................................................................................................1116
25.2.3 Modes of Operation ......................................................................................................1117
25.3 External Signal Description ........................................................................................................1117
25.4 Memory Map and Register Definition ........................................................................................1117
25.4.1 Decimation Filter Memory Map for SoC Integration ...................................................1117
25.4.2 Decimation Filter Registers Description .......................................................................1119
25.4.3 Decimation Filter Memory Map for Parallel Side Interface .........................................1127
25.4.4 PSI Register Description ...............................................................................................1127
25.5 Functional Description ................................................................................................................1129
25.5.1 Overview .......................................................................................................................1129
25.5.2 Parallel Side Interface (PSI) Description ......................................................................1129
25.5.3 Input Buffer Description ...............................................................................................1131
25.5.4 Output Buffer Description ............................................................................................1132
25.5.5 Bypass Configuration Description ................................................................................1133
25.5.6 IIR and FIR Filter .........................................................................................................1134
25.5.7 Filter Prefill Control Description ..................................................................................1137
25.5.8 Timestamp Data Transmission ......................................................................................1138
25.5.9 Flush Command Description ........................................................................................1138
25.5.10Soft-Reset Command Description ................................................................................1138
25.5.11Interrupt Request Description .......................................................................................1139
25.5.12Freeze Mode Description ..............................................................................................1139
25.6 Initialization Information ............................................................................................................1140
25.6.1 Initialization Procedure .................................................................................................1140
25.7 Application Information ..............................................................................................................1140
25.7.1 EQADC IP as the Master Block ...................................................................................1140
25.8 Filter Example Simulation ..........................................................................................................1141
25.8.1 Coefficients Calculation ................................................................................................1141
25.8.2 Input Data Calculation ..................................................................................................1142
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16 Freescale Semiconductor
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25.8.3 Filter Results .................................................................................................................1143
Chapter 26
Deserial Serial Peripheral Interface (DSPI)
26.1 Information Specific to This Device ...........................................................................................1145
26.1.1 Device-Specific Features ..............................................................................................1145
26.1.2 LVDS Pad Usage ..........................................................................................................1145
26.2 Introduction .................................................................................................................................1145
26.2.1 Overview .......................................................................................................................1146
26.2.2 Features .........................................................................................................................1147
26.2.3 DSPI Configurations .....................................................................................................1148
26.2.4 Modes of Operation ......................................................................................................1149
26.3 External Signal Description ........................................................................................................1150
26.3.1 Overview .......................................................................................................................1150
26.3.2 Detailed Signal Description ..........................................................................................1151
26.4 Memory Map and Register Definition ........................................................................................1152
26.4.1 Memory Map ................................................................................................................1152
26.4.2 Register Descriptions ....................................................................................................1153
26.5 Functional Description ................................................................................................................1175
26.5.1 Modes of Operation ......................................................................................................1176
26.5.2 Start and Stop of DSPI Transfers ..................................................................................1178
26.5.3 Serial Peripheral Interface (SPI) Configuration ............................................................1179
26.5.4 Deserial Serial Interface (DSI) Configuration ..............................................................1182
26.5.5 Combined Serial Interface (CSI) Configuration ...........................................................1187
26.5.6 DSPI Baud Rate and Clock Delay Generation .............................................................1190
26.5.7 Transfer Formats ...........................................................................................................1193
26.5.8 Continuous Serial Communications Clock ...................................................................1200
26.5.9 Timed Serial Bus (TSB) ................................................................................................1201
26.5.10Interrupts/DMA Requests .............................................................................................1204
26.5.11Power Saving Features ..................................................................................................1206
26.6 Initialization/Application Information ........................................................................................1207
26.6.1 How to Change Queues ................................................................................................1207
26.6.2 Baud Rate Settings ........................................................................................................1208
26.6.3 Delay Settings ...............................................................................................................1209
26.6.4 Calculation of FIFO Pointer Addresses ........................................................................1210
Chapter 27
Enhanced Serial Communication Interface (eSCI)
27.1 Introduction .................................................................................................................................1213
27.1.1 Bibliography .................................................................................................................1213
27.1.2 Acronyms and Abbreviations .......................................................................................1213
27.1.3 Glossary ........................................................................................................................1213
27.1.4 Overview .......................................................................................................................1214
27.1.5 Features .........................................................................................................................1214
27.1.6 Modes of Operation ......................................................................................................1215
MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 17
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27.2 External Signal Description ........................................................................................................1216
27.2.1 Detailed Signal Descriptions ........................................................................................1216
27.3 Memory Map and Register Definition ........................................................................................1216
27.3.1 Memory Map ................................................................................................................1216
27.3.2 Register Descriptions ....................................................................................................1218
27.4 Functional Description ................................................................................................................1234
27.4.1 Module Control .............................................................................................................1234
27.4.2 Frame Formats ..............................................................................................................1234
27.4.3 Baud Rate and Clock Generation ..................................................................................1237
27.4.4 Baud Rate Tolerance .....................................................................................................1239
27.4.5 SCI Mode ......................................................................................................................1241
27.4.6 LIN Mode .....................................................................................................................1256
27.4.7 Interrupts .......................................................................................................................1264
27.5 Application Information ..............................................................................................................1265
27.5.1 SCI Data Frames Separated by Preamble .....................................................................1265
Chapter 28
FlexCAN Module
28.1 Information Specific to This Device ...........................................................................................1267
28.1.1 Device-Specific Features ..............................................................................................1267
28.2 Introduction .................................................................................................................................1267
28.2.1 Overview .......................................................................................................................1268
28.2.2 FlexCAN Module Features ...........................................................................................1269
28.2.3 Modes of Operation ......................................................................................................1270
28.3 External Signal Description ........................................................................................................1271
28.3.1 Overview .......................................................................................................................1271
28.3.2 Signal Descriptions .......................................................................................................1271
28.4 Memory Map/Register Definition ...............................................................................................1271
28.4.1 FlexCAN Memory Mapping .........................................................................................1272
28.4.2 Message Buffer Structure ..............................................................................................1273
28.4.3 Rx FIFO Structure .........................................................................................................1277
28.4.4 Register Descriptions ....................................................................................................1278
28.5 Functional Description ................................................................................................................1297
28.5.1 Overview .......................................................................................................................1297
28.5.2 Transmit Process ...........................................................................................................1298
28.5.3 Arbitration process ........................................................................................................1299
28.5.4 Receive Process ............................................................................................................1299
28.5.5 Matching Process ..........................................................................................................1301
28.5.6 Data Coherence .............................................................................................................1302
28.5.7 Rx FIFO ........................................................................................................................1305
28.5.8 CAN Protocol Related Features ....................................................................................1305
28.5.9 Modes of Operation Details ..........................................................................................1310
28.5.10Interrupts .......................................................................................................................1313
28.5.11Bus Interface .................................................................................................................1313
28.6 Initialization/Application Information ........................................................................................1314
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28.6.1 FlexCAN Initialization Sequence .................................................................................1314
28.6.2 FlexCAN Addressing and RAM size configurations ...................................................1315
Chapter 29
Periodic Interrupt Timer (PIT_RTI)
29.1 Information Specific to This Device ...........................................................................................1317
29.1.1 Device-Specific Features ..............................................................................................1317
29.2 Introduction .................................................................................................................................1317
29.2.1 Overview .......................................................................................................................1318
29.2.2 Features .........................................................................................................................1318
29.3 Modes of Operation .....................................................................................................................1319
29.4 Signal Description .......................................................................................................................1319
29.5 Memory Map and Register Description ......................................................................................1319
29.5.1 Memory Map ................................................................................................................1319
29.5.2 Register Descriptions ....................................................................................................1320
29.6 Functional Description ................................................................................................................1325
29.6.1 General ..........................................................................................................................1325
29.6.2 Interrupts .......................................................................................................................1326
29.7 Initialization and Application Information ..................................................................................1327
29.7.1 Example Configuration .................................................................................................1327
Chapter 30
Power Management Controller (PMC)
30.1 Introduction .................................................................................................................................1329
30.1.1 Block Diagram .............................................................................................................1330
30.2 External Signal Description ........................................................................................................1331
30.2.1 Detailed Signal Descriptions ........................................................................................1331
30.3 Memory Map/Register Definition ...............................................................................................1332
30.3.1 Configuration and Status Register (CFGR) ..................................................................1332
30.3.2 Trimming Register (TRIMR) ........................................................................................1334
30.3.3 Status Register (SR) ......................................................................................................1337
30.4 Functional Description ................................................................................................................1340
30.4.1 Bandgap ........................................................................................................................1340
30.4.2 5V LVI ..........................................................................................................................1341
30.4.3 3.3V Internal Voltage Regulator ...................................................................................1341
30.4.4 3.3V LVI .......................................................................................................................1343
30.4.5 1.2V Voltage Regulator Controller ...............................................................................1343
30.4.6 1.2V LVI .......................................................................................................................1344
30.4.7 LVI 1.0V .......................................................................................................................1344
30.4.8 Resets and Interrupts .....................................................................................................1344
30.5 Application Information ..............................................................................................................1347
30.5.1 Regulator Example .......................................................................................................1347
30.5.2 Recommended Power Transistors .................................................................................1347
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Freescale Semiconductor 19
Preliminary—Subject to Change Without Notice
Chapter 31
JTAG Controller (JTAGC)
31.1 Information Specific to This Device ...........................................................................................1349
31.1.1 Device-Specific Parameters ..........................................................................................1349
31.1.2 Device Identification Register Parameters ...................................................................1349
31.1.3 Unavailable Instructions ...............................................................................................1349
31.1.4 Auxiliary TAP Controller Instructions ..........................................................................1350
31.2 Introduction .................................................................................................................................1350
31.2.1 Overview .......................................................................................................................1350
31.2.2 Features .........................................................................................................................1351
31.2.3 Modes of Operation ......................................................................................................1351
31.3 External Signal Description ........................................................................................................1352
31.3.1 Overview .......................................................................................................................1352
31.3.2 Detailed Signal Descriptions ........................................................................................1352
31.4 Register Definition ......................................................................................................................1353
31.4.1 Register Descriptions ....................................................................................................1353
31.5 Functional Description ................................................................................................................1356
31.5.1 JTAGC Reset Configuration .........................................................................................1356
31.5.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................1356
31.5.3 TAP Controller State Machine ......................................................................................1356
31.5.4 JTAGC Block Instructions ............................................................................................1358
31.5.5 Boundary Scan ..............................................................................................................1360
31.6 Initialization/Application Information ........................................................................................1360
Chapter 32
Nexus Port Controller (NPC)
32.1 Information Specific to This Device ...........................................................................................1363
32.1.1 Parameter Values ...........................................................................................................1363
32.1.2 Unavailable Features .....................................................................................................1363
32.1.3 Available Features .........................................................................................................1364
32.1.4 Nexus Clients ................................................................................................................1364
32.2 Introduction .................................................................................................................................1364
32.2.1 Overview .......................................................................................................................1364
32.2.2 Features .........................................................................................................................1365
32.2.3 Modes of Operation ......................................................................................................1365
32.2.4 Device-Specific Parameters ..........................................................................................1366
32.3 External Signal Description ........................................................................................................1367
32.3.1 Overview .......................................................................................................................1367
32.3.2 Detailed Signal Descriptions ........................................................................................1367
32.4 Register Definition ......................................................................................................................1368
32.4.1 Register Descriptions ....................................................................................................1369
32.5 Functional Description ................................................................................................................1373
32.5.1 NPC Reset Configuration .............................................................................................1373
32.5.2 Auxiliary Output Port ...................................................................................................1373
32.5.3 IEEE 1149.1-2001 (JTAG) TAP ...................................................................................1376
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32.5.4 Nexus JTAG Port Sharing ............................................................................................1380
32.5.5 MCKO and ipg_sync_mcko .........................................................................................1380
32.5.6 EVTO Sharing ..............................................................................................................1380
32.5.7 Nexus Reset Control .....................................................................................................1380
32.5.8 System Clock Locked Indication ..................................................................................1380
32.6 Initialization/Application Information ........................................................................................1381
32.6.1 Accessing NPC tool-mapped registers .........................................................................1381
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