NXP K10_100 Reference guide

Type
Reference guide
K10 Sub-Family Reference Manual
Supports: MK10DX128VLQ10, MK10DX128VMD10,
MK10DX256VLQ10, MK10DX256VMD10, MK10DN512VLQ10,
MK10DN512VMD10
Document Number: K10P144M100SF2V2RM
Rev. 2 Jun 2012
Preliminary
General Business Information
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
2
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose.........................................................................................................................................................53
1.1.2 Audience......................................................................................................................................................53
1.2 Conventions..................................................................................................................................................................53
1.2.1 Numbering systems......................................................................................................................................53
1.2.2 Typographic notation...................................................................................................................................54
1.2.3 Special terms................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 Module Functional Categories......................................................................................................................................55
2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................56
2.2.2 System Modules...........................................................................................................................................57
2.2.3 Memories and Memory Interfaces...............................................................................................................58
2.2.4 Clocks...........................................................................................................................................................59
2.2.5 Security and Integrity modules....................................................................................................................59
2.2.6 Analog modules...........................................................................................................................................59
2.2.7 Timer modules.............................................................................................................................................60
2.2.8 Communication interfaces...........................................................................................................................61
2.2.9 Human-machine interfaces..........................................................................................................................62
2.3 Orderable part numbers.................................................................................................................................................62
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................65
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
3
General Business Information
Section number Title Page
3.2 Core modules................................................................................................................................................................65
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................67
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................73
3.2.4 JTAG Controller Configuration...................................................................................................................75
3.3 System modules............................................................................................................................................................75
3.3.1 SIM Configuration.......................................................................................................................................75
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................76
3.3.3 PMC Configuration......................................................................................................................................77
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................77
3.3.5 MCM Configuration....................................................................................................................................79
3.3.6 Crossbar Switch Configuration....................................................................................................................80
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................82
3.3.8 Peripheral Bridge Configuration..................................................................................................................85
3.3.9 DMA request multiplexer configuration......................................................................................................86
3.3.10 DMA Controller Configuration...................................................................................................................89
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................90
3.3.12 Watchdog Configuration..............................................................................................................................91
3.4 Clock modules..............................................................................................................................................................92
3.4.1 MCG Configuration.....................................................................................................................................92
3.4.2 OSC Configuration......................................................................................................................................93
3.4.3 RTC OSC configuration...............................................................................................................................94
3.5 Memories and memory interfaces.................................................................................................................................94
3.5.1 Flash Memory Configuration.......................................................................................................................94
3.5.2 Flash Memory Controller Configuration.....................................................................................................98
3.5.3 SRAM Configuration...................................................................................................................................99
3.5.4 SRAM Controller Configuration.................................................................................................................103
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
4
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
3.5.5 System Register File Configuration.............................................................................................................103
3.5.6 VBAT Register File Configuration..............................................................................................................104
3.5.7 EzPort Configuration...................................................................................................................................105
3.5.8 FlexBus Configuration.................................................................................................................................106
3.6 Security.........................................................................................................................................................................109
3.6.1 CRC Configuration......................................................................................................................................109
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
5
General Business Information
Section number Title Page
3.7 Analog...........................................................................................................................................................................110
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................110
3.7.2 CMP Configuration......................................................................................................................................118
3.7.3 12-bit DAC Configuration...........................................................................................................................120
3.7.4 VREF Configuration....................................................................................................................................121
3.8 Timers...........................................................................................................................................................................122
3.8.1 PDB Configuration......................................................................................................................................122
3.8.2 FlexTimer Configuration.............................................................................................................................125
3.8.3 PIT Configuration........................................................................................................................................129
3.8.4 Low-power timer configuration...................................................................................................................130
3.8.5 CMT Configuration......................................................................................................................................132
3.8.6 RTC configuration.......................................................................................................................................133
3.9 Communication interfaces............................................................................................................................................134
3.9.1 CAN Configuration......................................................................................................................................134
3.9.2 SPI configuration.........................................................................................................................................136
3.9.3 I2C Configuration........................................................................................................................................140
3.9.4 UART Configuration...................................................................................................................................140
3.9.5 SDHC Configuration....................................................................................................................................143
3.9.6 I2S configuration..........................................................................................................................................145
3.10 Human-machine interfaces...........................................................................................................................................147
3.10.1 GPIO configuration......................................................................................................................................147
3.10.2 TSI Configuration........................................................................................................................................148
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................151
4.2 System memory map.....................................................................................................................................................151
4.2.1 Aliased bit-band regions..............................................................................................................................152
4.3 Flash Memory Map.......................................................................................................................................................153
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................154
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
6
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
4.4 SRAM memory map.....................................................................................................................................................155
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................155
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................155
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................159
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................163
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................165
5.2 Programming model......................................................................................................................................................165
5.3 High-Level device clocking diagram............................................................................................................................165
5.4 Clock definitions...........................................................................................................................................................166
5.4.1 Device clock summary.................................................................................................................................167
5.5 Internal clocking requirements.....................................................................................................................................169
5.5.1 Clock divider values after reset....................................................................................................................170
5.5.2 VLPR mode clocking...................................................................................................................................170
5.6 Clock Gating.................................................................................................................................................................171
5.7 Module clocks...............................................................................................................................................................171
5.7.1 PMC 1-kHz LPO clock................................................................................................................................172
5.7.2 WDOG clocking..........................................................................................................................................173
5.7.3 Debug trace clock.........................................................................................................................................173
5.7.4 PORT digital filter clocking.........................................................................................................................174
5.7.5 LPTMR clocking..........................................................................................................................................174
5.7.6 FlexCAN clocking.......................................................................................................................................175
5.7.7 UART clocking............................................................................................................................................175
5.7.8 SDHC clocking............................................................................................................................................175
5.7.9 I2S/SAI clocking..........................................................................................................................................176
5.7.10 TSI clocking.................................................................................................................................................176
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
7
General Business Information
Section number Title Page
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................179
6.2 Reset..............................................................................................................................................................................180
6.2.1 Power-on reset (POR)..................................................................................................................................180
6.2.2 System reset sources....................................................................................................................................180
6.2.3 MCU Resets.................................................................................................................................................184
6.2.4 Reset Pin .....................................................................................................................................................186
6.2.5 Debug resets.................................................................................................................................................186
6.3 Boot...............................................................................................................................................................................187
6.3.1 Boot sources.................................................................................................................................................187
6.3.2 Boot options.................................................................................................................................................188
6.3.3 FOPT boot options.......................................................................................................................................188
6.3.4 Boot sequence..............................................................................................................................................189
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................191
7.2 Power modes.................................................................................................................................................................191
7.3 Entering and exiting power modes...............................................................................................................................193
7.4 Power mode transitions.................................................................................................................................................194
7.5 Power modes shutdown sequencing.............................................................................................................................195
7.6 Module Operation in Low Power Modes......................................................................................................................195
7.7 Clock Gating.................................................................................................................................................................198
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................199
8.2 Flash Security...............................................................................................................................................................199
8.3 Security Interactions with other Modules.....................................................................................................................200
8.3.1 Security interactions with FlexBus..............................................................................................................200
8.3.2 Security Interactions with EzPort................................................................................................................200
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
8
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
8.3.3 Security Interactions with Debug.................................................................................................................200
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................203
9.1.1 References....................................................................................................................................................205
9.2 The Debug Port.............................................................................................................................................................205
9.2.1 JTAG-to-SWD change sequence.................................................................................................................206
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................206
9.3 Debug Port Pin Descriptions.........................................................................................................................................207
9.4 System TAP connection................................................................................................................................................207
9.4.1 IR Codes.......................................................................................................................................................207
9.5 JTAG status and control registers.................................................................................................................................208
9.5.1 MDM-AP Control Register..........................................................................................................................209
9.5.2 MDM-AP Status Register............................................................................................................................211
9.6 Debug Resets................................................................................................................................................................212
9.7 AHB-AP........................................................................................................................................................................213
9.8 ITM...............................................................................................................................................................................214
9.9 Core Trace Connectivity...............................................................................................................................................214
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................215
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................216
9.11.1 Performance Profiling with the ETB...........................................................................................................216
9.11.2 ETB Counter Control...................................................................................................................................217
9.12 TPIU..............................................................................................................................................................................217
9.13 DWT.............................................................................................................................................................................217
9.14 Debug in Low Power Modes........................................................................................................................................218
9.14.1 Debug Module State in Low Power Modes.................................................................................................219
9.15 Debug & Security.........................................................................................................................................................219
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
9
General Business Information
Section number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................221
10.2 Signal Multiplexing Integration....................................................................................................................................221
10.2.1 Port control and interrupt module features..................................................................................................222
10.2.2 PCRn reset values for port A.......................................................................................................................222
10.2.3 Clock gating.................................................................................................................................................222
10.2.4 Signal multiplexing constraints....................................................................................................................222
10.3 Pinout............................................................................................................................................................................223
10.3.1 K10 Signal Multiplexing and Pin Assignments...........................................................................................223
10.3.2 K10 Pinouts..................................................................................................................................................229
10.4 Module Signal Description Tables................................................................................................................................231
10.4.1 Core Modules...............................................................................................................................................231
10.4.2 System Modules...........................................................................................................................................232
10.4.3 Clock Modules.............................................................................................................................................233
10.4.4 Memories and Memory Interfaces...............................................................................................................233
10.4.5 Analog..........................................................................................................................................................236
10.4.6 Timer Modules.............................................................................................................................................238
10.4.7 Communication Interfaces...........................................................................................................................240
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................243
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................245
11.2 Overview.......................................................................................................................................................................245
11.2.1 Features........................................................................................................................................................245
11.2.2 Modes of operation......................................................................................................................................246
11.3 External signal description............................................................................................................................................247
11.4 Detailed signal description............................................................................................................................................247
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
10
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
11.5 Memory map and register definition.............................................................................................................................247
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................253
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................256
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................256
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................257
11.6 Functional description...................................................................................................................................................257
11.6.1 Pin control....................................................................................................................................................257
11.6.2 Global pin control........................................................................................................................................258
11.6.3 External interrupts........................................................................................................................................258
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................261
12.1.1 Features........................................................................................................................................................261
12.2 Memory map and register definition.............................................................................................................................262
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................263
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................265
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................267
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................269
12.2.5 System Options Register 7 (SIM_SOPT7)..................................................................................................271
12.2.6 System Device Identification Register (SIM_SDID)...................................................................................273
12.2.7 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................274
12.2.8 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................275
12.2.9 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................276
12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................278
12.2.11 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................280
12.2.12 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................282
12.2.13 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................284
12.2.14 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................285
12.2.15 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................287
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
11
General Business Information
Section number Title Page
12.2.16 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................288
12.2.17 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................290
12.2.18 Unique Identification Register High (SIM_UIDH).....................................................................................291
12.2.19 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................292
12.2.20 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................292
12.2.21 Unique Identification Register Low (SIM_UIDL)......................................................................................293
12.3 Functional description...................................................................................................................................................293
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................295
13.2 Reset memory map and register descriptions...............................................................................................................295
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................295
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................297
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................298
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................299
13.2.5 Mode Register (RCM_MR).........................................................................................................................301
Chapter 14
System Mode Controller
14.1 Introduction...................................................................................................................................................................303
14.2 Modes of operation.......................................................................................................................................................303
14.3 Memory map and register descriptions.........................................................................................................................305
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................306
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................307
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................308
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................309
14.4 Functional description...................................................................................................................................................310
14.4.1 Power mode transitions................................................................................................................................310
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
12
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
14.4.2 Power mode entry/exit sequencing..............................................................................................................313
14.4.3 Run modes....................................................................................................................................................315
14.4.4 Wait modes..................................................................................................................................................317
14.4.5 Stop modes...................................................................................................................................................318
14.4.6 Debug in low power modes.........................................................................................................................321
Chapter 15
Power Management Controller
15.1 Introduction...................................................................................................................................................................323
15.2 Features.........................................................................................................................................................................323
15.3 Low-voltage detect (LVD) system................................................................................................................................323
15.3.1 LVD reset operation.....................................................................................................................................324
15.3.2 LVD interrupt operation...............................................................................................................................324
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................324
15.4 I/O retention..................................................................................................................................................................325
15.5 Memory map and register descriptions.........................................................................................................................325
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................326
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................327
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................328
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................331
16.1.1 Features........................................................................................................................................................331
16.1.2 Modes of operation......................................................................................................................................332
16.1.3 Block diagram..............................................................................................................................................333
16.2 LLWU signal descriptions............................................................................................................................................334
16.3 Memory map/register definition...................................................................................................................................335
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................336
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................337
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................338
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
13
General Business Information
Section number Title Page
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................339
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................340
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................342
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................343
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................345
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................347
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................348
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................349
16.4 Functional description...................................................................................................................................................350
16.4.1 LLS mode.....................................................................................................................................................350
16.4.2 VLLS modes................................................................................................................................................350
16.4.3 Initialization.................................................................................................................................................351
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................353
17.1.1 Features........................................................................................................................................................353
17.2 Memory map/register descriptions...............................................................................................................................353
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................354
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................355
17.2.3 Control Register (MCM_CR)......................................................................................................................355
17.2.4 Interrupt Status Register (MCM_ISR).........................................................................................................357
17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................358
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................359
17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................359
17.2.8 Process ID register (MCM_PID).................................................................................................................360
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
14
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
17.3 Functional description...................................................................................................................................................360
17.3.1 Interrupts......................................................................................................................................................360
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................363
18.1.1 Features........................................................................................................................................................363
18.2 Memory Map / Register Definition...............................................................................................................................364
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................365
18.2.2 Control Register (AXBS_CRSn).................................................................................................................368
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................370
18.3 Functional Description..................................................................................................................................................370
18.3.1 General operation.........................................................................................................................................370
18.3.2 Register coherency.......................................................................................................................................372
18.3.3 Arbitration....................................................................................................................................................372
18.4 Initialization/application information...........................................................................................................................375
Chapter 19
Memory Protection Unit (MPU)
19.1 Introduction...................................................................................................................................................................377
19.2 Overview.......................................................................................................................................................................377
19.2.1 Block diagram..............................................................................................................................................377
19.2.2 Features........................................................................................................................................................378
19.3 Memory map/register definition...................................................................................................................................379
19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................383
19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................384
19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................385
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................386
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................386
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................387
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................390
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
15
General Business Information
Section number Title Page
19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................391
19.4 Functional description...................................................................................................................................................393
19.4.1 Access evaluation macro..............................................................................................................................393
19.4.2 Putting it all together and error terminations...............................................................................................394
19.4.3 Power management......................................................................................................................................395
19.5 Initialization information..............................................................................................................................................395
19.6 Application information................................................................................................................................................395
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................399
20.1.1 Features........................................................................................................................................................399
20.1.2 General operation.........................................................................................................................................400
20.2 Memory map/register definition...................................................................................................................................400
20.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................402
20.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................405
20.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................410
20.3 Functional description...................................................................................................................................................415
20.3.1 Access support.............................................................................................................................................415
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................417
21.1.1 Overview......................................................................................................................................................417
21.1.2 Features........................................................................................................................................................418
21.1.3 Modes of operation......................................................................................................................................418
21.2 External signal description............................................................................................................................................419
21.3 Memory map/register definition...................................................................................................................................419
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................420
21.4 Functional description...................................................................................................................................................421
21.4.1 DMA channels with periodic triggering capability......................................................................................421
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
16
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
21.4.2 DMA channels with no triggering capability...............................................................................................423
21.4.3 "Always enabled" DMA sources.................................................................................................................423
21.5 Initialization/application information...........................................................................................................................424
21.5.1 Reset.............................................................................................................................................................425
21.5.2 Enabling and configuring sources................................................................................................................425
Chapter 22
Direct Memory Access Controller (eDMA)
22.1 Introduction...................................................................................................................................................................429
22.1.1 Block diagram..............................................................................................................................................429
22.1.2 Block parts...................................................................................................................................................430
22.1.3 Features........................................................................................................................................................431
22.2 Modes of operation.......................................................................................................................................................433
22.3 Memory map/register definition...................................................................................................................................433
22.3.1 Control Register (DMA_CR).......................................................................................................................444
22.3.2 Error Status Register (DMA_ES)................................................................................................................446
22.3.3 Enable Request Register (DMA_ ERQ ).....................................................................................................448
22.3.4 Enable Error Interrupt Register (DMA_ EEI ).............................................................................................450
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................453
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................454
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................455
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................456
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................457
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................458
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................459
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................460
22.3.13 Interrupt Request Register (DMA_ INT )....................................................................................................461
22.3.14 Error Register (DMA_ ERR )......................................................................................................................463
22.3.15 Hardware Request Status Register (DMA_ HRS )......................................................................................466
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................468
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
17
General Business Information
Section number Title Page
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................469
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................469
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................470
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................471
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................471
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................472
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................474
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................474
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................475
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................475
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................476
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........477
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................478
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................480
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................481
22.4 Functional description...................................................................................................................................................482
22.4.1 eDMA basic data flow.................................................................................................................................482
22.4.2 Error reporting and handling........................................................................................................................485
22.4.3 Channel preemption.....................................................................................................................................487
22.4.4 Performance.................................................................................................................................................487
22.5 Initialization/application information...........................................................................................................................492
22.5.1 eDMA initialization.....................................................................................................................................492
22.5.2 Programming errors.....................................................................................................................................494
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
18
Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
22.5.3 Arbitration mode considerations..................................................................................................................494
22.5.4 Performing DMA transfers (examples)........................................................................................................495
22.5.5 Monitoring transfer descriptor status...........................................................................................................499
22.5.6 Channel Linking...........................................................................................................................................500
22.5.7 Dynamic programming................................................................................................................................502
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................507
23.1.1 Features........................................................................................................................................................507
23.1.2 Modes of Operation.....................................................................................................................................508
23.1.3 Block Diagram.............................................................................................................................................509
23.2 EWM Signal Descriptions............................................................................................................................................510
23.3 Memory Map/Register Definition.................................................................................................................................510
23.3.1 Control Register (EWM_CTRL).................................................................................................................510
23.3.2 Service Register (EWM_SERV)..................................................................................................................511
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................511
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................512
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................513
23.4 Functional Description..................................................................................................................................................513
23.4.1 The EWM_out Signal..................................................................................................................................513
23.4.2 The EWM_in Signal....................................................................................................................................514
23.4.3 EWM Counter..............................................................................................................................................515
23.4.4 EWM Compare Registers............................................................................................................................515
23.4.5 EWM Refresh Mechanism...........................................................................................................................515
23.4.6 EWM Interrupt.............................................................................................................................................516
23.4.7 Counter clock prescaler................................................................................................................................516
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................517
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
19
General Business Information
Section number Title Page
24.2 Features.........................................................................................................................................................................517
24.3 Functional overview......................................................................................................................................................519
24.3.1 Unlocking and updating the watchdog.........................................................................................................520
24.3.2 Watchdog configuration time (WCT)..........................................................................................................521
24.3.3 Refreshing the watchdog..............................................................................................................................522
24.3.4 Windowed mode of operation......................................................................................................................522
24.3.5 Watchdog disabled mode of operation.........................................................................................................522
24.3.6 Low-power modes of operation...................................................................................................................523
24.3.7 Debug modes of operation...........................................................................................................................523
24.4 Testing the watchdog....................................................................................................................................................524
24.4.1 Quick test.....................................................................................................................................................524
24.4.2 Byte test........................................................................................................................................................525
24.5 Backup reset generator..................................................................................................................................................526
24.6 Generated resets and interrupts.....................................................................................................................................526
24.7 Memory map and register definition.............................................................................................................................527
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................528
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................529
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................530
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................530
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................531
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................531
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................532
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................532
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................532
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................533
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................533
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................534
24.8 Watchdog operation with 8-bit access..........................................................................................................................534
24.8.1 General guideline.........................................................................................................................................534
K10 Sub-Family Reference Manual, Rev. 2 Jun 2012
20
Preliminary
Freescale Semiconductor, Inc.
General Business Information
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26
  • Page 27 27
  • Page 28 28
  • Page 29 29
  • Page 30 30
  • Page 31 31
  • Page 32 32
  • Page 33 33
  • Page 34 34
  • Page 35 35
  • Page 36 36
  • Page 37 37
  • Page 38 38
  • Page 39 39
  • Page 40 40
  • Page 41 41
  • Page 42 42
  • Page 43 43
  • Page 44 44
  • Page 45 45
  • Page 46 46
  • Page 47 47
  • Page 48 48
  • Page 49 49
  • Page 50 50
  • Page 51 51
  • Page 52 52
  • Page 53 53
  • Page 54 54
  • Page 55 55
  • Page 56 56
  • Page 57 57
  • Page 58 58
  • Page 59 59
  • Page 60 60
  • Page 61 61
  • Page 62 62
  • Page 63 63
  • Page 64 64
  • Page 65 65
  • Page 66 66
  • Page 67 67
  • Page 68 68
  • Page 69 69
  • Page 70 70
  • Page 71 71
  • Page 72 72
  • Page 73 73
  • Page 74 74
  • Page 75 75
  • Page 76 76
  • Page 77 77
  • Page 78 78
  • Page 79 79
  • Page 80 80
  • Page 81 81
  • Page 82 82
  • Page 83 83
  • Page 84 84
  • Page 85 85
  • Page 86 86
  • Page 87 87
  • Page 88 88
  • Page 89 89
  • Page 90 90
  • Page 91 91
  • Page 92 92
  • Page 93 93
  • Page 94 94
  • Page 95 95
  • Page 96 96
  • Page 97 97
  • Page 98 98
  • Page 99 99
  • Page 100 100
  • Page 101 101
  • Page 102 102
  • Page 103 103
  • Page 104 104
  • Page 105 105
  • Page 106 106
  • Page 107 107
  • Page 108 108
  • Page 109 109
  • Page 110 110
  • Page 111 111
  • Page 112 112
  • Page 113 113
  • Page 114 114
  • Page 115 115
  • Page 116 116
  • Page 117 117
  • Page 118 118
  • Page 119 119
  • Page 120 120
  • Page 121 121
  • Page 122 122
  • Page 123 123
  • Page 124 124
  • Page 125 125
  • Page 126 126
  • Page 127 127
  • Page 128 128
  • Page 129 129
  • Page 130 130
  • Page 131 131
  • Page 132 132
  • Page 133 133
  • Page 134 134
  • Page 135 135
  • Page 136 136
  • Page 137 137
  • Page 138 138
  • Page 139 139
  • Page 140 140
  • Page 141 141
  • Page 142 142
  • Page 143 143
  • Page 144 144
  • Page 145 145
  • Page 146 146
  • Page 147 147
  • Page 148 148
  • Page 149 149
  • Page 150 150
  • Page 151 151
  • Page 152 152
  • Page 153 153
  • Page 154 154
  • Page 155 155
  • Page 156 156
  • Page 157 157
  • Page 158 158
  • Page 159 159
  • Page 160 160
  • Page 161 161
  • Page 162 162
  • Page 163 163
  • Page 164 164
  • Page 165 165
  • Page 166 166
  • Page 167 167
  • Page 168 168
  • Page 169 169
  • Page 170 170
  • Page 171 171
  • Page 172 172
  • Page 173 173
  • Page 174 174
  • Page 175 175
  • Page 176 176
  • Page 177 177
  • Page 178 178
  • Page 179 179
  • Page 180 180
  • Page 181 181
  • Page 182 182
  • Page 183 183
  • Page 184 184
  • Page 185 185
  • Page 186 186
  • Page 187 187
  • Page 188 188
  • Page 189 189
  • Page 190 190
  • Page 191 191
  • Page 192 192
  • Page 193 193
  • Page 194 194
  • Page 195 195
  • Page 196 196
  • Page 197 197
  • Page 198 198
  • Page 199 199
  • Page 200 200
  • Page 201 201
  • Page 202 202
  • Page 203 203
  • Page 204 204
  • Page 205 205
  • Page 206 206
  • Page 207 207
  • Page 208 208
  • Page 209 209
  • Page 210 210
  • Page 211 211
  • Page 212 212
  • Page 213 213
  • Page 214 214
  • Page 215 215
  • Page 216 216
  • Page 217 217
  • Page 218 218
  • Page 219 219
  • Page 220 220
  • Page 221 221
  • Page 222 222
  • Page 223 223
  • Page 224 224
  • Page 225 225
  • Page 226 226
  • Page 227 227
  • Page 228 228
  • Page 229 229
  • Page 230 230
  • Page 231 231
  • Page 232 232
  • Page 233 233
  • Page 234 234
  • Page 235 235
  • Page 236 236
  • Page 237 237
  • Page 238 238
  • Page 239 239
  • Page 240 240
  • Page 241 241
  • Page 242 242
  • Page 243 243
  • Page 244 244
  • Page 245 245
  • Page 246 246
  • Page 247 247
  • Page 248 248
  • Page 249 249
  • Page 250 250
  • Page 251 251
  • Page 252 252
  • Page 253 253
  • Page 254 254
  • Page 255 255
  • Page 256 256
  • Page 257 257
  • Page 258 258
  • Page 259 259
  • Page 260 260
  • Page 261 261
  • Page 262 262
  • Page 263 263
  • Page 264 264
  • Page 265 265
  • Page 266 266
  • Page 267 267
  • Page 268 268
  • Page 269 269
  • Page 270 270
  • Page 271 271
  • Page 272 272
  • Page 273 273
  • Page 274 274
  • Page 275 275
  • Page 276 276
  • Page 277 277
  • Page 278 278
  • Page 279 279
  • Page 280 280
  • Page 281 281
  • Page 282 282
  • Page 283 283
  • Page 284 284
  • Page 285 285
  • Page 286 286
  • Page 287 287
  • Page 288 288
  • Page 289 289
  • Page 290 290
  • Page 291 291
  • Page 292 292
  • Page 293 293
  • Page 294 294
  • Page 295 295
  • Page 296 296
  • Page 297 297
  • Page 298 298
  • Page 299 299
  • Page 300 300
  • Page 301 301
  • Page 302 302
  • Page 303 303
  • Page 304 304
  • Page 305 305
  • Page 306 306
  • Page 307 307
  • Page 308 308
  • Page 309 309
  • Page 310 310
  • Page 311 311
  • Page 312 312
  • Page 313 313
  • Page 314 314
  • Page 315 315
  • Page 316 316
  • Page 317 317
  • Page 318 318
  • Page 319 319
  • Page 320 320
  • Page 321 321
  • Page 322 322
  • Page 323 323
  • Page 324 324
  • Page 325 325
  • Page 326 326
  • Page 327 327
  • Page 328 328
  • Page 329 329
  • Page 330 330
  • Page 331 331
  • Page 332 332
  • Page 333 333
  • Page 334 334
  • Page 335 335
  • Page 336 336
  • Page 337 337
  • Page 338 338
  • Page 339 339
  • Page 340 340
  • Page 341 341
  • Page 342 342
  • Page 343 343
  • Page 344 344
  • Page 345 345
  • Page 346 346
  • Page 347 347
  • Page 348 348
  • Page 349 349
  • Page 350 350
  • Page 351 351
  • Page 352 352
  • Page 353 353
  • Page 354 354
  • Page 355 355
  • Page 356 356
  • Page 357 357
  • Page 358 358
  • Page 359 359
  • Page 360 360
  • Page 361 361
  • Page 362 362
  • Page 363 363
  • Page 364 364
  • Page 365 365
  • Page 366 366
  • Page 367 367
  • Page 368 368
  • Page 369 369
  • Page 370 370
  • Page 371 371
  • Page 372 372
  • Page 373 373
  • Page 374 374
  • Page 375 375
  • Page 376 376
  • Page 377 377
  • Page 378 378
  • Page 379 379
  • Page 380 380
  • Page 381 381
  • Page 382 382
  • Page 383 383
  • Page 384 384
  • Page 385 385
  • Page 386 386
  • Page 387 387
  • Page 388 388
  • Page 389 389
  • Page 390 390
  • Page 391 391
  • Page 392 392
  • Page 393 393
  • Page 394 394
  • Page 395 395
  • Page 396 396
  • Page 397 397
  • Page 398 398
  • Page 399 399
  • Page 400 400
  • Page 401 401
  • Page 402 402
  • Page 403 403
  • Page 404 404
  • Page 405 405
  • Page 406 406
  • Page 407 407
  • Page 408 408
  • Page 409 409
  • Page 410 410
  • Page 411 411
  • Page 412 412
  • Page 413 413
  • Page 414 414
  • Page 415 415
  • Page 416 416
  • Page 417 417
  • Page 418 418
  • Page 419 419
  • Page 420 420
  • Page 421 421
  • Page 422 422
  • Page 423 423
  • Page 424 424
  • Page 425 425
  • Page 426 426
  • Page 427 427
  • Page 428 428
  • Page 429 429
  • Page 430 430
  • Page 431 431
  • Page 432 432
  • Page 433 433
  • Page 434 434
  • Page 435 435
  • Page 436 436
  • Page 437 437
  • Page 438 438
  • Page 439 439
  • Page 440 440
  • Page 441 441
  • Page 442 442
  • Page 443 443
  • Page 444 444
  • Page 445 445
  • Page 446 446
  • Page 447 447
  • Page 448 448
  • Page 449 449
  • Page 450 450
  • Page 451 451
  • Page 452 452
  • Page 453 453
  • Page 454 454
  • Page 455 455
  • Page 456 456
  • Page 457 457
  • Page 458 458
  • Page 459 459
  • Page 460 460
  • Page 461 461
  • Page 462 462
  • Page 463 463
  • Page 464 464
  • Page 465 465
  • Page 466 466
  • Page 467 467
  • Page 468 468
  • Page 469 469
  • Page 470 470
  • Page 471 471
  • Page 472 472
  • Page 473 473
  • Page 474 474
  • Page 475 475
  • Page 476 476
  • Page 477 477
  • Page 478 478
  • Page 479 479
  • Page 480 480
  • Page 481 481
  • Page 482 482
  • Page 483 483
  • Page 484 484
  • Page 485 485
  • Page 486 486
  • Page 487 487
  • Page 488 488
  • Page 489 489
  • Page 490 490
  • Page 491 491
  • Page 492 492
  • Page 493 493
  • Page 494 494
  • Page 495 495
  • Page 496 496
  • Page 497 497
  • Page 498 498
  • Page 499 499
  • Page 500 500
  • Page 501 501
  • Page 502 502
  • Page 503 503
  • Page 504 504
  • Page 505 505
  • Page 506 506
  • Page 507 507
  • Page 508 508
  • Page 509 509
  • Page 510 510
  • Page 511 511
  • Page 512 512
  • Page 513 513
  • Page 514 514
  • Page 515 515
  • Page 516 516
  • Page 517 517
  • Page 518 518
  • Page 519 519
  • Page 520 520
  • Page 521 521
  • Page 522 522
  • Page 523 523
  • Page 524 524
  • Page 525 525
  • Page 526 526
  • Page 527 527
  • Page 528 528
  • Page 529 529
  • Page 530 530
  • Page 531 531
  • Page 532 532
  • Page 533 533
  • Page 534 534
  • Page 535 535
  • Page 536 536
  • Page 537 537
  • Page 538 538
  • Page 539 539
  • Page 540 540
  • Page 541 541
  • Page 542 542
  • Page 543 543
  • Page 544 544
  • Page 545 545
  • Page 546 546
  • Page 547 547
  • Page 548 548
  • Page 549 549
  • Page 550 550
  • Page 551 551
  • Page 552 552
  • Page 553 553
  • Page 554 554
  • Page 555 555
  • Page 556 556
  • Page 557 557
  • Page 558 558
  • Page 559 559
  • Page 560 560
  • Page 561 561
  • Page 562 562
  • Page 563 563
  • Page 564 564
  • Page 565 565
  • Page 566 566
  • Page 567 567
  • Page 568 568
  • Page 569 569
  • Page 570 570
  • Page 571 571
  • Page 572 572
  • Page 573 573
  • Page 574 574
  • Page 575 575
  • Page 576 576
  • Page 577 577
  • Page 578 578
  • Page 579 579
  • Page 580 580
  • Page 581 581
  • Page 582 582
  • Page 583 583
  • Page 584 584
  • Page 585 585
  • Page 586 586
  • Page 587 587
  • Page 588 588
  • Page 589 589
  • Page 590 590
  • Page 591 591
  • Page 592 592
  • Page 593 593
  • Page 594 594
  • Page 595 595
  • Page 596 596
  • Page 597 597
  • Page 598 598
  • Page 599 599
  • Page 600 600
  • Page 601 601
  • Page 602 602
  • Page 603 603
  • Page 604 604
  • Page 605 605
  • Page 606 606
  • Page 607 607
  • Page 608 608
  • Page 609 609
  • Page 610 610
  • Page 611 611
  • Page 612 612
  • Page 613 613
  • Page 614 614
  • Page 615 615
  • Page 616 616
  • Page 617 617
  • Page 618 618
  • Page 619 619
  • Page 620 620
  • Page 621 621
  • Page 622 622
  • Page 623 623
  • Page 624 624
  • Page 625 625
  • Page 626 626
  • Page 627 627
  • Page 628 628
  • Page 629 629
  • Page 630 630
  • Page 631 631
  • Page 632 632
  • Page 633 633
  • Page 634 634
  • Page 635 635
  • Page 636 636
  • Page 637 637
  • Page 638 638
  • Page 639 639
  • Page 640 640
  • Page 641 641
  • Page 642 642
  • Page 643 643
  • Page 644 644
  • Page 645 645
  • Page 646 646
  • Page 647 647
  • Page 648 648
  • Page 649 649
  • Page 650 650
  • Page 651 651
  • Page 652 652
  • Page 653 653
  • Page 654 654
  • Page 655 655
  • Page 656 656
  • Page 657 657
  • Page 658 658
  • Page 659 659
  • Page 660 660
  • Page 661 661
  • Page 662 662
  • Page 663 663
  • Page 664 664
  • Page 665 665
  • Page 666 666
  • Page 667 667
  • Page 668 668
  • Page 669 669
  • Page 670 670
  • Page 671 671
  • Page 672 672
  • Page 673 673
  • Page 674 674
  • Page 675 675
  • Page 676 676
  • Page 677 677
  • Page 678 678
  • Page 679 679
  • Page 680 680
  • Page 681 681
  • Page 682 682
  • Page 683 683
  • Page 684 684
  • Page 685 685
  • Page 686 686
  • Page 687 687
  • Page 688 688
  • Page 689 689
  • Page 690 690
  • Page 691 691
  • Page 692 692
  • Page 693 693
  • Page 694 694
  • Page 695 695
  • Page 696 696
  • Page 697 697
  • Page 698 698
  • Page 699 699
  • Page 700 700
  • Page 701 701
  • Page 702 702
  • Page 703 703
  • Page 704 704
  • Page 705 705
  • Page 706 706
  • Page 707 707
  • Page 708 708
  • Page 709 709
  • Page 710 710
  • Page 711 711
  • Page 712 712
  • Page 713 713
  • Page 714 714
  • Page 715 715
  • Page 716 716
  • Page 717 717
  • Page 718 718
  • Page 719 719
  • Page 720 720
  • Page 721 721
  • Page 722 722
  • Page 723 723
  • Page 724 724
  • Page 725 725
  • Page 726 726
  • Page 727 727
  • Page 728 728
  • Page 729 729
  • Page 730 730
  • Page 731 731
  • Page 732 732
  • Page 733 733
  • Page 734 734
  • Page 735 735
  • Page 736 736
  • Page 737 737
  • Page 738 738
  • Page 739 739
  • Page 740 740
  • Page 741 741
  • Page 742 742
  • Page 743 743
  • Page 744 744
  • Page 745 745
  • Page 746 746
  • Page 747 747
  • Page 748 748
  • Page 749 749
  • Page 750 750
  • Page 751 751
  • Page 752 752
  • Page 753 753
  • Page 754 754
  • Page 755 755
  • Page 756 756
  • Page 757 757
  • Page 758 758
  • Page 759 759
  • Page 760 760
  • Page 761 761
  • Page 762 762
  • Page 763 763
  • Page 764 764
  • Page 765 765
  • Page 766 766
  • Page 767 767
  • Page 768 768
  • Page 769 769
  • Page 770 770
  • Page 771 771
  • Page 772 772
  • Page 773 773
  • Page 774 774
  • Page 775 775
  • Page 776 776
  • Page 777 777
  • Page 778 778
  • Page 779 779
  • Page 780 780
  • Page 781 781
  • Page 782 782
  • Page 783 783
  • Page 784 784
  • Page 785 785
  • Page 786 786
  • Page 787 787
  • Page 788 788
  • Page 789 789
  • Page 790 790
  • Page 791 791
  • Page 792 792
  • Page 793 793
  • Page 794 794
  • Page 795 795
  • Page 796 796
  • Page 797 797
  • Page 798 798
  • Page 799 799
  • Page 800 800
  • Page 801 801
  • Page 802 802
  • Page 803 803
  • Page 804 804
  • Page 805 805
  • Page 806 806
  • Page 807 807
  • Page 808 808
  • Page 809 809
  • Page 810 810
  • Page 811 811
  • Page 812 812
  • Page 813 813
  • Page 814 814
  • Page 815 815
  • Page 816 816
  • Page 817 817
  • Page 818 818
  • Page 819 819
  • Page 820 820
  • Page 821 821
  • Page 822 822
  • Page 823 823
  • Page 824 824
  • Page 825 825
  • Page 826 826
  • Page 827 827
  • Page 828 828
  • Page 829 829
  • Page 830 830
  • Page 831 831
  • Page 832 832
  • Page 833 833
  • Page 834 834
  • Page 835 835
  • Page 836 836
  • Page 837 837
  • Page 838 838
  • Page 839 839
  • Page 840 840
  • Page 841 841
  • Page 842 842
  • Page 843 843
  • Page 844 844
  • Page 845 845
  • Page 846 846
  • Page 847 847
  • Page 848 848
  • Page 849 849
  • Page 850 850
  • Page 851 851
  • Page 852 852
  • Page 853 853
  • Page 854 854
  • Page 855 855
  • Page 856 856
  • Page 857 857
  • Page 858 858
  • Page 859 859
  • Page 860 860
  • Page 861 861
  • Page 862 862
  • Page 863 863
  • Page 864 864
  • Page 865 865
  • Page 866 866
  • Page 867 867
  • Page 868 868
  • Page 869 869
  • Page 870 870
  • Page 871 871
  • Page 872 872
  • Page 873 873
  • Page 874 874
  • Page 875 875
  • Page 876 876
  • Page 877 877
  • Page 878 878
  • Page 879 879
  • Page 880 880
  • Page 881 881
  • Page 882 882
  • Page 883 883
  • Page 884 884
  • Page 885 885
  • Page 886 886
  • Page 887 887
  • Page 888 888
  • Page 889 889
  • Page 890 890
  • Page 891 891
  • Page 892 892
  • Page 893 893
  • Page 894 894
  • Page 895 895
  • Page 896 896
  • Page 897 897
  • Page 898 898
  • Page 899 899
  • Page 900 900
  • Page 901 901
  • Page 902 902
  • Page 903 903
  • Page 904 904
  • Page 905 905
  • Page 906 906
  • Page 907 907
  • Page 908 908
  • Page 909 909
  • Page 910 910
  • Page 911 911
  • Page 912 912
  • Page 913 913
  • Page 914 914
  • Page 915 915
  • Page 916 916
  • Page 917 917
  • Page 918 918
  • Page 919 919
  • Page 920 920
  • Page 921 921
  • Page 922 922
  • Page 923 923
  • Page 924 924
  • Page 925 925
  • Page 926 926
  • Page 927 927
  • Page 928 928
  • Page 929 929
  • Page 930 930
  • Page 931 931
  • Page 932 932
  • Page 933 933
  • Page 934 934
  • Page 935 935
  • Page 936 936
  • Page 937 937
  • Page 938 938
  • Page 939 939
  • Page 940 940
  • Page 941 941
  • Page 942 942
  • Page 943 943
  • Page 944 944
  • Page 945 945
  • Page 946 946
  • Page 947 947
  • Page 948 948
  • Page 949 949
  • Page 950 950
  • Page 951 951
  • Page 952 952
  • Page 953 953
  • Page 954 954
  • Page 955 955
  • Page 956 956
  • Page 957 957
  • Page 958 958
  • Page 959 959
  • Page 960 960
  • Page 961 961
  • Page 962 962
  • Page 963 963
  • Page 964 964
  • Page 965 965
  • Page 966 966
  • Page 967 967
  • Page 968 968
  • Page 969 969
  • Page 970 970
  • Page 971 971
  • Page 972 972
  • Page 973 973
  • Page 974 974
  • Page 975 975
  • Page 976 976
  • Page 977 977
  • Page 978 978
  • Page 979 979
  • Page 980 980
  • Page 981 981
  • Page 982 982
  • Page 983 983
  • Page 984 984
  • Page 985 985
  • Page 986 986
  • Page 987 987
  • Page 988 988
  • Page 989 989
  • Page 990 990
  • Page 991 991
  • Page 992 992
  • Page 993 993
  • Page 994 994
  • Page 995 995
  • Page 996 996
  • Page 997 997
  • Page 998 998
  • Page 999 999
  • Page 1000 1000
  • Page 1001 1001
  • Page 1002 1002
  • Page 1003 1003
  • Page 1004 1004
  • Page 1005 1005
  • Page 1006 1006
  • Page 1007 1007
  • Page 1008 1008
  • Page 1009 1009
  • Page 1010 1010
  • Page 1011 1011
  • Page 1012 1012
  • Page 1013 1013
  • Page 1014 1014
  • Page 1015 1015
  • Page 1016 1016
  • Page 1017 1017
  • Page 1018 1018
  • Page 1019 1019
  • Page 1020 1020
  • Page 1021 1021
  • Page 1022 1022
  • Page 1023 1023
  • Page 1024 1024
  • Page 1025 1025
  • Page 1026 1026
  • Page 1027 1027
  • Page 1028 1028
  • Page 1029 1029
  • Page 1030 1030
  • Page 1031 1031
  • Page 1032 1032
  • Page 1033 1033
  • Page 1034 1034
  • Page 1035 1035
  • Page 1036 1036
  • Page 1037 1037
  • Page 1038 1038
  • Page 1039 1039
  • Page 1040 1040
  • Page 1041 1041
  • Page 1042 1042
  • Page 1043 1043
  • Page 1044 1044
  • Page 1045 1045
  • Page 1046 1046
  • Page 1047 1047
  • Page 1048 1048
  • Page 1049 1049
  • Page 1050 1050
  • Page 1051 1051
  • Page 1052 1052
  • Page 1053 1053
  • Page 1054 1054
  • Page 1055 1055
  • Page 1056 1056
  • Page 1057 1057
  • Page 1058 1058
  • Page 1059 1059
  • Page 1060 1060
  • Page 1061 1061
  • Page 1062 1062
  • Page 1063 1063
  • Page 1064 1064
  • Page 1065 1065
  • Page 1066 1066
  • Page 1067 1067
  • Page 1068 1068
  • Page 1069 1069
  • Page 1070 1070
  • Page 1071 1071
  • Page 1072 1072
  • Page 1073 1073
  • Page 1074 1074
  • Page 1075 1075
  • Page 1076 1076
  • Page 1077 1077
  • Page 1078 1078
  • Page 1079 1079
  • Page 1080 1080
  • Page 1081 1081
  • Page 1082 1082
  • Page 1083 1083
  • Page 1084 1084
  • Page 1085 1085
  • Page 1086 1086
  • Page 1087 1087
  • Page 1088 1088
  • Page 1089 1089
  • Page 1090 1090
  • Page 1091 1091
  • Page 1092 1092
  • Page 1093 1093
  • Page 1094 1094
  • Page 1095 1095
  • Page 1096 1096
  • Page 1097 1097
  • Page 1098 1098
  • Page 1099 1099
  • Page 1100 1100
  • Page 1101 1101
  • Page 1102 1102
  • Page 1103 1103
  • Page 1104 1104
  • Page 1105 1105
  • Page 1106 1106
  • Page 1107 1107
  • Page 1108 1108
  • Page 1109 1109
  • Page 1110 1110
  • Page 1111 1111
  • Page 1112 1112
  • Page 1113 1113
  • Page 1114 1114
  • Page 1115 1115
  • Page 1116 1116
  • Page 1117 1117
  • Page 1118 1118
  • Page 1119 1119
  • Page 1120 1120
  • Page 1121 1121
  • Page 1122 1122
  • Page 1123 1123
  • Page 1124 1124
  • Page 1125 1125
  • Page 1126 1126
  • Page 1127 1127
  • Page 1128 1128
  • Page 1129 1129
  • Page 1130 1130
  • Page 1131 1131
  • Page 1132 1132
  • Page 1133 1133
  • Page 1134 1134
  • Page 1135 1135
  • Page 1136 1136
  • Page 1137 1137
  • Page 1138 1138
  • Page 1139 1139
  • Page 1140 1140
  • Page 1141 1141
  • Page 1142 1142
  • Page 1143 1143
  • Page 1144 1144
  • Page 1145 1145
  • Page 1146 1146
  • Page 1147 1147
  • Page 1148 1148
  • Page 1149 1149
  • Page 1150 1150
  • Page 1151 1151
  • Page 1152 1152
  • Page 1153 1153
  • Page 1154 1154
  • Page 1155 1155
  • Page 1156 1156
  • Page 1157 1157
  • Page 1158 1158
  • Page 1159 1159
  • Page 1160 1160
  • Page 1161 1161
  • Page 1162 1162
  • Page 1163 1163
  • Page 1164 1164
  • Page 1165 1165
  • Page 1166 1166
  • Page 1167 1167
  • Page 1168 1168
  • Page 1169 1169
  • Page 1170 1170
  • Page 1171 1171
  • Page 1172 1172
  • Page 1173 1173
  • Page 1174 1174
  • Page 1175 1175
  • Page 1176 1176
  • Page 1177 1177
  • Page 1178 1178
  • Page 1179 1179
  • Page 1180 1180
  • Page 1181 1181
  • Page 1182 1182
  • Page 1183 1183
  • Page 1184 1184
  • Page 1185 1185
  • Page 1186 1186
  • Page 1187 1187
  • Page 1188 1188
  • Page 1189 1189
  • Page 1190 1190
  • Page 1191 1191
  • Page 1192 1192
  • Page 1193 1193
  • Page 1194 1194
  • Page 1195 1195
  • Page 1196 1196
  • Page 1197 1197
  • Page 1198 1198
  • Page 1199 1199
  • Page 1200 1200
  • Page 1201 1201
  • Page 1202 1202
  • Page 1203 1203
  • Page 1204 1204
  • Page 1205 1205
  • Page 1206 1206
  • Page 1207 1207
  • Page 1208 1208
  • Page 1209 1209
  • Page 1210 1210
  • Page 1211 1211
  • Page 1212 1212
  • Page 1213 1213
  • Page 1214 1214
  • Page 1215 1215
  • Page 1216 1216
  • Page 1217 1217
  • Page 1218 1218
  • Page 1219 1219
  • Page 1220 1220
  • Page 1221 1221
  • Page 1222 1222
  • Page 1223 1223
  • Page 1224 1224
  • Page 1225 1225
  • Page 1226 1226
  • Page 1227 1227
  • Page 1228 1228
  • Page 1229 1229
  • Page 1230 1230
  • Page 1231 1231
  • Page 1232 1232
  • Page 1233 1233
  • Page 1234 1234
  • Page 1235 1235
  • Page 1236 1236
  • Page 1237 1237
  • Page 1238 1238
  • Page 1239 1239
  • Page 1240 1240
  • Page 1241 1241
  • Page 1242 1242
  • Page 1243 1243
  • Page 1244 1244
  • Page 1245 1245
  • Page 1246 1246
  • Page 1247 1247
  • Page 1248 1248
  • Page 1249 1249
  • Page 1250 1250
  • Page 1251 1251
  • Page 1252 1252
  • Page 1253 1253
  • Page 1254 1254
  • Page 1255 1255
  • Page 1256 1256
  • Page 1257 1257
  • Page 1258 1258
  • Page 1259 1259
  • Page 1260 1260
  • Page 1261 1261
  • Page 1262 1262
  • Page 1263 1263
  • Page 1264 1264
  • Page 1265 1265
  • Page 1266 1266
  • Page 1267 1267
  • Page 1268 1268
  • Page 1269 1269
  • Page 1270 1270
  • Page 1271 1271
  • Page 1272 1272
  • Page 1273 1273
  • Page 1274 1274
  • Page 1275 1275
  • Page 1276 1276
  • Page 1277 1277
  • Page 1278 1278
  • Page 1279 1279
  • Page 1280 1280
  • Page 1281 1281
  • Page 1282 1282
  • Page 1283 1283
  • Page 1284 1284
  • Page 1285 1285
  • Page 1286 1286
  • Page 1287 1287
  • Page 1288 1288
  • Page 1289 1289
  • Page 1290 1290
  • Page 1291 1291
  • Page 1292 1292
  • Page 1293 1293
  • Page 1294 1294
  • Page 1295 1295
  • Page 1296 1296
  • Page 1297 1297
  • Page 1298 1298
  • Page 1299 1299
  • Page 1300 1300
  • Page 1301 1301
  • Page 1302 1302
  • Page 1303 1303
  • Page 1304 1304
  • Page 1305 1305
  • Page 1306 1306
  • Page 1307 1307
  • Page 1308 1308
  • Page 1309 1309
  • Page 1310 1310
  • Page 1311 1311
  • Page 1312 1312
  • Page 1313 1313
  • Page 1314 1314
  • Page 1315 1315
  • Page 1316 1316
  • Page 1317 1317
  • Page 1318 1318
  • Page 1319 1319
  • Page 1320 1320
  • Page 1321 1321
  • Page 1322 1322
  • Page 1323 1323
  • Page 1324 1324
  • Page 1325 1325
  • Page 1326 1326
  • Page 1327 1327
  • Page 1328 1328
  • Page 1329 1329
  • Page 1330 1330
  • Page 1331 1331
  • Page 1332 1332
  • Page 1333 1333
  • Page 1334 1334
  • Page 1335 1335
  • Page 1336 1336
  • Page 1337 1337
  • Page 1338 1338
  • Page 1339 1339
  • Page 1340 1340
  • Page 1341 1341
  • Page 1342 1342
  • Page 1343 1343
  • Page 1344 1344
  • Page 1345 1345
  • Page 1346 1346
  • Page 1347 1347
  • Page 1348 1348
  • Page 1349 1349
  • Page 1350 1350
  • Page 1351 1351
  • Page 1352 1352
  • Page 1353 1353
  • Page 1354 1354
  • Page 1355 1355
  • Page 1356 1356
  • Page 1357 1357
  • Page 1358 1358
  • Page 1359 1359
  • Page 1360 1360
  • Page 1361 1361
  • Page 1362 1362
  • Page 1363 1363
  • Page 1364 1364
  • Page 1365 1365
  • Page 1366 1366
  • Page 1367 1367
  • Page 1368 1368
  • Page 1369 1369
  • Page 1370 1370
  • Page 1371 1371
  • Page 1372 1372
  • Page 1373 1373
  • Page 1374 1374
  • Page 1375 1375
  • Page 1376 1376
  • Page 1377 1377
  • Page 1378 1378
  • Page 1379 1379
  • Page 1380 1380
  • Page 1381 1381
  • Page 1382 1382
  • Page 1383 1383
  • Page 1384 1384
  • Page 1385 1385
  • Page 1386 1386
  • Page 1387 1387
  • Page 1388 1388
  • Page 1389 1389
  • Page 1390 1390
  • Page 1391 1391
  • Page 1392 1392
  • Page 1393 1393
  • Page 1394 1394
  • Page 1395 1395
  • Page 1396 1396
  • Page 1397 1397
  • Page 1398 1398
  • Page 1399 1399
  • Page 1400 1400
  • Page 1401 1401
  • Page 1402 1402
  • Page 1403 1403
  • Page 1404 1404
  • Page 1405 1405
  • Page 1406 1406
  • Page 1407 1407
  • Page 1408 1408
  • Page 1409 1409
  • Page 1410 1410
  • Page 1411 1411
  • Page 1412 1412
  • Page 1413 1413
  • Page 1414 1414
  • Page 1415 1415
  • Page 1416 1416
  • Page 1417 1417
  • Page 1418 1418
  • Page 1419 1419
  • Page 1420 1420
  • Page 1421 1421
  • Page 1422 1422
  • Page 1423 1423
  • Page 1424 1424
  • Page 1425 1425
  • Page 1426 1426
  • Page 1427 1427
  • Page 1428 1428
  • Page 1429 1429
  • Page 1430 1430
  • Page 1431 1431
  • Page 1432 1432
  • Page 1433 1433
  • Page 1434 1434
  • Page 1435 1435
  • Page 1436 1436
  • Page 1437 1437
  • Page 1438 1438
  • Page 1439 1439
  • Page 1440 1440
  • Page 1441 1441
  • Page 1442 1442
  • Page 1443 1443
  • Page 1444 1444
  • Page 1445 1445
  • Page 1446 1446
  • Page 1447 1447
  • Page 1448 1448
  • Page 1449 1449
  • Page 1450 1450
  • Page 1451 1451
  • Page 1452 1452
  • Page 1453 1453
  • Page 1454 1454
  • Page 1455 1455
  • Page 1456 1456
  • Page 1457 1457
  • Page 1458 1458
  • Page 1459 1459
  • Page 1460 1460
  • Page 1461 1461
  • Page 1462 1462
  • Page 1463 1463
  • Page 1464 1464
  • Page 1465 1465
  • Page 1466 1466
  • Page 1467 1467
  • Page 1468 1468
  • Page 1469 1469
  • Page 1470 1470
  • Page 1471 1471
  • Page 1472 1472
  • Page 1473 1473
  • Page 1474 1474
  • Page 1475 1475
  • Page 1476 1476
  • Page 1477 1477
  • Page 1478 1478
  • Page 1479 1479
  • Page 1480 1480
  • Page 1481 1481
  • Page 1482 1482
  • Page 1483 1483
  • Page 1484 1484
  • Page 1485 1485
  • Page 1486 1486
  • Page 1487 1487
  • Page 1488 1488
  • Page 1489 1489
  • Page 1490 1490
  • Page 1491 1491
  • Page 1492 1492
  • Page 1493 1493
  • Page 1494 1494
  • Page 1495 1495
  • Page 1496 1496
  • Page 1497 1497
  • Page 1498 1498
  • Page 1499 1499
  • Page 1500 1500
  • Page 1501 1501
  • Page 1502 1502
  • Page 1503 1503
  • Page 1504 1504
  • Page 1505 1505
  • Page 1506 1506
  • Page 1507 1507
  • Page 1508 1508
  • Page 1509 1509
  • Page 1510 1510
  • Page 1511 1511
  • Page 1512 1512
  • Page 1513 1513
  • Page 1514 1514
  • Page 1515 1515
  • Page 1516 1516
  • Page 1517 1517
  • Page 1518 1518
  • Page 1519 1519
  • Page 1520 1520
  • Page 1521 1521
  • Page 1522 1522
  • Page 1523 1523
  • Page 1524 1524
  • Page 1525 1525
  • Page 1526 1526
  • Page 1527 1527
  • Page 1528 1528
  • Page 1529 1529
  • Page 1530 1530
  • Page 1531 1531
  • Page 1532 1532
  • Page 1533 1533
  • Page 1534 1534
  • Page 1535 1535
  • Page 1536 1536
  • Page 1537 1537
  • Page 1538 1538
  • Page 1539 1539
  • Page 1540 1540
  • Page 1541 1541
  • Page 1542 1542
  • Page 1543 1543
  • Page 1544 1544
  • Page 1545 1545
  • Page 1546 1546
  • Page 1547 1547
  • Page 1548 1548
  • Page 1549 1549
  • Page 1550 1550
  • Page 1551 1551
  • Page 1552 1552
  • Page 1553 1553
  • Page 1554 1554
  • Page 1555 1555
  • Page 1556 1556
  • Page 1557 1557
  • Page 1558 1558
  • Page 1559 1559
  • Page 1560 1560
  • Page 1561 1561
  • Page 1562 1562
  • Page 1563 1563
  • Page 1564 1564
  • Page 1565 1565
  • Page 1566 1566
  • Page 1567 1567

NXP K10_100 Reference guide

Type
Reference guide

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI