Texas Instruments 24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo DAC (Rev. B) Datasheet



SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

    

   

FEATURES

D 24-Bit Resolution

D Analog Performance:

− Dynamic Range:

− 132 dB (9 V rms, Mono)

− 129 dB (4.5 V rms, Stereo)

− 127 dB (2 V rms, Stereo)

− THD+N: 0.0004%

D Differential Current Output: 7.8 mA p-p

D 8× Oversampling Digital Filter:

− Stop-Band Attenuation: –130 dB

− Pass-Band Ripple: ±0.00001 dB

D Sampling Frequency: 10 kHz to 200 kHz

D System Clock: 128, 192, 256, 384, 512, or

768 f

S

With Autodetect

D Accepts 16-, 20-, and 24-Bit Audio Data

D PCM Data Formats: Standard, I

2

S, and

Left-Justified

D DSD Format Interface Available

D Optional Interface to External Digital Filter or

DSP Available

D TDMCA or Serial Port (SPI/I

2

C)

D User-Programmable Mode Controls:

− Digital Attenuation: 0 dB to –120 dB,

0.5 dB/Step

− Digital De-Emphasis

− Digital Filter Rolloff: Sharp or Slow

− Soft Mute

− Zero Flag for Each Output

D Dual Supply Operation:

− 5-V Analog, 3.3-V Digital

D 5-V Tolerant Digital Inputs

D Small 28-Lead SSOP Package

APPLICATIONS

D A/V Receivers

D SACD Player

D DVD Players

D HDTV Receivers

D Car Audio Systems

D Digital Multitrack Recorders

D Other Applications Requiring 24-Bit Audio

DESCRIPTION

The PCM1792A is a monolithic CMOS integrated circuit

that includes stereo digital-to-analog converters and

support circuitry in a small 28-lead SSOP package. The

data converters use TI’s advanced segment DAC

architecture to achieve excellent dynamic performance

and improved tolerance to clock jitter. The PCM1792A

provides balanced current outputs, allowing the user to

optimize analog performance externally. The PCM1792A

accepts PCM and DSD audio data formats, providing easy

interfacing to audio DSP and decoder chips. The

PCM1792A also interfaces with external digital filter

devices (DF1704, DF1706, PMD200). Sampling rates up

to 200 kHz are supported. A full set of user-programmable

functions is accessible through an SPI or I

2

C serial control

port, which supports register write and readback functions.

The PCM1792A also supports the time division

multiplexed command and audio (TDMCA) data format.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

  !"#$ % &'!!($ #%  )'*+&#$ ,#$(- !,'&$%

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

'!!!0 !,'&$%

!" (/#% %$!'"($%

Copyright  2006, Texas Instruments Incorporated



SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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2

ORDERING INFORMATION

PRODUCT PACKAGE PACKAGE CODE

OPERATION

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PCM1792ADB

28-lead SSOP

28DB

−25°C to 85°C

PCM1792A

PCM1792ADB Tube

PCM1792ADB

28-lead SSOP

28DB

−25

°

C to 85

°

C

PCM1792A

PCM1792ADBR Tape and reel

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

PCM1792A

Supply voltage

V

CC

1, V

CC

2L, V

CC

2R −0.3 V to 6.5 V

Supply voltage

V

DD

−0.3 V to 4 V

Supply voltage differences: V

CC

1, V

CC

2L and V

CC

2R ±0.1 V

Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, and DGND ±0.1 V

Digital input

LRCK, DATA, BCK, SCK, MSEL, RST, MS

(2)

, MDI, MC, MDO

(2)

, ZEROL

(2)

, ZEROR

(2)

–0.3 V to 6.5 V

Digital input

voltage

ZEROL

(3)

, ZEROR

(3)

, MDO

(3)

, MS

(3)

–0.3 V to (V

DD

+ 0.3 V) < 4 V

Analog input voltage –0.3 V to (V

CC

+ 0.3 V) < 6.5 V

Input current (any pins except supplies) ±10 mA

Ambient temperature under bias –40°C to 125°C

Storage temperature –55°C to 150°C

Junction temperature 150°C

Lead temperature (soldering) 260°C, 5 s

Package temperature (IR reflow, peak) 250°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Input mode or I

2

C mode.

(3)

Output mode except for I

2

C mode.

ELECTRICAL CHARACTERISTICS

all specifications at T

A

= 25°C, V

CC

1 = V

CC

2L = V

CC

2R = 5 V, f

S

= 44.1 kHz, system clock = 256 f

S

, and 24-bit data unless otherwise noted

PARAMETER

TEST CONDITIONS

PCM1792ADB

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

RESOLUTION 24 Bits

DATA FORMAT (PCM Mode)

Audio data interface format Standard, I

2

S, left justified

Audio data bit length 16-, 20-, 24-bit selectable

Audio data format MSB first, 2s complement

f

S

Sampling frequency 10 200 kHz

System clock frequency 128, 192, 256, 384, 512, 768 f

S

DATA FORMAT (DSD Mode)

Audio data interface format DSD (direct stream digital)

Audio data bit length 1 Bit

f

S

Sampling frequency 2.8224 MHz

System clock frequency 2.8224 11.2896 MHz

DIGITAL INPUT/OUTPUT

Logic family TTL compatible

V

IH

Input logic level

2

Vdc

V

IL

Input logic level

0.8

Vdc

I

IH

Input logic current

V

IN

= V

DD

10

µA

I

IL

Input logic current

V

IN

= 0 V –10

µ

A

V

OH

Output logic level

I

OH

= −2 mA 2.4

Vdc

V

OL

Output logic level

I

OL

= 2 mA 0.4

Vdc

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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3

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T

A

= 25°C, V

CC

1 = V

CC

2L = V

CC

2R = 5 V, f

S

= 44.1 kHz, system clock = 256 f

S

, and 24-bit data unless otherwise noted

PARAMETER

TEST CONDITIONS

PCM1792ADB

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

DYNAMIC PERFORMANCE (PCM MODE, 2-V RMS OUTPUT)

(1)(2)

f

S

= 44.1 kHz 0.0004% 0.0008%

THD+N at V

OUT

= 0 dB

f

S

= 96 kHz 0.0008%

THD+N at V

OUT

= 0 dB

f

S

= 192 kHz 0.0015%

EIAJ, A-weighted, f

S

= 44.1 kHz 123 127

Dynamic range

EIAJ, A-weighted, f

S

= 96 kHz 127

dB

Dynamic range

EIAJ, A-weighted, f

S

= 192 kHz 127

dB

EIAJ, A-weighted, f

S

= 44.1 kHz 123 127

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 96 kHz 127

dB

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 192 kHz 127

dB

f

S

= 44.1 kHz 120 123

Channel separation

f

S

= 96 kHz 122

dB

Channel separation

f

S

= 192 kHz 120

dB

Level Linearity Error V

OUT

= −120 dB ±1 dB

DYNAMIC PERFORMANCE (PCM Mode, 4.5-V RMS Output)

(1)(3)

f

S

= 44.1 kHz 0.0004%

THD+N at V

OUT

= 0 dB

f

S

= 96 kHz 0.0008%

THD+N at V

OUT

= 0 dB

f

S

= 192 kHz 0.0015%

EIAJ, A-weighted, f

S

= 44.1 kHz 129

Dynamic range

EIAJ, A-weighted, f

S

= 96 kHz 129

dB

Dynamic range

EIAJ, A-weighted, f

S

= 192 kHz 129

dB

EIAJ, A-weighted, f

S

= 44.1 kHz 129

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 96 kHz 129

dB

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 192 kHz 129

dB

f

S

= 44.1 kHz 124

Channel separation

f

S

= 96 kHz 123

dB

Channel separation

f

S

= 192 kHz 121

dB

DYNAMIC PERFORMANCE (MONO MODE)

(1)(3)

f

S

= 44.1 kHz 0.0004%

THD+N at V

OUT

= 0 dB

f

S

= 96 kHz 0.0008%

THD+N at V

OUT

= 0 dB

f

S

= 192 kHz 0.0015%

EIAJ, A-weighted, f

S

= 44.1 kHz 132

Dynamic range

EIAJ, A-weighted, f

S

= 96 kHz 132

dB

Dynamic range

EIAJ, A-weighted, f

S

= 192 kHz 132

dB

EIAJ, A-weighted, f

S

= 44.1 kHz 132

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 96 kHz 132

dB

Signal-to-noise ratio

EIAJ, A-weighted, f

S

= 192 kHz 132

dB

(1)

Filter condition:

THD+N: 20-Hz HPF, 20-kHz apogee LPF

Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Channel separation: 20-Hz HPF, 20-kHz AES17 LPF

Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the

averaging mode.

(2)

Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 36.

(3)

Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 37.

Audio Precision and System Two are trademarks of Audio Precision, Inc.

Other trademarks are the property of their respective owners.

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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4

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T

A

= 25°C, V

CC

1 = V

CC

2L = V

CC

2R = 5 V, f

S

= 44.1 kHz, system clock = 256 f

S

, and 24-bit data unless otherwise noted

PARAMETER

TEST CONDITIONS

PCM1792ADB

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

DSD MODE DYNAMIC PERFORMANCE

(1)

(2)

(44.1 kHz, 64 f

S

)

THD+N at FS 4.5 V rms 0.0005%

Dynamic range –60 dB, EIAJ, A-weighted 128 dB

Signal-to-noise ratio EIAJ, A-weighted 128 dB

ANALOG OUTPUT

Gain error –6 ±2 6 % of FSR

Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR

Bipolar zero error At BPZ –2 ±0.5 2 % of FSR

Output current Full scale (0 dB) 7.8 mA p-p

Center current At BPZ –6.2 mA

DIGITAL FILTER PERFORMANCE

De-emphasis error ±0.004 dB

FILTER CHARACTERISTICS–1: SHARP ROLLOFF

Pass band

±0.00001 dB 0.454 f

S

Pass band

–3 dB 0.49 f

S

Stop band 0.546 f

S

Pass-band ripple ±0.00001 dB

Stop-band attenuation Stop band = 0.546 f

S

–130 dB

Delay time 55/f

S

s

FILTER CHARACTERISTICS–2: SLOW ROLLOFF

Pass band

±0.04 dB 0.254 f

S

Pass band

–3 dB 0.46 f

S

Stop band 0.732 f

S

Pass-band ripple ±0.001 dB

Stop-band attenuation Stop band = 0.732 f

S

–100 dB

Delay time 18/f

S

s

(1)

Filter condition:

THD+N: 20-Hz HPF, 20-kHz apogee LPF

Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Channel separation: 20-Hz HPF, 20-kHz AES17 LPF

Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging

mode.

(2)

Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 38.



SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

www.ti.com

5

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T

A

= 25°C, V

CC

1 = V

CC

2L = V

CC

2R = 5 V, f

S

= 44.1 kHz, system clock = 256 f

S

, and 24-bit data unless otherwise noted

PARAMETER

TEST CONDITIONS

PCM1792ADB

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

POWER SUPPLY REQUIREMENTS

V

DD

3 3.3 3.6 Vdc

V

CC

1

Voltage range

V

CC

2L

Voltage range

4.75 5 5.25 Vdc

V

CC

2R

(1)

f

S

= 44.1 kHz 12 15

I

DD

Supply current

(1)

f

S

= 96 kHz 23

mA

I

DD

Supply current

(1)

f

S

= 192 kHz 45

mA

(1)

f

S

= 44.1 kHz 33 40

I

CC

Supply current

(1)

f

S

= 96 kHz 35

mA

I

CC

Supply current

(1)

f

S

= 192 kHz 37

mA

(1)

f

S

= 44.1 kHz 205 250

Power dissipation

(1)

f

S

= 96 kHz 250

mW

Power dissipation

(1)

f

S

= 192 kHz 335

mW

TEMPERATURE RANGE

Operation temperature –25 85 °C

θ

JA

Thermal resistance 28-pin SSOP 100 °C/W

(1)

Input is BPZ data.

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ZEROL

ZEROR

MSEL

LRCK

DATA

BCK

SCK

DGND

V

DD

MS

MDI

MC

MDO

RST

V

CC

2L

AGND3L

I

OUT

L−

I

OUT

L+

AGND2

V

CC

1

V

COM

L

V

COM

R

I

REF

AGND1

I

OUT

R−

I

OUT

R+

AGND3R

V

CC

2R

PCM1792A

(TOP VIEW)

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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6

Terminal Functions

TERMINAL

I/O

DESCRIPTIONS

NAME PIN

I/O

DESCRIPTIONS

AGND1 19 − Analog ground (internal bias)

AGND2 24 − Analog ground (internal bias)

AGND3L 27 − Analog ground (L-channel DACFF)

AGND3R 16 − Analog ground (R-channel DACFF)

BCK 6 I Bit clock input

(1)

DATA 5 I Serial audio data input for normal operation

(1)

DGND 8 − Digital ground

I

OUT

L+ 25 O L-channel analog current output+

I

OUT

L– 26 O L-channel analog current output–

I

OUT

R+ 17 O R-channel analog current output+

I

OUT

R– 18 O R-channel analog current output–

I

REF

20 − Output current reference bias pin

LRCK 4 I Left and right clock (f

S

) input for normal operation

(1)

MC 12 I Mode control clock input

(1)

MDI 11 I Mode control data input

(1)

MDO 13 I/O Mode control readback data output

(3)

MS 10 I/O Mode control chip-select input

(2)

MSEL 3 I I

2

C/SPI select

(1)

RST 14 I Reset

(1)

SCK 7 I System clock input

(1)

V

CC

1 23 − Analog power supply, 5 V

V

CC

2L 28 − Analog power supply (L-channel DACFF), 5 V

V

CC

2R 15 − Analog power supply (R-channel DACFF), 5 V

V

COM

L 22 − L-channel internal bias decoupling pin

V

COM

R 21 − R-channel internal bias decoupling pin

V

DD

9 − Digital power supply, 3.3 V

ZEROL 1 I/O Zero flag for L-channel

(2)

ZEROR 2 I/O Zero flag for R-channel

(2)

(1)

Schmitt-trigger input, 5-V tolerant

(2)

Schmitt-trigger input and output. 5-V tolerant input and CMOS output

(3)

Schmitt-trigger input and output. 5-V tolerant input. In I

2

C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS

output.

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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7

FUNCTIONAL BLOCK DIAGRAM

Power Supply

RST

SCK

Advanced

Segment

DAC

Modulator

I

OUT

L+

I

OUT

L−

I

OUT

R−

Current

Segment

DAC

I

OUT

R+

Bias

and

Vref

V

COM

L

V

COM

R

AGND2

V

DD

V

CC

1

V

CC

2L

V

CC

2R

AGND1

I/V and Filter

8

Oversampling

Digital

Filter

and

Function

Control

Audio

Data Input

I/F

LRCK

BCK

DATA

MDO

MDI

MC

MS

AGND3L

AGND3R

DGND

Current

Segment

DAC

I

REF

V

OUT

L

I/V and Filter

V

OUT

R

Function

Control

I/F

MSEL

Zero

Detect

ZEROL

ZEROR

System

Clock

Manager

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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8

TYPICAL PERFORMANCE CURVES

DIGITAL FILTER

Digital Filter Response

Figure 1. Frequency Response, Sharp Rolloff

Frequency [× f

S

]

−200

−150

−100

−50

0

01234

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

Figure 2. Pass-Band Ripple, Sharp Rolloff

Frequency [× f

S

]

−2

−1

0

1

2

0.0 0.1 0.2 0.3 0.4 0.5

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

0.00002

0

−0.00001

−0.00002

0.00001

Figure 3. Frequency Response, Slow Rolloff

Frequency [× f

S

]

−200

−150

−100

−50

0

01234

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

Figure 4. Transition Characteristics, Slow Rolloff

Frequency [× f

S

]

−20

−18

−16

−14

−12

−10

−8

−6

−4

−2

0

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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9

De-Emphasis Filter

Figure 5

f − Frequency − kHz

−10

−8

−6

−4

−2

0

0 2 4 6 8 10 12 14

De-Emphasis Level − dB

DE-EMPHASIS LEVEL

vs

FREQUENCY

f

S

= 32 kHz

Figure 6

f − Frequency − kHz

−20

−15

−10

−5

0

5

10

15

20

0 2 4 6 8 10 12 14

DE-EMPHASIS ERROR

vs

FREQUENCY

0

−0.015

−0.020

0.015

f

S

= 32 kHz

0.010

0.005

−0.010

−0.005

De-Emphasis Error − dB

Figure 7

f − Frequency − kHz

−10

−8

−6

−4

−2

0

0 2 4 6 8 101214161820

De-Emphasis Level − dB

DE-EMPHASIS LEVEL

vs

FREQUENCY

f

S

= 44.1 kHz

Figure 8

f − Frequency − kHz

−20

−15

−10

−5

0

5

10

15

20

0 2 4 6 8 101214161820

DE-EMPHASIS ERROR

vs

FREQUENCY

0.020

0

−0.015

−0.020

0.015

f

S

= 44.1 kHz

0.010

0.005

−0.010

−0.005

De-Emphasis Error − dB

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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10

De-Emphasis Filter (Continued)

Figure 9

f − Frequency − kHz

−10

−8

−6

−4

−2

0

0 2 4 6 8 10121416182022

De-Emphasis Level − dB

DE-EMPHASIS LEVEL

vs

FREQUENCY

f

S

= 48 kHz

Figure 10

f − Frequency − kHz

−20

−15

−10

−5

0

5

10

15

20

0 2 4 6 8 10121416182022

DE-EMPHASIS ERROR

vs

FREQUENCY

0.020

0

−0.015

−0.020

0.015

f

S

= 48 kHz

0.010

0.005

−0.010

−0.005

De-Emphasis Error − dB

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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11

ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

Figure 11

4.50 4.75 5.00 5.25 5.50

V

CC

− Supply Voltage − V

TOTAL HARMONIC DISTORTION + NOISE

vs

SUPPLY VOLTAGE

0.01

0.001

0.0001

f

S

= 192 kHz

f

S

= 96 kHz

THD+N − Total Harmonic Distortion + Noise − %

f

S

= 48 kHz

Figure 12

V

CC

− Supply Voltage − V

122

124

126

128

130

132

4.50 4.75 5.00 5.25 5.50

Dynamic Range − dB

DYNAMIC RANGE

vs

SUPPLY VOLTAGE

f

S

= 96 kHz

f

S

= 48 kHz

f

S

= 192 kHz

Figure 13

V

CC

− Supply Voltage − V

122

124

126

128

130

132

4.50 4.75 5.00 5.25 5.50

SNR − Signal-to-Noise Ratio − dB

SIGNAL-to-NOISE RATIO

vs

SUPPLY VOLTAGE

f

S

= 96 kHz

f

S

= 192 kHz

f

S

= 48 kHz

Figure 14

V

CC

− Supply Voltage − V

120

122

124

126

128

130

4.50 4.75 5.00 5.25 5.50

Channel Separation − dB

CHANNEL SEPARATION

vs

SUPPLY VOLTAGE

f

S

= 96 kHz

f

S

= 192 kHz

f

S

= 48 kHz

NOTE: PCM mode, T

A

= 25°C, V

DD

= 3.3 V, measurement circuit is Figure 37 (V

OUT

= 4.5 V rms).

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12

Temperature Characteristics

Figure 15

−50 −25 0 25 50 75 100

TOTAL HARMONIC DISTORTION + NOISE

vs

FREE-AIR TEMPERATURE

0.01

0.001

0.0001

f

S

= 192 kHz

f

S

= 96 kHz

THD+N − Total Harmonic Distortion + Noise − %

f

S

= 48 kHz

T

A

− Free-Air Temperature − °C

Figure 16

T

A

− Free-Air Temperature − °C

122

124

126

128

130

132

−50 −25 0 25 50 75 10

0

Dynamic Range − dB

DYNAMIC RANGE

vs

FREE-AIR TEMPERATURE

f

S

= 192 kHz

f

S

= 96 kHz

f

S

= 48 kHz

Figure 17

T

A

− Free-Air Temperature − °C

122

124

126

128

130

132

−50 −25 0 25 50 75 100

SNR − Signal-to-Noise Ratio − dB

SIGNAL-to-NOISE RATIO

vs

FREE-AIR TEMPERATURE

f

S

= 96 kHz

f

S

= 192 kHz

f

S

= 48 kHz

Figure 18

T

A

− Free-Air Temperature − °C

120

122

124

126

128

130

−50 −25 0 25 50 75 10

0

Channel Separation − dB

CHANNEL SEPARATION

vs

FREE-AIR TEMPERATURE

f

S

= 192 kHz

f

S

= 48 kHz

f

S

= 96 kHz

NOTE: PCM mode, V

DD

= 3.3 V, V

CC

= 5 V, measurement circuit is Figure 37 (V

OUT

= 4.5 V rms).

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13

Figure 19. −60-dB Output Spectrum, BW = 20 kHz

f − Frequency − kHz

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

0 2 4 6 8 101214161820

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

Figure 20. −60-dB Output Spectrum, BW = 100 kHz

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 102030405060708090100

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

NOTE: PCM mode, f

S

= 48 kHz, 32,768 point 8 average, T

A

= 25°C, V

DD

= 3.5 V V

CC

= 5 V, measurement circuit is Figure 37.

Figure 21. THD+N vs Input Level, PCM Mode

−100 −80 −60 −40 −20 0

Input Level − dBFS

TOTAL HARMONIC DISTORTION + NOISE

vs

INPUT LEVEL

10

0.1

0.01

0.001

0.0001

THD+N − Total Harmonic Distortion + Noise − %

1

NOTE: PCM mode, f

S

= 48 kHz, T

A

= 25°C, V

DD

= 3.3 V, V

CC

= 5 V, measurement circuit is Figure 37.

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14

Figure 22. −60-dB Output Spectrum, DSD Mode

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 2 4 6 8 101214161820

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

NOTE: DSD mode (FIR-4), 32,768 point 8 average, T

A

= 25°C, V

DD

= 3.3 V, V

CC

= 5 V, measurement circuit is Figure 38.

f − Frequency − kHz

−160

−157

−154

−151

−148

−145

−142

−139

−136

−133

−130

02468101214161820

Amplitude − dB

AMPLITUDE

vs

FREQUENCY

Figure 23. −150-dB Output Spectrum, DSD Mono Mode

NOTE: DSD mode (FIR-4), 32,768 point 8 average, T

A

= 25°C, V

DD

= 3.3 V, V

CC

= 5 V, measurement circuit is Figure 38.

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15

SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The PCM1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 7). The PCM1792A has a system clock detection circuit that

automatically senses if the system clock is operating between 128 f

S

and 768 f

S

. Table 1 shows examples of system clock

frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 f

S

,

the system clock frequency is over 256 f

S

.

Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock

source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators is an

excellent choice for providing the PCM1792A system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (f

SCK

) (MHz)

SAMPLING FREQUENCY

128 f

S

192 f

S

256 f

S

384 f

S

512 f

S

768 f

S

32 kHz 4.096

(1)

6.144

(1)

8.192 12.288 16.384 24.576

44.1 kHz 5.6488

(1)

8.4672 11.2896 16.9344 22.5792 33.8688

48 kHz 6.144

(1)

9.216 12.288 18.432 24.576 36.864

96 kHz 12.288 18.432 24.576 36.864 49.152

(1)

73.728

(1)

192 kHz 24.576 36.864 49.152

(1)

73.728

(1) (2) (2)

(1)

This system clock rate is not supported in I

2

C fast mode.

(2)

This system clock rate is not supported for the given sampling frequency.

t

(SCKH)

t

(SCY)

System Clock (SCK)

t

(SCKL)

2 V

0.8 V

H

L

PARAMETERS MIN MAX UNITS

t

(SCY)

System clock pulse cycle time 13 ns

t

(SCKH)

System clock pulse duration, HIGH 0.4 t

(SCY)

ns

t

(SCKL)

System clock pulse duration, LOW 0.4 t

(SCY)

ns

Figure 24. System Clock Input Timing

Power-On and External Reset Functions

The PCM1792A includes a power-on reset function. Figure 25 shows the operation of this function. With V

DD

> 2 V, the

power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V

DD

> 2 V. After

the initialization period, the PCM1792A is set to its default reset state, as described in the MODE CONTROL REGISTERS

section of this data sheet.

The PCM1792A also includes an external reset capability using the RST input (pin 14). This allows an external controller

or master reset circuit to force the PCM1792A to initialize to its default reset state.

Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST

pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The

external reset is especially useful in applications where there is a delay between the PCM1792A power up and system clock

activation.

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16

Reset Reset Removal

1024 System Clocks

V

DD

2.4 V (Max)

2 V (Typ)

1.6 V (Min)

Internal Reset

System Clock

Figure 25. Power-On Reset Timing

Reset Reset Removal

1024 System Clocks

Internal Reset

System Clock

RST (Pin 14)

t

(RST)

50 % of V

DD

PARAMETERS MIN MAX UNITS

t

(RST)

Reset pulse duration, LOW 20 ns

Figure 26. External Reset Timing

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17

AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial

audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface.

Serial data is clocked into the PCM1792A on the rising edge of BCK. LRCK is the serial audio left/right word clock.

The PCM1792A requires the synchronization of LRCK and system clock, but does not need a specific phase relation

between LRCK and system clock.

If the relationship between LRCK and system clock changes more than ±6 BCK, internal operation is initialized within 1/f

S

and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is

completed.

PCM Audio Data Formats and Timing

The PCM1792A supports industry-standard audio data formats, including standard right-justified, I

2

S, and left-justified. The

data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0], in control register 18. The

default data format is 24-bit I

2

S. All formats require binary 2s complement, MSB-first audio data. Figure 27 shows a detailed

timing diagram for the serial audio interface.

DATA

t

(BCH)

50% of V

DD

BCK

LRCK

t

(BCL)

t

(LB)

t

(BCY)

t

(DS)

t

(DH)

50% of V

DD

50% of V

DD

t

(BL)

PARAMETERS MIN MAX UNITS

t

(BCY)

BCK pulse cycle time 70 ns

t

(BCL)

BCK pulse duration, LOW 30 ns

t

(BCH)

BCK pulse duration, HIGH 30 ns

t

(BL)

BCK rising edge to LRCK edge 10 ns

t

(LB)

LRCK edge to BCK rising edge 10 ns

t

(DS)

DATA setup time 10 ns

t

(DH)

DATA hold time 10 ns

— LRCK clock duty 50% ± 2 bit clocks

Figure 27. Timing of Audio Interface

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006

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18

14 15 16 1 2 15 16

MSB LSB

1 2 15 16

18 19 20

MSB

LSB

1 2 19 20 1 2 19 20

22 23 24

LSB

1 232 24 1 232 24

21

MSB

LSB

1 2 24 1 2 24

LSB

1 2 24 211 2 24

21

LSB

1 2 16 1 2 16

BCK

L-Channel

DATA

R-Channel

1/f

S

DATA

LRCK

Audio Data Word = 16-Bit

Audio Data Word = 20-Bit

Audio Data Word = 24-Bit

BCK

L-Channel

DATA

R-Channel

1/f

S

LRCK

Audio Data Word = 24-Bit

23 23

15 15

23 23

BCK

L-Channel

DATA

R-Channel

1/f

S

LRCK

Audio Data Word = 24-Bit

DATA

Audio Data Word = 16-Bit

MSB

(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW

(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW

(3) I

2

S Data Format; L-Channel = LOW, R-Channel = HIGH

Figure 28. Audio Data Input Formats

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19

External Digital Filter Interface and Timing

The PCM1792A supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows

the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the Pacific

Microsonics PMD200, or a programmable digital signal processor.

In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as WDCK, the word clock; BCK, the bit

clock; and DATA, the monaural data. The external digital filter interface is selected by using the DFTH bit of control register

20, which functions to bypass the internal digital filter of the PCM1792A.

When the DFMS bit of control register 19 is set, the PCM1792A can process stereo data. In this case, ZEROL (pin 1) and

ZEROR (pin 2) are defined as L-channel data and R-channel data, respectively.

Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL

DIGITAL FILTER INTERFACE section of this data sheet.

Direct Stream Digital (DSD) Format Interface and Timing

The PCM1792A supports the DSD-format interface operation, which includes out-of-band noise filtering using an internal

analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left channel audio data),

and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in the DSD mode. The DSD-format

interface is activated by setting the DSD bit of control register 20.

Detailed information for the DSD mode is provided in the APPLICATION FOR DSD-FORMAT (DSD MODE) INTERFACE

section of this data sheet.

TDMCA Interface

The PCM1792A supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and

communication with a number of external devices over a single serial interface.

Detailed information for the TDMCA format is provided in the TDMCA Format section of this data sheet.

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20

FUNCTION DESCRIPTIONS

Zero Detect

The PCM1792A has a zero-detect function. When the PCM1792A detects the zero conditions as shown in Table 2, the

PCM1792A sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH.

Table 2. Zero Conditions

MODE DETECTING CONDITION AND TIME

PCM DATA is continuously LOW for 1024 LRCKs.

External DF Mode DATA is continuously LOW for 1024 WDCKs.

DSD

DZ0 There are an equal number of 1s and 0s in every 8 bits of DSD

input data for 200 ms.

DSD

DZ1 The input data is 1001 0110 continuously for 200 ms.

Serial Control Interface

The PCM1792A supports SPI and I

2

C serial control interfaces that set the mode control registers as shown in Table 4. This

serial control interface is selected by MSEL (pin 3); SPI is activated when MSEL is set to LOW, and I

2

C is activated when

MSEL is set to HIGH.

SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and the

system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The control

interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output, used to read

back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the serial

bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used to enable the internal

mode register access.

Register Read/Write Operation

All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word format.

The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For read operations,

the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read

and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from,

the register specified by IDX[6:0].

Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1 state until

a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen clocks are then

provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data on MDO. After the eighth

clock cycle has completed, the data from the indexed-mode control register appears on MDO during the read operation.

After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write

operation. To write or read subsequent data, MS must be set to 1 once.

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