RT8884B
®
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Multi-Phase PWM Controller for CPU Core Power Supply
Applications
VR12.5 Intel Core Power Supply
Notebook/Desktop Computer/Servers Multi-phase CPU
Core Power Supply
AVP Step-Down Converter
General Description
The RT8884B is a 4/3/2/1 multi-phase synchronous Buck
controller designed to meet Intel VR12.5 compatible CPU
specification with a serial VID control interface. The
RT8884B adopts G-NAVP
TM
(Green Native AVP) which is
Richtek's proprietary topology derived from finite DC gain
of EA amplifier with current mode control, making it easy
to set the droop to meet all Intel CPU requirements of
AVP (Adaptive Voltage Positioning). Based on the G-
NAVP
TM
topology, the RT8884B also features a quick
response mechanism for optimized AVP performance
during load transient. The RT8884B supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8884B to
communicate with Intel VR12.5 compliant CPU. The
RT8884B supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. By utilizing
the G-NAVP
TM
topology, the operating frequency of the
RT8884B varies with VID, load current and input voltage
to further enhance the efficiency even in CCM. Besides
G-NAVP
TM
, the CCRCOT (Constant Current Ripple
Constant On Time) technology provides superior output
voltage ripple over the entire input/output range.
Features
Intel VR12.5 Serial VID Interface Compatible
4/3/2/1 Phase PWM Controller
G-NAVP
TM
Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase Operation
Fast Transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, UVP, OCP, NVP, UVLO
External No-Load Offset Setting
DVID Enhancement
Small 32-Lead WQFN Package
RoHS Compliant and Halogen Free
Simplified Application Circuit
V
CORE
PWM3
PWM2
PWM1
RT8884B
PWM4
RT9624A
RT9624A
RT9624A
RT9624A
VR_RDY
VR_HOT
VCLK
VDIO
ALERT
To CPU
To PCH
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Pin Configurations
WQFN-32L 4x4
Ordering Information
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
0F= : Product Code
YMDNN : Date Code
Package Type
QW : WQFN-32L 4x4 (W-Type)
RT8884B
Lead Plating System
G : Green (Halogen Free and Pb Free)
0F=YM
DNN
ISEN1P
ISEN4N
ISEN3N
ISEN3P
DVD
VCLK
TONSET
VR_RDY
VSEN
RGND
VCC
SET1
ISEN2N
ISEN2P
EN
PWM2
IMON
ISEN4P
VDIO
ALERT
FB ISEN1N
SET2 PWM1
VREF VR_HOT
SET3 PWM3
IBIAS PWM4
COMP TSEN
33
24
23
22
21
1
2
3
4
10 11 12 13
31 30 29 28
20
19
5
6
9
32
14
27
18
7
15
26
16
25
17
8
GND
(TOP VIEW)
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Functional Pin Description
Pin No. Pin Name Pin Function
1, 30, 2, 5 ISEN [1:4] P Positive Current Sense Inputs of Channel 1, 2, 3 and 4.
32, 31, 3, 4 ISEN [1:4] N Negative Current Sense Inputs of Channel 1, 2, 3 and 4.
6 IMON
CPU CORE Current Monitor Output. This pin outputs a voltage proportional to
the output current.
7 VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
output voltage of IMON pin. Connect a 0.47μF decoupling capacitor between
this pin and GND.
8 COMP CORE VR Compensation. This pin is an error amplifier output pin.
9 FB
Negative Input of the Error Amplifier. This pin is for output voltage feedback to
controller.
10 VSEN
VR Voltage Sense Input. This pin is connected to the terminal of VR output
voltage.
11 RGND
Return Ground for VR. This pin is the negative node of the differential remote
voltage sensing.
12 VCC
Controller Power Supply. Connect this pin to 5V and place a minimum 2.2μF
decoupling capacitor. The decoupling capacitor should be placed to this pin as
close as possible.
13 SET1
1
st
Platform Setting. Platform can use this pin to set DVID time, RSET, DVID
width and OCS.
14 SET2
2
nd
Platform Setting. Platform can use this pin to set ICCMAX, QRTH and
QRSET.
15 SET3
3
rd
Platform Setting. Platform can use this to set output offset voltage.
16 IBIAS
Internal Bias Current Setting. Connect a 100kΩ resistor from this pin to GND for
setting the internal current. Don’t connect a bypass capacitor from this pin to
GND.
17 TSEN Thermal Sense Input for CORE VR.
18
VR_HOT
Thermal Monitor Output. (Active low).
19 VDIO VR and CPU Data Transmission Interface.
20
ALERT
SVID Alert. (Active low)
21 VCLK Synchronous Clock from the CPU.
22 TONSET
On-time Setting. An on-time setting resistor is connected from this pin to input
voltage.
23 VR_RDY VR Ready Indicator.
24 DVD
Divided Input Voltage Detection of CORE VR. Connect this pin to a voltage
divider from input voltage of power stage to detect input voltage.
27, 28, 26, 25 PWM [1:4] PWM Outputs for Channel 1, 2, 3 and 4.
29 EN VR Enable.
33
(Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
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Function Block Diagram
IBIAS
FB
COMP
RGND
PWM4
PWM3
PWM2
PWM1
ISEN4N
Soft-Start & Slew
Rate Control
VSET
OVP/UVP/NVP
ERROR
AMP
OCP
From Control Logic
Offset
Cancellation
ISEN4P
ISEN3N
ISEN3P
ISEN2N
ISEN2P
ISEN1N
ISEN1P
Current Balance
To Protection Logic
+
-
+
-
DAC
TON
GEN
+
-
Current mirror
IB1
Current mirror
IB2
Current mirror
IB3
Current mirror
IB4
+
-
OCS
OC
VSEN
IMON VREF
PWM
CMP
QR_TH
QRWIDTH
+
RSET
TONSET
SET2
Loop Control
Protection Logic
SVID Interface
Configuration Registers
Control Logic
UVLO
TON, QR_TH
QRWIDTH
ADC
SET1
IMONI
TSEN
EN
DVD
VCC
VR_RDY
GND
MUX
VCLK
VDIO
ALERT
VR_HOT
VSEN
+
-
+
-
+
-
To Protection Logic
RSETOCS
1/2
Ai
IB4IB3IB1 IB2
IMON Filter IMONI
SET3
DVID_TH,
DVID_WTH
DVID_TH,
DVID_WTH
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Operation
The RT8884B adopts G-NAVP
TM
(Green Native AVP) which
is Richtek's proprietary topology derived from finite DC
gain of EA amplifier with current mode control, making it
easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
The RT8884B adopts the G-NAVP
TM
controller, which is
one type of current mode constant on-time control with
DC offset cancellation. The approach can not only improve
DC offset problem for increasing system accuracy but also
provide fast transient response. For the RT8884B, when
current feedback signal reaches COMP signal to generate
an on-time width to achieve PWM modulation.
TON GEN
Generate the PWM1 to PWM4 sequentially according to
the phase control signal from the Loop Control Protection
Logic.
SVID Interface/Configuration Registers/Control
Logic
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Loop Control Protection Logic
It controls the power on sequence, the protection behavior,
and the operational phase number.
Current Balance
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the DVD and VCC voltage and issue POR signal as
they are high enough.
DAC
Generate an analog signal according to the digital code
generated by Control Logic.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 0 0 0 0 0 0 00 0.000
0 0 0 0 0 0 0 1 01 0.500
0 0 0 0 0 0 1 0 02 0.510
0 0 0 0 0 0 1 1 03 0.520
0 0 0 0 0 1 0 0 04 0.530
0 0 0 0 0 1 0 1 05 0.540
0 0 0 0 0 1 1 0 06 0.550
0 0 0 0 0 1 1 1 07 0.560
0 0 0 0 1 0 0 0 08 0.570
0 0 0 0 1 0 0 1 09 0.580
0 0 0 0 1 0 1 0 0A 0.590
0 0 0 0 1 0 1 1 0B 0.600
0 0 0 0 1 1 0 0 0C 0.610
0 0 0 0 1 1 0 1 0D 0.620
0 0 0 0 1 1 1 0 0E 0.630
0 0 0 0 1 1 1 1 0F 0.640
0 0 0 1 0 0 0 0 10 0.650
0 0 0 1 0 0 0 1 11 0.660
0 0 0 1 0 0 1 0 12 0.670
0 0 0 1 0 0 1 1 13 0.680
0 0 0 1 0 1 0 0 14 0.690
0 0 0 1 0 1 0 1 15 0.700
0 0 0 1 0 1 1 0 16 0.710
0 0 0 1 0 1 1 1 17 0.720
0 0 0 1 1 0 0 0 18 0.730
0 0 0 1 1 0 0 1 19 0.740
0 0 0 1 1 0 1 0 1A 0.750
0 0 0 1 1 0 1 1 1B 0.760
0 0 0 1 1 1 0 0 1C 0.770
0 0 0 1 1 1 0 1 1D 0.780
0 0 0 1 1 1 1 0 1E 0.790
0 0 0 1 1 1 1 1 1F 0.800
0 0 1 0 0 0 0 0 20 0.810
0 0 1 0 0 0 0 1 21 0.820
0 0 1 0 0 0 1 0 22 0.830
0 0 1 0 0 0 1 1 23 0.840
0 0 1 0 0 1 0 0 24 0.850
0 0 1 0 0 1 0 1 25 0.860
0 0 1 0 0 1 1 0 26 0.870
0 0 1 0 0 1 1 1 27 0.880
Table 1. VR12.5 VID Code Table
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 1 0 1 0 0 0 28 0.890
0 0 1 0 1 0 0 1 29 0.900
0 0 1 0 1 0 1 0 2A 0.910
0 0 1 0 1 0 1 1 2B 0.920
0 0 1 0 1 1 0 0 2C 0.930
0 0 1 0 1 1 0 1 2D 0.940
0 0 1 0 1 1 1 0 2E 0.950
0 0 1 0 1 1 1 1 2F 0.960
0 0 1 1 0 0 0 0 30 0.970
0 0 1 1 0 0 0 1 31 0.980
0 0 1 1 0 0 1 0 32 0.990
0 0 1 1 0 0 1 1 33 1.000
0 0 1 1 0 1 0 0 34 1.010
0 0 1 1 0 1 0 1 35 1.020
0 0 1 1 0 1 1 0 36 1.030
0 0 1 1 0 1 1 1 37 1.040
0 0 1 1 1 0 0 0 38 1.050
0 0 1 1 1 0 0 1 39 1.060
0 0 1 1 1 0 1 0 3A 1.070
0 0 1 1 1 0 1 1 3B 1.080
0 0 1 1 1 1 0 0 3C 1.090
0 0 1 1 1 1 0 1 3D 1.100
0 0 1 1 1 1 1 0 3E 1.110
0 0 1 1 1 1 1 1 3F 1.120
0 1 0 0 0 0 0 0 40 1.130
0 1 0 0 0 0 0 1 41 1.140
0 1 0 0 0 0 1 0 42 1.150
0 1 0 0 0 0 1 1 43 1.160
0 1 0 0 0 1 0 0 44 1.170
0 1 0 0 0 1 0 1 45 1.180
0 1 0 0 0 1 1 0 46 1.190
0 1 0 0 0 1 1 1 47 1.200
0 1 0 0 1 0 0 0 48 1.210
0 1 0 0 1 0 0 1 49 1.220
0 1 0 0 1 0 1 0 4A 1.230
0 1 0 0 1 0 1 1 4B 1.240
0 1 0 0 1 1 0 0 4C 1.250
0 1 0 0 1 1 0 1 4D 1.260
0 1 0 0 1 1 1 0 4E 1.270
0 1 0 0 1 1 1 1 4F 1.280
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 0 1 0 0 0 0 50 1.290
0 1 0 1 0 0 0 1 51 1.300
0 1 0 1 0 0 1 0 52 1.310
0 1 0 1 0 0 1 1 53 1.320
0 1 0 1 0 1 0 0 54 1.330
0 1 0 1 0 1 0 1 55 1.340
0 1 0 1 0 1 1 0 56 1.350
0 1 0 1 0 1 1 1 57 1.360
0 1 0 1 1 0 0 0 58 1.370
0 1 0 1 1 0 0 1 59 1.380
0 1 0 1 1 0 1 0 5A 1.390
0 1 0 1 1 0 1 1 5B 1.400
0 1 0 1 1 1 0 0 5C 1.410
0 1 0 1 1 1 0 1 5D 1.420
0 1 0 1 1 1 1 0 5E 1.430
0 1 0 1 1 1 1 1 5F 1.440
0 1 1 0 0 0 0 0 60 1.450
0 1 1 0 0 0 0 1 61 1.460
0 1 1 0 0 0 1 0 62 1.470
0 1 1 0 0 0 1 1 63 1.480
0 1 1 0 0 1 0 0 64 1.490
0 1 1 0 0 1 0 1 65 1.500
0 1 1 0 0 1 1 0 66 1.510
0 1 1 0 0 1 1 1 67 1.520
0 1 1 0 1 0 0 0 68 1.530
0 1 1 0 1 0 0 1 69 1.540
0 1 1 0 1 0 1 0 6A 1.550
0 1 1 0 1 0 1 1 6B 1.560
0 1 1 0 1 1 0 0 6C 1.570
0 1 1 0 1 1 0 1 6D 1.580
0 1 1 0 1 1 1 0 6E 1.590
0 1 1 0 1 1 1 1 6F 1.600
0 1 1 1 0 0 0 0 70 1.610
0 1 1 1 0 0 0 1 71 1.620
0 1 1 1 0 0 1 0 72 1.630
0 1 1 1 0 0 1 1 73 1.640
0 1 1 1 0 1 0 0 74 1.650
0 1 1 1 0 1 0 1 75 1.660
0 1 1 1 0 1 1 0 76 1.670
0 1 1 1 0 1 1 1 77 1.680
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 1 1 1 0 0 0 78 1.690
0 1 1 1 1 0 0 1 79 1.700
0 1 1 1 1 0 1 0 7A 1.710
0 1 1 1 1 0 1 1 7B 1.720
0 1 1 1 1 1 0 0 7C 1.730
0 1 1 1 1 1 0 1 7D 1.740
0 1 1 1 1 1 1 0 7E 1.750
0 1 1 1 1 1 1 1 7F 1.760
1 0 0 0 0 0 0 0 80 1.770
1 0 0 0 0 0 0 1 81 1.780
1 0 0 0 0 0 1 0 82 1.790
1 0 0 0 0 0 1 1 83 1.800
1 0 0 0 0 1 0 0 84 1.810
1 0 0 0 0 1 0 1 85 1.820
1 0 0 0 0 1 1 0 86 1.830
1 0 0 0 0 1 1 1 87 1.840
1 0 0 0 1 0 0 0 88 1.850
1 0 0 0 1 0 0 1 89 1.860
1 0 0 0 1 0 1 0 8A 1.870
1 0 0 0 1 0 1 1 8B 1.880
1 0 0 0 1 1 0 0 8C 1.890
1 0 0 0 1 1 0 1 8D 1.900
1 0 0 0 1 1 1 0 8E 1.910
1 0 0 0 1 1 1 1 8F 1.920
1 0 0 1 0 0 0 0 90 1.930
1 0 0 1 0 0 0 1 91 1.940
1 0 0 1 0 0 1 0 92 1.950
1 0 0 1 0 0 1 1 93 1.960
1 0 0 1 0 1 0 0 94 1.970
1 0 0 1 0 1 0 1 95 1.980
1 0 0 1 0 1 1 0 96 1.990
1 0 0 1 0 1 1 1 97 2.000
1 0 0 1 1 0 0 0 98 2.010
1 0 0 1 1 0 0 1 99 2.020
1 0 0 1 1 0 1 0 9A 2.030
1 0 0 1 1 0 1 1 9B 2.040
1 0 0 1 1 1 0 0 9C 2.050
1 0 0 1 1 1 0 1 9D 2.060
1 0 0 1 1 1 1 0 9E 2.070
1 0 0 1 1 1 1 1 9F 2.080
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 0 1 0 0 0 0 0 A0 2.090
1 0 1 0 0 0 0 1 A1 2.100
1 0 1 0 0 0 1 0 A2 2.110
1 0 1 0 0 0 1 1 A3 2.120
1 0 1 0 0 1 0 0 A4 2.130
1 0 1 0 0 1 0 1 A5 2.140
1 0 1 0 0 1 1 0 A6 2.150
1 0 1 0 0 1 1 1 A7 2.160
1 0 1 0 1 0 0 0 A8 2.170
1 0 1 0 1 0 0 1 A9 2.180
1 0 1 0 1 0 1 0 AA 2.190
1 0 1 0 1 0 1 1 AB 2.200
1 0 1 0 1 1 0 0 AC 2.210
1 0 1 0 1 1 0 1 AD 2.220
1 0 1 0 1 1 1 0 AE 2.230
1 0 1 0 1 1 1 1 AF 2.240
1 0 1 1 0 0 0 0 B0 2.250
1 0 1 1 0 0 0 1 B1 2.260
1 0 1 1 0 0 1 0 B2 2.270
1 0 1 1 0 0 1 1 B3 2.280
1 0 1 1 0 1 0 0 B4 2.290
1 0 1 1 0 1 0 1 B5 2.300
1 0 1 1 0 1 1 0 B6 2.310
1 0 1 1 0 1 1 1 B7 2.320
1 0 1 1 1 0 0 0 B8 2.330
1 0 1 1 1 0 0 1 B9 2.340
1 0 1 1 1 0 1 0 BA 2.350
1 0 1 1 1 0 1 1 BB 2.360
1 0 1 1 1 1 0 0 BC 2.370
1 0 1 1 1 1 0 1 BD 2.380
1 0 1 1 1 1 1 0 BE 2.390
1 0 1 1 1 1 1 1 BF 2.400
1 1 0 0 0 0 0 0 C0 2.410
1 1 0 0 0 0 0 1 C1 2.420
1 1 0 0 0 0 1 0 C2 2.430
1 1 0 0 0 0 1 1 C3 2.440
1 1 0 0 0 1 0 0 C4 2.450
1 1 0 0 0 1 0 1 C5 2.460
1 1 0 0 0 1 1 0 C6 2.470
1 1 0 0 0 1 1 1 C7 2.480
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 1 0 0 1 0 0 0 C8 2.490
1 1 0 0 1 0 0 1 C9 2.500
1 1 0 0 1 0 1 0 CA 2.510
1 1 0 0 1 0 1 1 CB 2.520
1 1 0 0 1 1 0 0 CC 2.530
1 1 0 0 1 1 0 1 CD 2.540
1 1 0 0 1 1 1 0 CE 2.550
1 1 0 0 1 1 1 1 CF 2.560
1 1 0 1 0 0 0 0 D0 2.570
1 1 0 1 0 0 0 1 D1 2.580
1 1 0 1 0 0 1 0 D2 2.590
1 1 0 1 0 0 1 1 D3 2.600
1 1 0 1 0 1 0 0 D4 2.610
1 1 0 1 0 1 0 1 D5 2.620
1 1 0 1 0 1 1 0 D6 2.630
1 1 0 1 0 1 1 1 D7 2.640
1 1 0 1 1 0 0 0 D8 2.650
1 1 0 1 1 0 0 1 D9 2.660
1 1 0 1 1 0 1 0 DA 2.670
1 1 0 1 1 0 1 1 DB 2.680
1 1 0 1 1 1 0 0 DC 2.690
1 1 0 1 1 1 0 1 DD 2.700
1 1 0 1 1 1 1 0 DE 2.710
1 1 0 1 1 1 1 1 DF 2.720
1 1 1 0 0 0 0 0 E0 2.730
1 1 1 0 0 0 0 1 E1 2.740
1 1 1 0 0 0 1 0 E2 2.750
1 1 1 0 0 0 1 1 E3 2.760
1 1 1 0 0 1 0 0 E4 2.770
1 1 1 0 0 1 0 1 E5 2.780
1 1 1 0 0 1 1 0 E6 2.790
1 1 1 0 0 1 1 1 E7 2.800
1 1 1 0 1 0 0 0 E8 2.810
1 1 1 0 1 0 0 1 E9 2.820
1 1 1 0 1 0 1 0 EA 2.830
1 1 1 0 1 0 1 1 EB 2.840
1 1 1 0 1 1 0 0 EC 2.850
1 1 1 0 1 1 0 1 ED 2.860
1 1 1 0 1 1 1 0 EE 2.870
1 1 1 0 1 1 1 1 EF 2.880
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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 1 1 1 0 0 0 0 F0 2.890
1 1 1 1 0 0 0 1 F1 2.900
1 1 1 1 0 0 1 0 F2 2.910
1 1 1 1 0 0 1 1 F3 2.920
1 1 1 1 0 1 0 0 F4 2.930
1 1 1 1 0 1 0 1 F5 2.940
1 1 1 1 0 1 1 0 F6 2.950
1 1 1 1 0 1 1 1 F7 2.960
1 1 1 1 1 0 0 0 F8 2.970
1 1 1 1 1 0 0 1 F9 2.980
1 1 1 1 1 0 1 0 FA 2.990
1 1 1 1 1 0 1 1 FB 3.000
1 1 1 1 1 1 0 0 FC 3.010
1 1 1 1 1 1 0 1 FD 3.020
1 1 1 1 1 1 1 0 FE 3.030
1 1 1 1 1 1 1 1 FF 3.040
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Table 2. Standard Serial VID Commands
Code Commands
Master
Payload
Contents
Slave
Payload
Contents
Description
00h not supported N/A N/A N/A
01h SetVID_Fast VID code N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default “fast” slew rate 12.5mV/μs.
2. Set VR_Settled when VR reaches target VID voltage.
02h SetVID_Slow VID code N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default “slow” slew rate 3.125mV/μs.
2. Set VR_Settled when VR reaches target VID voltage.
03h SetVID_Decay VID code N/A
1. Set new target VID code, VR jumps to new VID target,
but does not control the slew rate. The output voltage
decays at a rate proportional to the load current.
2. Low side MOSFET is not allowed to sync current.
3. ACK 11b when target higher than current VOUT
voltage.
4. ACK 10b when target lower than current VOUT
voltage.
04h SetPS
Byte
indicating
power states
N/A
1. Set power state.
2. ACK 11b when not support.
3. ACK 10b even slave not change configuration.
4. ACK 11b for still running SetVID command.
5. VR remains in lower state when receiving SetVID
(decay).
05h SetRegADR
Pointer of
registers in
data table
N/A
1. Set the pointer of the data register.
2. ACK 11b for address outside of support.
3. NAK 01b for SetADR (all call).
06h SetReg DAT
New data
register
content
N/A
1. Write the contents to the data register.
2. NAK 01b for SetReg (all call).
07h GetReg
Specified
Register
Contents
1. Slave returns the contents of the specified register as
the payload.
2. ACK 11b for non support address.
3. NAK 01b for GetReg (all call).
08h to
1Fh
not supported N/A N/A N/A
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Table 3. SVID Data and Configuration Register
Index Register Name Description Access Default
00h Vendor ID Vendor ID RO, Vendor 1Eh
01h Product ID Product ID RO, Vendor 84h
02h Product Revision Product Revision RO, Vendor 00h
05h Protocol ID SVID Protocol ID RO, Vendor 02h
06h Capability
Bit mapped register, identifies the SVID VR Capabilities
and which of the optional telemetry register is supported.
RO, Vendor 81h
10h Status_1 Data register containing the status of VR.
R-M,
W-PWM
00h
11h Status-2 Data register containing the status of transmission.
R-M,
W-PWM
00h
12h
Temperature
Zone
Data register showing temperature zone that has been
entered.
R-M,
W-PWM
00h
15h IOUT
At PS0 to PS2, IOUT report data from ADC sense IMON
voltage. When power state at PS3, the IOUT report data is
fixed to 04h.
R-M,
W-PWM
00h
1Ch Status_2_lastread The register contains a copy of the status_2.
R-M,
W-PWM
00h
21h ICC Max
Data register containing the ICC max the platform
supports. Binary format in A IE 64h = 100A.
RO,
Platform
7Dh
22h Temp Max
Data register containing the temperature max the platform
supports.
Binary format in °C IE 64h = 100°C.
RO,
Platform
64h
24h SR-fast
Data register containing the capability of fast slew rate the
platform can sustain. Binary format in mV/μs IE 0Ah = 10
mV/μs.
RO 0Ah
25h SR-slow
Data register containing the capability of slow slew rate.
Binary format in mV/μs IE 02h = 2mV/μs.
RO 02h
30h VOUT Max
The register is programmed by master and sets the
maximum VID.
RW, Master B5h
31h VID Setting Data register containing currently programmed VID. RW, Master 00h
32h Power State Register containing the current programmed power state. RW, Master 00h
33h Offset Set offset in VID steps. RW, Master 00h
34h
Multi VR
Configuration
Bit mapped data register which configures multiple VRs
behavior on the same bus.
RW, Master 00h
35h Pointer
Scratch pad register for temporary storage of the
SetRegADR pointer register.
RW, Master 30h
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM Only
Vendor = Hard Coded by VR Vendor
Platform = Programmed by the Master
PWM = Programmed by the VR Control IC
RT8884B
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Electrical Characteristics
Recommended Operating Conditions
(Note 4)
Supply Voltage, VCC ---------------------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C
Absolute Maximum Ratings (Note 1)
VCC to GND --------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
RGND to GND ------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
TONSET to GND ---------------------------------------------------------------------------------------------------- −0.3V to 6.5V
Other Pins------------------------------------------------------------------------------------------------------------ −0.3V to (V
CC
+ 0.3V)
Power Dissipation, P
D
@ T
A
= 25°C
WQFN-32L 4x4 ----------------------------------------------------------------------------------------------------- 3.6W
Package Thermal Resistance (Note 2)
WQFN-32L 4x4, θ
JA
------------------------------------------------------------------------------------------------ 27.8°C/W
WQFN-32L 4x4, θ
JC
----------------------------------------------------------------------------------------------- 7°C/W
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV
(V
CC
= 5V, T
A
= 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Input
Supply Current I
VC C
V
EN
= H, Not switching -- 4.1 -- mA
Supply Current at PS3 I
VC C_PS3
V
EN
= H, Not switching -- 2.7 -- mA
Shutdown Current I
SH DN
V
EN
= 0V -- -- 5 μA
Reference and DAC
V
DAC
= 1.5V − 2.3V −0.5 0 0.5
% of
VID
V
DAC
= 1V − 1.49V −8 0 8
DAC Accuracy V
FB
V
DAC
= 0.5V − 0.99V −10 0 10
mV
Slew Rate
Set VID slow 2.5 3.125 3.75
Dynamic VID Slew Rate SR
Set VID fast 10 12.5 15
mV/μs
EA Amplifier
DC Gain A
DC
R
L
= 47kΩ 70 -- -- dB
Gain-Bandwidth Product G
BW
C
LOAD
= 5pF 4 5 -- MHz
Slew Rate SR
EA
C
LOAD
= 10pF (Gain = −4, R
F
= 47kΩ,
V
OUT
= 0.5V to −3V)
5 -- -- V/μs
RT8884B
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Parameter Symbol Test Conditions Min Typ Max Unit
Output Voltage Range V
COMP
R
L
= 47kΩ 0.5 -- 3.6 V
Maximum Source/Sink Current I
OUTEA
V
COMP
= 2V -- 5 -- mA
Load-Line Current Gain Amplifier
Input Offset Voltage V
ILOFS
V
IMON
= 1V −5 -- 5 mV
Current Gain A
ILGAIN
V
IMON
− V
VREF
= 1V
V
FB
= V
COMP
= 1.7V
-- 1/2 -- A/A
Current Sensing Amplifier
Input Offset Voltage V
OSCS
−0.8 -- 0.8 mV
Impedance at Positive Input R
ISENxP
1 -- -- MΩ
Current Mirror Gain A
MIRROR
I
IMON
/ I
SENxN
0.97 1 1.03 A/A
TON Setting
TONSET Pin Voltage V
TON
I
RTON
= 80μA, V
DAC
= 1.7V 1.6 1.7 1.8 V
On-Time Setting T
ON
I
RTON
= 80μA, V
DAC
= 1.7V 450 500 550 ns
Input Current Range I
RTON
V
DAC
= 1.7V 25 -- 280 μA
Minimum Off time T
OFF
V
DAC
= 1.7V -- 400 -- ns
IBIAS
IBIAS Pin Voltage V
IBIAS
R
IBIAS
= 100kΩ 1.85 2 -- V
OFS Setting
Impedance R
OFS
1 -- -- MΩ
Enable OFS function and offset
600mV
1.95 2.4 2.44
Enable OFS function and offset
300mV
1.76 1.8 1.84
Enable OFS function and offset 0V 1.16 1.2 1.24
Enable OFS function and offset
−50mV
1.06 1.1 1.14
Enable OFS function and offset
−250mV
0.66 0.7 0.74
Set OFS Voltage V
SET3
Disable -- -- 0.55
V
Protections
V
UVLO
4.1 4.3 4.45 V
Under Voltage Lockout Threshold
ΔV
UVLO
Falling edge hysteresis -- 200 -- mV
VID higher than 1.5V
VID
+ 300
VID
+ 350
VID
+ 400
Over Voltage Protection Threshold V
OV
VID lower than 1.5V 1800 1850 1900
mV
Under Voltage Protection Threshold V
UV
Respect to VID voltage −400 −350 −300 mV
Negative Voltage Protection
Threshold
V
NV
−100 −70 -- mV
EN and VR_RDY
Logic-High V
IH
0.7 -- --
EN Input Voltage
Logic-Low V
IL
-- -- 0.3
V
Leakage Current of EN −1 -- 1 μA
RT8884B
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Parameter Symbol Test Conditions Min Typ Max Unit
VR_RDY Delay T
VR_RDY
V
SEN
= VBoot to VR_RDY High 3 4.5 6 μs
VR_RDY Pull Low Voltage V
PGOOD
I
VR_RDY
= 10mA -- -- 0.13 V
DVD
DVD Input V
DVD
Detect VIN Voltage 2 -- -- V
Serial VID and VR_HOT
Logic-High V
IH
Respect to INTEL Spec. with
50mV hysteresis
0.65 -- --
VCLK, VDIO
Input Voltage
Logic-Low V
IL
-- -- 0.45
V
Leakage Current of VCLK,
VDIO, ALERT and VR_HOT
I
LEAK_IN
−1 -- 1 μA
I
VDIO
= 10mA
I
ALERT
= 10mA
VDIO, ALERT and VR_HOT
Pull Low Voltage
I
VR_HOT
= 10mA
-- -- 0.13 V
V
REF
and V
BOOT
V
REF
Voltage V
REF
0.55 0.6 0.65 V
V
BOOT
Voltage V
BOOT
No Load, set V
BOOT
= 1.7V 1.692 1.7 1.708 V
ADC
V
IMON
− V
IMON_INI
= 1.6V 252 255 258
V
IMON
− V
IMON_INI
= 0.8V 125 128 131 Digital IMON Set V
IMON
V
IMON
− V
IMON_INI
= 0V 0 0 3
Decimal
Update Period of IMON T
IMON
320 400 480 μs
TSEN Threshold for
Tmp_Zone [7] transition
V
TSEN
100°C -- 1.887 -- V
TSEN Threshold for
Tmp_Zone [6] transition
V
TSEN
97°C -- 1.837 -- V
TSEN Threshold for
Tmp_Zone [5] transition
V
TSEN
94°C -- 1.784 -- V
TSEN Threshold for
Tmp_Zone [4] transition
V
TSEN
91°C -- 1.729 -- V
TSEN Threshold for
Tmp_Zone [3] transition
V
TSEN
88°C -- 1.672 -- V
TSEN Threshold for
Tmp_Zone [2] transition
V
TSEN
85°C -- 1.612 -- V
TSEN Threshold for
Tmp_Zone [1] transition
V
TSEN
82°C -- 1.551 -- V
TSEN Threshold for
Tmp_Zone [0] transition
V
TSEN
75°C -- 1.402 -- V
Update Period of TSEN t
TSEN
40 50 60 μs
C
ICCMAX1
V
ICCMAX
= 0.403V 58 64 70
C
ICCMAX2
V
ICCMAX
= 0.806V 122 128 134
Digital Code of ICCMAX
C
ICCMAX3
V
ICCMAX
= 1.6V 248 256 260
Decimal
RT8884B
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Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θ
JA
is measured at T
A
= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ
JC
is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Parameter Symbol Test Conditions Min Typ Max Unit
PWM Driving Capability
PWM Source Resistance R
PWM _SRC
-- -- 30 Ω
PWM Sink R
PWM _SNK
-- -- 10 Ω
RT8884B
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Typical Application Circuit
RT8884B
TSEN
17
22
T
O
N
S
E
T
14
13
15
SET2
SET1
SET3
12V
12
VCC
5V
24
DVD
I
B
I
A
S
16
R
NTC2
V
R
E
F
IMON
6
7
3
1
2
V
PWM
BOOT
UGATE
PHASE
LGATE
RT9624A
ISEN3N
ISEN3P
2
ISEN2P
ISEN2N
30
31
PWM3
PWM2
28
26
1
2
V
1
2
V
LOAD
V
C
C
_
S
E
N
S
E
V
S
S
_
S
E
N
S
E
V
C
O
R
E
_
O
U
T
ISEN4N
ISEN4P
PWM4
25
5
4
VIN
GND
33 (Exposed Pad)
V
S
E
N
COMP
1
1
2
V
ISEN1P
ISEN1N
32
PWM1
27
V
CC_SENSE
V
SS_SENSE
RGND
VCCIO
VR_RDY
23
18
VR_HOT
VCLK
VDIO
ALERT
To CPU
EN
21
19
20
29
8
11
10
FB
9
EN5V
VCC
GND
1
2
V
R1
510k
R2
125k
R3
2.2
C1
0.1µF
C2
2.2µF
R5
R7
1.833k
R9
9.68k
R12
6.2k
VCC
R
NTC1
R4
R6 30k
R8 75.8k
R10 100k
R11 5.6k
100k
C5
390pF
C6
90pF
R24
10k
C7
C8
C9
Optional
Optional
Optional
R19
10k
R20
75
R21
130
R22
130
R23
150
R18
5.43k
100k
R16 12.6k
C4
0.47µF
R17
13.9k
R15
100k
R13 1
C3
0.1µF
R49 680
Q8 x 2
Q7
R45 0
R44 2.2
C32
0.1µF
C33
22µF
C34
390µF
C36 1µF
R47
510
Optional
R48
R46
C35
Optional
R43 680
Q6 x 2
Q5
R39 0
R38 2.2
C26
0.1µF
C27
22µF
C28
390µF
C30 1µF
R41
510
Optional
R42
R40
C29
Optional
R37 680
Q4 x 2
Q3
R33 0
R32 2.2
C17
0.1µF
C18
22µF
C19
390µF
C21 1µF
R35
510
Optional
R36
R34
C20
Optional
C25
0.1µF
PWM
BOOT
UGATE
PHASE
LGATE
RT9624A
EN
5V
VCC
GND
1
2
V
C31
0.1µF
PWM
BOOT
UGATE
PHASE
LGATE
RT9624A
EN
5V
VCC
GND
1
2
V
C16
0.1µF
PWM
BOOT
UGATE
PHASE
LGATE
RT9624A
EN
5V
VCC
GND
1
2
V
C10
0.1µF
R31 680
Q2 x 2
Q1
R27 0
R26 2.2
C11
0.1µF
C12
22µF
C13
390µF
L1
C15 1µF
R29
510
Optional
R30
R28
C14
Optional
R37 R38
C22
Optional
C23
560µF/7m
x4
C22
22µFx19
Optional for OFS
ß = 4485
ß = 4485
R14
130k
L2
L3
L4
360nH / 0.72mΩ
360nH / 0.72mΩ
360nH / 0.72m
Ω
360nH / 0.72mΩ
R25
59.2k
Enable
RT8884B
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Typical Operating Characteristics
V
IN
= 12V, No Load, Boot VID 1.7V
Time (200μs/Div)
CORE VR Power On from EN
EN
(2V/Div)
VR_RDY
(2V/Div)
UGATE1
(20V/Div)
V
CORE
(2V/Div)
V
IN
= 12V, No Load, Boot VID 1.7V
Time (200μs/Div)
CORE VR Power Off from EN
EN
(2V/Div)
VR_RDY
(2V/Div)
UGATE1
(20V/Div)
V
CORE
(2V/Div)
V
IN
= 12V, VID = 1.85V to 1.6V, Slew Rate = Slow
Time (20μs/Div)
CORE VR Dynamic VID Down
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
V
CORE
(1V/Div)
V
IN
= 12V, VID = 1.6V to 1.85V, Slew Rate = Slow
Time (20μs/Div)
CORE VR Dynamic VID Up
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
V
CORE
(1V/Div)
V
IN
= 12V, Boot VID 1.7V
Time (40μs/Div)
CORE VR OVP
VR_RDY
(1V/Div)
UGATE1
(20V/Div)
LGATE1
(20V/Div)
V
CORE
(2V/Div)
V
IN
= 12V, Boot VID 1.7V
Time (100μs/Div)
CORE VR OCP
I
LOAD
(150A/Div)
VR_RDY
(2V/Div)
UGATE1
(50V/Div)
V
CORE
(2V/Div)
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