Delta Tau PMAC MINI PCI Reference guide

Delta Tau
Brand
Delta Tau
Model
PMAC MINI PCI
Type
Reference guide
^1 HARDWARE REFERENCE MANUAL
^2 Flex CPU Piggyback Board
^3 CPU
^4 3xx-603605-xHxx
^5 December 8 2003
Single Source Machine Control Power // Flexibility // Ease of Use
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
Copyright Information
© 2003 Delta Tau Data Systems, Inc. All rights reserved.
This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained
in this manual may be updated from time-to-time due to product improvements, etc., and may not
conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656
Fax: (818) 998-7807
Email: [email protected]
Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain
static sensitive components that can be damaged by incorrect handling. When installing or
handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials.
Only qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial
environment, install them into an industrial electrical cabinet or industrial PC to protect them
from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials.
If Delta Tau Data Systems, Inc. products are directly exposed to hazardous or conductive
materials and/or environments, we cannot guarantee their operation.
Flex CPU Piggyback Board Hardware Reference
Table of Contents i
Table of Contents
INTRODUCTION.......................................................................................................................................................1
BOARD CONFIGURATION.....................................................................................................................................3
Non-Turbo CPU Base Configuration ...................................................................................................................3
Non-Turbo CPU Further Options.........................................................................................................................3
Turbo CPU Base Configuration...........................................................................................................................3
Turbo CPU Further Options.................................................................................................................................3
HARDWARE SETUP.................................................................................................................................................5
Flex CPU Board Jumper Configuration...............................................................................................................5
Watchdog Timer Jumper.......................................................................................................................................5
Dual-Ported RAM Source Jumper........................................................................................................................5
Power-Up State Jumpers......................................................................................................................................5
Firmware Load Jumper........................................................................................................................................5
Flash Memory Bank Select Jumpers.....................................................................................................................5
Installation............................................................................................................................................................5
OPERATION OF THE FLEX CPU ..........................................................................................................................7
Operation as Non-Turbo CPU..............................................................................................................................7
Operation as a Turbo CPU...................................................................................................................................9
FLEX CPU BOARD JUMPER DESCRIPTIONS..................................................................................................11
E1: Watchdog Disable Jumper...........................................................................................................................11
E2: Dual-Ported RAM Port Select......................................................................................................................11
E4 – E6: Power-Up/Reset Load Source..............................................................................................................11
E7: Firmware Reload Enable.............................................................................................................................11
E10A, B, C: Flash Memory Bank Select.............................................................................................................12
CONNECTOR SUMMARY.....................................................................................................................................13
CONNECTOR PINOUTS.........................................................................................................................................15
J8 JRS232 (10-Pin Connector)...........................................................................................................................15
SCHEMATICS
Flex CPU Piggyback Board Hardware Reference
ii Table of Contents
Flex CPU Piggyback Board Hardware Reference
Introduction 1
INTRODUCTION
The Flex CPU piggyback board (Part # 300-603605-10x) for the PMAC/PMAC2 and Turbo
PMAC/PMAC2 families of boards provides new high-end capabilities for these controllers and uses
newer components with longer product lifetimes. It can be manufactured in a wide variety of
configurations, and can be used in the following products:
• PMAC(1)-PC
• PMAC(1)-PCI
• PMAC(1)-VME
• PMAC2-PC
• PMAC2-PCI
• PMAC2-VME
• Turbo PMAC(1)-PC
• Turbo PMAC(1)-PCI
• Turbo PMAC(1)-VME
• Turbo PMAC2-PC
• Turbo PMAC2-PCI
• Turbo PMAC2-VME
On the regular (non-Turbo) PMAC(1) and PMAC2 boards, the Flex CPU is provided automatically when
any of the following CPU options are ordered:
• Option 5AF: 40 MHz CPU with 128k x 24 internal SRAM
• Option 5CF: 80 MHz CPU with 128k x 24 internal SRAM
• Option 5EF: 160 MHz CPU with 128k x 24 internal SRAM
The Flex CPU board is not provided if Option 4x or 5x is not ordered, or if Option 4A, 5A, 5B, or 5C is
ordered.
On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU may be provided when any of the
following CPU options is ordered:
• Option 5C0: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 256k x 24 external SRAM
• Option 5C3: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 1M x 24 external SRAM
• Option 5D0: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 256k x 24 external SRAM
• Option 5D3: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 1M x 24 external SRAM
In these cases, however, the older Turbo only CPU piggyback board may also be provided.
On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU will be provided automatically when either
of the following CPU options is ordered:
• Option 5E0: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 256k x 24 external SRAM
• Option 5E3: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 1M x 24 external SRAM
Flex CPU Piggyback Board Hardware Reference
2 Introduction
Flex CPU Piggyback Board Hardware Reference
Board Configuration 3
BOARD CONFIGURATION
Non-Turbo CPU Base Configuration
When assembled for a non-Turbo CPU, the DSP IC in U1 of the Flex CPU board contains all of the
memory required for operation. Therefore, there are no ICs installed in the locations for external RAM:
U11, U12, U13, U14, U15, and U16.
The CPU is available in several speed options: 40 MHz (Option 5AF), 80 MHz (Option 5CF), and 160
MHz (Option 5EF). The maximum frequency of operation is indicated with a sticker on the CPU in U1.
When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin
header on the solder side for direct connection to the baseboard, and a 10-pin header on the component
side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex
CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side
for direct connection of all signals to the baseboard.
Non-Turbo CPU Further Options
The Option 16 battery-backed parameter RAM provides a bank of non-volatile memory for the controller.
Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1
Turbo CPU Base Configuration
When assembled for a Turbo CPU section, the Flex CPU board contains external RAM ICs in locations
U11, U12, U13, U14, U15, U16. With the standard memory configuration (Option 5x0), these ICs fill the
smaller footprint in these locations, leaving an open pin on the board on each end of each side.
When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin
header on the solder side for direct connection to the baseboard, and a 10-pin header on the component
side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex
CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side
for direct connection of all signals to the baseboard.
Turbo CPU Further Options
If an expanded memory configuration (Option 5x3) is ordered, larger RAM ICs are installed in locations
U11, U12, U13, U14, U15, U16, occupying the full footprints in these locations
If the Option 9T auxiliary serial port is ordered for the Turbo PMAC controller, an RS-232 serial port is
provided on the CPU board to supplement the serial port on the baseboard. The key components are ICs
in U28 and U29, and the connector J8.
The Option 16A battery-backed parameter RAM provides a bank of non-volatile memory for the
controller. Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1
Flex CPU Piggyback Board Hardware Reference
4 Board Configuration
Flex CPU Piggyback Board Hardware Reference
Hardware Setup 5
HARDWARE SETUP
Flex CPU Board Jumper Configuration
Watchdog Timer Jumper
Jumper E1 on the Turbo CPU board must be OFF for the watchdog timer to operate. This is a very
important safety feature, so it is vital that this jumper be OFF in normal operation. E1 should be put ON
only to debug problems with the watchdog timer circuit.
Dual-Ported RAM Source Jumper
Jumper E2 must connect pins 1 and 2 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo
addresses $06xxxx) from the baseboard. If it is desired to use the Option 2 DPRAM on the baseboard,
jumper E2 must be in this setting. All Delta Tau base boards except the PMAC(1)-PC board have the
option for installing DPRAM on the base board.
Jumper E2 must connect pins 2 and 3 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo
addresses $06xxxx) through the JEXP expansion port. If it is desired to use DPRAM on an external
accessory board, jumper E2 must be in this setting. The PMAC(1)-PC base board (part # 602191-10x)
does not have the option for installing on-board DPRAM; it requires the external Option 2 DPRAM board
(part #602240-10x) for this functionality. Use of this DPRAM board, interfacing through the JEXP port,
requires E2 to connect pins 2 and 3.
Power-Up State Jumpers
Jumper E4 on the Turbo CPU board must be OFF, jumper E5 must be ON, and jumper E6 must be ON, in
order for the CPU to copy the firmware from flash memory into active RAM on power-up/reset. This is
necessary for normal operation of the card. (Other settings are for factory use only.)
Firmware Load Jumper
If jumper E7 on the CPU board is ON during power-up/reset, the board comes up in “bootstrap mode,”
which permits loading new firmware into the flash-memory IC on the board. When the PMAC Executive
program tries to establish communications with a board in this mode, it will automatically detect that the
board is in bootstrap mode and ask you what file you want to download as the new firmware.
Jumper E7 must be OFF during power-up/reset for the board to come up in normal “operational mode.”
Flash Memory Bank Select Jumpers
The flash-memory IC in location U10 on the Flex CPU board has the capacity for eight separate banks of
firmware, only one of which can be used at any given time. The eight combinations of settings for
jumpers E10A, E10B, and E10C select which bank of the flash memory is used. In the factory production
process, firmware is loaded only into Bank 0, which is selected by having all of these jumpers OFF.
Installation
The Flex CPU board installs on the base controller board using the P1 and P3 stack connectors on the
solder side of the CPU board. The CPU board can be further secured to the base board with a standoff
and screw through the central hole. When a complete PMAC or Turbo PMAC controller is purchased,
this assembly is done at the factory. In the case of retrofits or updates to existing controllers, this
assembly is easy to do in the field.
ESD Warning: The Flex CPU board and PMAC controller boards contain static-sensitive components.
Make sure proper ESD protection is employed.
Flex CPU Piggyback Board Hardware Reference
6 Hardware Setup
Flex CPU Piggyback Board Hardware Reference
Operation of the Flex CPU 7
OPERATION OF THE FLEX CPU
Operation as Non-Turbo CPU
When used as a non-Turbo CPU, the Flex CPU board operates in a manner that is fundamentally
compatible with older CPU designs. However, there are a few issues to note:
• The Flex CPU requires the use of V1.17 or newer firmware. There are few differences between the
previous V1.16H firmware and the V1.17 firmware other than the addition of internal support for the
Flex CPU design.
• Due to more advanced processor logic and the internal integration of all memory, the Flex CPU will
operate significantly faster than older non-Turbo CPU designs, even for equivalent CPU frequencies.
The Flex CPU in a non-Turbo configuration will generally operate more than twice as fast as older
non-Turbo CPUs running at the same frequency.
This will result in significantly faster cycle times for background tasks such as PLC programs (the
frequency of interrupt-driven foreground tasks is not affected, although the increased computational
speeds permit higher frequencies for these tasks). Generally, this will not be a problem, but if
existing programs controlled timing by computational delay (e.g. number of loops waiting),
operational differences may occur.
• The operational frequency of the CPU can now be set in software by new variable I46. If this
variable is set to 0, PMAC firmware looks at the jumpers (E48 on a PMAC(1), E2 and E4 on a
PMAC2) to set the operational frequency, retaining backward compatibility for 40, 60, and 80 MHz
operation.. If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 +
1), regardless of the jumper setting. If the desired operational frequency is higher than the maximum
rated frequency for that CPU, the operational frequency will be reduced to the rated maximum. It is
always possible to operate the Flex CPU board at a frequency below its rated maximum.
On a Flex CPU board configured for Option 5AF with 40 MHz maximum frequency, I46 should be
set to 3 to operate the CPU at its maximum rated frequency.
On a Flex CPU board configured for Option 5CF with 80 MHz maximum frequency, I46 should be
set to 7 to operate the CPU at its maximum rated frequency.
On a Flex CPU board configured for Option 5EF with 160 MHz maximum frequency, I46 should be
set to 15 to operate the CPU at its maximum rated frequency.
I46 is only used at power-up/reset, so to change the operational frequency, set a new value of I46,
issue a SAVE command to store this value in non-volatile flash memory, then issue a $$$ command
to reset the controller.
To determine the frequency at which the CPU is actually operating, issue the TYPE command to the
PMAC. The PMAC will respond with five data items, the last of which is CLK Xn, where n is the
multiplication factor from the 20 MHz crystal frequency (not 10 MHz). n should be equivalent to
(I46+1)/2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board. n
will be “2” for 40 MHz operation, 4 for 80 MHz operation, and 8 for 160 MHz operation.
• If the CPU’s operational frequency has been determined by (a non-zero setting of) I46, the serial
communications baud rate is determined at power-up/reset by variable I54 alone according to the
following table:
Flex CPU Piggyback Board Hardware Reference
8 Operation of the Flex CPU
I54 Baud Rate I54 Baud Rate
0 600 8 9600
1 900 9 14,400
2 1200 10 19,200
3 1800 11 28,800
4 2400 12 38,400
5 3600 13 57,600
6 4800 14 76,800
7 7200 15 115,200
Note that these values can be different from those used on PMAC2 boards with jumper-set CPU
frequencies (see below).
• If the saved value of I46 is 0, so the CPU’s operational frequency is determined by jumper settings,
then the serial baud rate is determined by a combination of the setting of jumpers E44-E47 and the
CPU frequency on a PMAC(1) board, as shown in the following table. These settings maintain
backward compatibility.
E44 E45 E46 E47 Baud Rate
for
20MHz
Baud Rate
for
40MHz
Baud Rate
for
60MHz
N ON ON ON Disabled Disabled Disabled
OFF ON ON ON 300 600 900
ON OFF ON ON 400* 800* 1200
OFF OFF ON ON 600 1200 1800
ON ON OFF ON 800* 1600* 2400
OFF ON OFF ON 1200 2400 3600
ON OFF OFF ON 1600* 3200* 4800
OFF OFF OFF ON 2400 4800 7200
ON ON ON OFF 3200* 6400* 9600
OFF ON ON OFF 4800 9600 14400
ON OFF ON OFF 6400* 12800* 19200
OFF OFF ON OFF 9600 19200 28800
ON ON OFF OFF 12800* 25600* 38400
OFF ON OFF OFF 19200 38400 57600
ON OFF OFF OFF 25600* 51200* 76800
OFF OFF OFF OFF 38400 76800 115200
* Not an exact baud rate
Flex CPU Piggyback Board Hardware Reference
Operation of the Flex CPU 9
For a PMAC2 board with a saved value of 0 for I46, the serial baud rate is determined by the combination
of I54 and the CPU frequency on a PMAC2 board as shown in the following table. These settings
maintain backward compatibility.
I54 Baud Rate for
40 MHz CPU
Baud Rate for
60 MHz CPU
Baud Rate for
80 MHz CPU
0 600 Disabled 1200
1 900* (-0.05%) 900 1800* (-0.1%)
2 1200 1200 2400
3 1800* (-0.1%) 1800 3600* (-0.19%)
4 2400 2400 4800
5 3600* (-0.19%) 3600 7200* (-0.38%)
6 4800 4800 9600
7 7200* (-0.38%) 7200 14,400*(-0.75%)
8 9600 9600 19,200
9 14,400*(-0.75%) 14,400 28,800*(-1.5%)
10 19,200 19,200 38,400
11 28,800*(-1.5%) 28,800 57,600*(-3.0%)
12 38,400 38,400 76,800
13 57,600*(-3.0%) 57,600 115,200*(-6.0%)
14 76,800 76,800 153,600
15 Disabled 115,200 DISABLED
* Not an exact baud rate
• With the Flex CPU, the card number (0 – 15) for serial addressing of multiple cards on a daisy-chain
serial cable is determined by variable I0, even on PMAC(1) boards. This has always been the case
for PMAC2 boards, but with other CPU boards, the card number on PMAC(1) boards has been
determined by the settings of jumpers E40 – E43. Jumpers E40 – E43 on a PMAC(1) board with the
Flex CPU still determine the “direction” of the phase and servo clocks: all of these jumpers must be
ON for the card to use its internally generated clock signals and to output these on the serial port
connector; if any of these jumpers is OFF, the card will expect to input these clock signals from the
serial port connector, and its watchdog timer will trip immediately if it does not receive these signals.
Operation as a Turbo CPU
When used as a Turbo CPU, the Flex CPU is fully compatible with older CPU designs. It does permit
higher-speed configurations (Option 5Ex at 160 MHz), which offer significantly higher performance both
due to increased operation frequency and added internal memory.
Variable I52 determines the actual operating frequency of the Turbo CPU. The operational frequency is
set to 10MHz * (I52 + 1). I52 should be set to 7 to operate an Option 5Cx board at its maximum rated
frequency of 80 MHz; it should be set to 9 to operate an Option 5Dx board at its maximum rated
frequency of 100 MHz; it should be set to 15 to operate an Option 5Ex board at is maximum rated
frequency of 160 MHz.
I52 is used only at power-up/reset, so to change the operational frequency, set a new value of I52, issue a
SAVE command to store this value in non-volatile flash memory, then issue a $$$ command to reset the
controller.
Flex CPU Piggyback Board Hardware Reference
10 Operation of the Flex CPU
Flex CPU Piggyback Board Hardware Reference
Flex CPU Board Jumper Descriptions 11
FLEX CPU BOARD JUMPER DESCRIPTIONS
E1: Watchdog Disable Jumper
E Point and
Physical Layout
Description Default
E1
Jump pin 1 to 2 to disable Watchdog timer (for test
purposes only).
Remove jumper to enable Watchdog timer.
No jumper installed
E2: Dual-Ported RAM Port Select
E Point and
Physical Layout
Description Default
E2
Jump pin 1 to 2 to access DPRAM from baseboard.
Jump pin 2 to 3 to access DPRAM through JEXP
expansion port (PMAC(1)-PC with Option 2 DPRAM
board).
Pins 2 and 3 jumpered
(with PMAC(1)-PC base
board only)
Pins 1 and 2 jumpered
(when used on all other
base boards)
E4 – E6: Power-Up/Reset Load Source
E Point and
Physical Layout
Description Default
E6
E4
Remove jumper E4;
jump E5 pin 1 to 2;
jump E6 pin 2 to 3;
to read flash IC on power-up/reset
Other combinations are for factory use only; the board
will not operate in any other configuration.
No E4 jumper installed;
E5 and E6 jump pin 1 to 2
E7: Firmware Reload Enable
E Point and
Physical Layout
Description Default
E7
Jump pin 1 to 2 to reload firmware through serial or
bus port.
Remove jumper for normal operation.
No jumper installed
Flex CPU Piggyback Board Hardware Reference
12 Flex CPU Board Jumper Descriptions
E10A, B, C: Flash Memory Bank Select
E Point and
Physical Layout
Description Default
E10A
E10C
Remove all 3 jumpers to select flash memory bank
with factory-installed firmware.
Use other configuration to select one of the 7 other
flash memory banks
No jumpers installed
Flex CPU Piggyback Board Hardware Reference
Connector Summary 13
CONNECTOR SUMMARY
J2: JEXP Expansion Port (50-pin IDC header for Delta Tau accessory boards)
J5: JTAG/OnCE Port (for factory use only)
J6: JSIO Port (for factory use only)
J7: JISP Port (for factory use only)
J8: Auxiliary Serial Port (10-pin IDC header)*
P1: Stack Connector (Internal connections to main PMAC board)
P3: Stack Connector (Internal connections to main PMAC board)
*Pinout shown in next section
Flex CPU Piggyback Board Hardware Reference
14 Connector Summary
Flex CPU Piggyback Board Hardware Reference
Connector Pinouts 15
CONNECTOR PINOUTS
J8 JRS232 (10-Pin Connector)
Front View
Pin # Symbol Function Description Notes
1 N.C. No Connect
2 DTR Bidirect Data Terminal Ready Tied to DSR
3 TXD/ Input Receive Data Host transmit data
4 CTS Input Clear to Send Host ready bit
5 RXD/ Output Send Data Host receive data
6 RTS Output Request to Send PMAC ready bit
7 DSR Bidirect Data Set Ready Tied to DTR
8 N.C. No Connect
9 GND Common PMAC Common
10 +5V Output +5VDC Supply Power supply out
The JRS232 connector provided with Option 9T on a Turbo PMAC is an auxiliary serial port that can be
used independently of the standard main serial port and other communications ports. It can be connected
with a straight-across flat cable to a DB-9 connector with the standard RS-232 pinout.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
(JTAG/OnCE)
TSI
GND
GND
GND
N.C.
N.C.
TSO
TCK
RST-
TMS
DE-
TRST-
+3.3V
WDPWR
J5
+
GND
(jisp)
(jsio)
+5V
TXD
RXD
CTS-
INIT-
GND
(.100 MOLEX)
+3.3V
N.C.
P1
J6
J7
JUMP `J6' PIN 6 TO 7
TO LOAD `isp' PART
E4
E5
E6
E1
RTS-
E7
|Link
|605-1sh2.sch
X/Y:$000000-$0107FF STANDARD MEMORY OPTION (64K)
P:$000000-$0FFFFF
X/Y:$000000-$03FFFF EXTENDED MEMORY OPTION (256K)
PRAM MEMORY P:
$040000-$0403FF User Written Phase (1K)
$000000-$00FFFF Firmware (64K)
$040400-$040BFF User Written Servo (2K)
$050000-$05FFFF Plcc Standard Memory Option (64K)
$050000-$0BFFFF Plcc Extended Memory Option (448K)
GUARD BANDING REQ'D
GND
+5V
TXD-
RXD-
CTS
RTS
DSR
DTR
(JRS232)
NOTE:
OF THE `RS232' INPUT SECTION.
TO PROVIDE `ESD' PROTECTION
N.C.
N.C.
J8
PWR WD
**POLY CAP**
GUARD BANDGUARD BAND
GUARD BAND
GUARD BAND
*DUAL FOOTPRINT*
OR
THIS PART MUST BE `MAX3232ECWE'
GUARD BAND
GUARD BANDING REQ'D
E2 1-to-2 is for DPR on base board
E2 2-to-3 is for DPR on expansion board
GUARD BAND
GUARD BAND
FOR `DSP56303PW80'
DO NOT INSTALL
FOR `DSP56303PW80'
INSTALL `F2' ONLY
FOR `DSP56309PW80'
INSTALL
DO NOT INSTALL `F2'
NOTE1:
NOTE2:
*
`VR1,C89,C90,R11,R12'
`VR1,C89,C90,R11,R12'
X/Y:$078000-$0780FF
X/Y:$078100-$0781FF
X/Y:$078200-$0782FF
X/Y:$078300-$0783FF
X/Y:$078800-$0789FF
X/Y:$078A00-$078AFF
X/Y:$078B00-$078BFF
X/Y:$078C00-$078CFF
X/Y:$078D00-$078DFF
X/Y:$078E00-$078EFF
X/Y:$078F00-$078FFF
X/Y:$078400-$0787FF
TDO
TDI
BSCAN-
TMS
TCK
X/Y:$078F00-$078FFF
X/Y:$070000-$077FFF
X/Y:$060000-$060FFF STANDARD MEMORY OPTION (4K)
X/Y:$060000-$063FFF EXTENDED MEMORY OPTION (16K)
X/Y:$060000-$06FFFF EXTENDED MEMORY OPTION (64K)
X/Y:$050000-$053FFF STANDARD MEMORY OPTION (16K)
P:$D00000-$D3FFFF (MAXIMUM OF 16 BANKS)
X/Y:$050000-$05FFFF EXTENDED MEMORY OPTION (64K)
Memory Range
AND `DSP56311GC150'
NOTE1:
NOTE2:
OR
(Request 6pf load capacitance)
(See layout instructions)
*NETLIST CHANGE*
********
********
*NETLIST CHANGE*
*NETLIST CHANGE*
*NETLIST CHANGE*
********
*NETLIST CHANGE*
*NETLIST CHANGE*
603605-322P
-
DSP563XX CPU Piggyback Board
Delta Tau Data Systems, Inc.
D
12Thursday, September 19, 2002
Title
Size Document Number Rev
Date: Sheet
of
A0
A1
A2
A3
A4
RESET- A5
A6
TRST- A7
MODD/IRQD- A8
MODC/IRQC- A9
MODB/IRQB- A10
MODA/IRQA- A11
DE- A12
TA- A13
TMS A14
TCK A15
TDO A16
TDI A17
BSC12 A19X/YP
BSC11 WR-
BSTD1 RD-
BSRD1
SC02 STD0
SC01 SRD0
Vbat D0 SCK0
RP1_9 D1 SC02
D2
PRDY D3 SIRQ-
D4
D5
D6
D7
BH0 D0 D8
BH1 D1 D9
BH2 D2 D10
BH3 D3 D11
SC02 BH4 D4 D12
A0 BA00 BHREQ- BH5 D5 D13
A1 BA01 DE- BH6 D6 D14
BH7 D7 D15
TMS A2 BA02 SRD0 BHA0 D8 D16
A3 BA03 STD0 BHA1 D9 D17
SCK0 BHA2 D10 D18
DE- A4 BA04 BB- MODD/IRQD- D11 D19
A5 BA05 BHDS- D12 D20
BHR/W D13 D21
A6 BA06 BHACK- D14 D22
A7 BA07 BRTS- BHREQ- D15 D23
A8 BA08 TMS BRXD D16
A9 BA09 BG- BTXD D17
T/R- SRD0 D18
A10 BA10 BSTD1 STD0 D19
A11 BA11 BSRD1 BOOTEN- D20
BSCK1 BRTS- D21
A12 BA12 BSC12 SCK0 D22
TXD A13 BA13 BSCK1 D23
RXD BRCLK A0
CTS- A14 BA14 PHA_A A1
RTS- A15 BA15 SER_A A2
INIT- BCTS- A3
BG- A4
A19X/YP A5
FLASHCS- A6
DRAMCS- A7 INIT-
PRAMCS- A8
CPUCLK EXTAL A9
HACK- BHACK- A10
EXTAL A11
A19X/YP BX/Y A12
WR- BWR- A13
A14
RD- BRD- A15
BA05 BA05_A A16 WDTC
A17
RD- BA06 BA06_A RD-
FLASHCS- BA07 BA07_A WR-
BA08 BA08_A
BA09 BA09_A BB-
PRAMCS-
BA10 BA10_A
WR- BA11 BA11_A
BA12 BA12_A
BA13 BA13_A
BA14 BA14_A
BA15 BA15_A
MODA/IRQA-
MODB/IRQB-
MODC/IRQC-
BOOTEN-
H0 BH0 SC01
H1 BH1 SIRQ-
H2 BH2 BTXD
H3 BH3 BSC11
H4 BH4
H5 BH5 Vbat
H6 BH6
H7 BH7
HR/W BHR/W
HDS- BHDS-
A3 LA12
A4 LA13 Vout
A5 PA16
A6 PA17
A7 PA18
A8 PA19
A9 PA20
A10 PA21
A11
A12 BBRCS-
A13 BBRAMCS-
A14 IOCS_A- BBRAMCS-
A15 IOCS_B-
A16 TRST-
A17
RD- 19.6608Mhz
WR-
PRAMCS- CS0-
DRAMCS- CS1-
FLASHCS-
CPUCLK CS2-
SEL CS3-
RESET- BSTD1 STD1
BSCAN- CS4- BSRD1 SRD1
CS00- BSCK1 SCK1
BSC12 SC12
CS04- BSC11 SC11
CS06- WAIT1- BTXD TXD
CS10- TA- BRTS- RTS-
CS12- WAIT2- BHREQ- HREQ-
CS14-
CS16-
BRCLK
VMECS-
DPRCS-
WDTC
RP1_9
INIT- 19.6608Mhz
RESET- RESET_A WDO
HA2
HA1
HA0 TXD
HR/W
HDS- STD1
HREQ- SRD1
H7 SCK1
IOCS_A- H6 SC12
BWR_A- H5 SC11
BWR- H4
H3
H2
H1
H0
WAIT2-
BRD_A-
BRD-
BRXD RXD BPHA
BCTS- CTS-
SER_A BSER
PHA_A BPHA
BHA2 HA2
IOCS_B- BHA1 HA1
BWR_B- BHA0 HA0
BWR- MODD/IRQD- IRQB-
BSER
T/R-
RESET
BRD_B-
BRD-
RESET_B
TDI
TDO
TCK
RESET-
TRST-
RESET
BSCAN-
WDO
CPUCLK
RESET-
HACK-
RXD
CTS-
IRQB-
CS4-
WAIT1-
PINIT
BA00
BA10
BA11
BA12
BA13
BA14
BA15
BA01
BA02
BA03
BA04
BA05
BA06
BA07
BA08
BA09
BX/Y
BWR-
BRD-
BA05_A
BA06_A
BA07_A
BA08_A
BA09_A
BA10_A
BA11_A
BBRCS-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A19X/YP
WR-
RD-
PRAMCS-
DRAMCS-
FLASHCS-
PA18
PA19
PA20
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
PRDY
Vout
RESET-PA21
BA15_A
BA14_A
19.6608Mhz
IOCS_B-
IOCS_A-
BA13_A
BA12_A
RESET_B
BPHA
BSER
WAIT2-
BRD_A-
BWR_A-
BRD_B-
BWR_B-
PA16
PA17
CS0-
CS1-
CS2-
CS3-
CS4-
CS00-
CS04-
CS06-
CS10-
CS12-
CS14-
CS16-
DPRCS-
VMECS-
LA13
LA12
+5V +3P3V
+3P3V
+5V
+3P3V
+5V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
+5V
+5V
+5V
+3P3V
+3P3V
+3P3V
VCCQL
+3P3V
+5V VCCQL
+5V
+3P3V
+5V
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GNDGND
GND
GND
GND
+5V
GND
GND
VCCQL
+3P3V
GND
+5V
+5VGND
C35
.01UF
RP4
3.3KSIP10C
12
3
4
5
6
7
8
9 10
+
C37
10UF
16V
(TANT)
+
C90
10UF
16V
(TANT)
5 6
C21
.01UF
R2
10K
3 4
E4
2 1
E6
2 1
D1A
LED
RED
J6
HEA_SIP 8
1
2
3
4
5
6
7
8
D2
LED
GRN
RP5C
1KSIP6I
56
R3
1K
P1
VSP01VT18A01
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
R6A
1K
R5
1K
VR1
LM1117MPX-3.3
MC33269ST-3.3
(SOT-223)
3
1
2
IN
GND
OUT
C15
.1UF
C17
.01FARAD
FM0H103Z
NEC
U27
74LCX245
(TSSOP20)
2
3
4
5
6
7
8
9
1
19
18
17
16
15
14
13
12
11
20
10
A0
A1
A2
A3
A4
A5
A6
A7
T/R
OE
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
U24A
74ACT32
(SO14)
1
2
3
C16
.1UF
U4A
74ACT14
(SO14)
1 2
U24B
74ACT32
(SO14)
4
5
6
U24C
74ACT32
(SO14)
9
10
8
U5
DS2415P
(TSOC)
1
2
34
5
6
GND
DATA
VDDVBAT
X1
X2
U2
MAX795SCSA
(SO8)
2 7
1
3
4 5
6
8
VCC RST
VOUT
ON
GND CEI
CEO
BATT
U24D
74ACT32
(SO14)
12
13
11
C20
.1UF
C70
22pf
U4B
74ACT14
(SO14)
3 4
C5
.1UF
D5
MMBD301LT1
1 3
C88
.1UF
U6
ISPLSI2064E_DECODE
(TSOP100)
86
17
29
33
55
46
57
70
59
31
80
56
3
71
73
8
4
79
90
6
84
9
82
78
54
39
60
37
20
16
11
7
15
14
66
87
65
62
10
26
1
24
52
75
27
49
2
13
25
38 51
63
74
88
41
42
48
45
47
58
32
93
67
50
61
76
77
89
22
19
28
40
99
12
64
100
43
30
35
72
34
69
97
96
95
94
98
91
92
5
83
81
21
44
53
18
23
36
68
85
H0
H1
H2
H3
H4
H5
H6
H7
HRW
HDS-
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
RD-/TDO
WR-/TCK
PRAMCS-/TMS
DRAMCS-
PROMCS-/TDI
CPUCLK/Y0
SEL
RESET-
BSCAN-
GOE0
GOE1
Y1
Y2
N.C.
N.C.
VCCIO
VCCIO
VCCIO
VCCIO
N.C.
N.C.
GND
GND
GND
GND GND
GND
GND
GND
CS16-
CS14-
CS12-
CS10-
CS06-
CS04-
CS00-
BRCLK
WDTC
N.C.
N.C.
N.C.
N.C.
N.C.
CS4-
CS3-
CS2-
CS1-
N.C.
VCC
VCC
N.C.
CS0-
IOCS1-
IOCS0-
BBRCS-
DPRCS-
VMECS-
PA21
PA20
PA19
PA18
PA17
PA16
LA13
LA12
BHDS-
BHRW
BH7
BH6
BH5
BH4
BH3
BH2
BH1
BH0
C28
.1UF
RP5A
1KSIP6I
1 2
VR2
LM1117MPX-1.8
MC33269ST-1.8
(SOT-223)
3
1
2
IN
GND
OUT
U30
PI74FCT245TL
(TSSOP20)
2
3
4
5
6
7
8
9
1
19
18
17
16
15
14
13
12
11
20
10
A0
A1
A2
A3
A4
A5
A6
A7
T/R
OE
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
J7
HSIP8NO5
1
2
3
4
6
7
8
RP7
3.3KSIP10C
12
3
4
5
6
7
8
9 10
BT1
3.6V BAT
12
U26B
74ACT14
(SO14)
3 4
C85
.1UF
U29
MAX3232ECWE
(SOL16)
2
1
3
11
12
10
9
16
6
4
5
14
13
7
8
15
+V
C1+
C1-
TXD
RXD
RTS
CTS
VCC
V-
C2+
C2-
TXD
RXD
RTS
CTS
VSS
U8
74LCX16245
(TSSOP48)
2
3
5
6
8
9
11
12
46
44
43
41
40
38
37
36
1
4
7
10
47
48
13
14
15
16
17
18
19
20
21
22
23
2425
26
27
28
29
30
31
32
33
34
35
39
42
45
B0
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GND
A9
GND
VCC
GND
TP2
SIRQ-
U26C
74ACT14
(SO14)
5 6
C86
.1UF
U26E
74ACT14
(SO14)
11 10
E5
2 1
U26D
74ACT14
(SO14)
9 8
RP5B
1KSIP6I
3 4
RP8
3.3KSIP10C
12
3
4
5
6
7
8
9 10
D2A
LED
GRN
U26A
74ACT14
(SO14)
1 2
R5A
1K
U26F
74ACT14
(SO14)
13 12
U9
NC7SZ00
(SOT23-5)
1
2
4
53
C40
.1UF
U7
74LCX16245
(TSSOP48)
2
3
5
6
8
9
11
12
46
44
43
41
40
38
37
36
1
4
7
10
47
48
13
14
15
16
17
18
19
20
21
22
23
2425
26
27
28
29
30
31
32
33
34
35
39
42
45
B0
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GND
A9
GND
VCC
GND
C27
.1UF
D3
MMBD301LT1
1 3
+
C34
1UF
35V
tant
D4
MMBD301LT1
1 3
C26
.1UF
C4
.1UF
Q1
MMBT3906LT1
(SOT23)
1
23
C83
.1UF
SOT23
Q2
2N7002
(SOT23)
3
12
C84
.1UF
C10
.1UF
C101
.1UF
C102
.1UF
J5
HEADER14_NO8
1
2
3
4
5
6
7
9
10
11
12
13
14
C76
.1UF
C82
.1UF
C87
.1UF
C105
.1UF
C100
.1UF
Y3
C-002RX
32.768Khz
TP1
GND
C103
.1UF
U4C
74ACT14
(SO14)
5 6
C72
.1UF
E2
2
3
1
RP6
10KSIP10C
1 2
3
4
5
6
7
8
910
E7
2 1
C73
.1UF
U25
PI74FCT16245ATA
(TSSOP48)
2
3
5
6
8
9
11
12
46
44
43
41
40
38
37
36
1
4
7
10
47
48
13
14
15
16
17
18
19
20
21
22
23
2425
26
27
28
29
30
31
32
33
34
35
39
42
45
B0
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GND
A9
GND
VCC
GND
C32
.1UF
C74
.1UF
C75
.1UF
J8
HEADER 10
(BOX)
1
2
3
4
5
6
7
8
9
10
C12
.1UF
C8
.1UF
C14
.1UF
U4D
74ACT14
(SO14)
9 8
C11
.1UF
U3
DS1231S
(SOL16)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
IN
N.C.
MODE
N.C.
TOL
N.C.
GND
N.C.
VCC
N.C.
NMI
N.C.
RST
N.C.
RST
R7
100
C41
.1UF
Y2
ECS-36-20-5P
3.6864Mhz
C43
.001
(0805)
POLY
C3
.1UF
F1
55FZ103N
C42
.47UF
U1
DSP56311GC150
D4
D5
E4
D11
D10
D9
D8
D7
D6
E5
E6
E7
E8
E9
E10
E11
F4
F5
F6
F7
F8
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
H5
H6
H7
H8
H9
H10
H11
J4
J5
J6
J7
J8
J9
J10
J11
K4
K5
K6
K7
K8
K9
K10
K11
L4
L5
L6
L7
L8
L9
L10
L11
E14
D12
D13
C13
C14
B13
C12
A13
B12
A12
B11
A11
C10
B10
A10
B9
A9
B8
C8
A8
B7
B6
C6
A6
N14
M13
M14
L13
L14
K13
K14
J13
J12
J14
H13
H14
G14
G12
F13
F14
E13
E12
M12
M11
N11
P11
M5
P4
N4
P3
N3
P2
N1
N2
M3
M1
M2
L1
J3
J2
J1
K2
P6
N6
P5
M6
M10
N10
M9
M8
P8
N8
N7
P7
P12
N13
P13
K3
L2
L3
G1
G2
H3
F1
G3
F3
F2
E3
E1
D2
C1
B1
C2
A2
B2
B3
A4
C3
P10
A3
D3
C4
A5
C5
B5
N9
H2
G13
C7
P14
P9
N12
L12
K12
H12
D14
C11
C9
A7
N5
D1
B4
B14
M7
H1
F12
A14
K1
E2
P1
A1
M4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
RD-
WR-
BR-
BB-
H0
H1
H2
H3
H4
H5
H6
H7
HA0
HA1
HA2
HCS-
HDS-
HRW
HACK-
HREQ-
GNDP1
GNDP
PCAP
VCCP
BCLK-
BCLK
CLKOUT
EXTAL
XTAL
CAS-
AA3
AA2
AA1
AA0
BG-
TIO2
TIO1
TIO0
SCK1
SCLK
SCK0
RXD
TXD
SC00
SC10
SRD0
STD0
SC01
SC02
SRD1
STD1
SC11
SC12
TDI
TDO
TCK
TA
TMS
DE
IRQA
IRQB
IRQC
IRQD
VCCQL
VCCQL
VCCQL
VCCQL
N.C.
VCCC
VCCC
VCCA
VCCA
VCCA
VCCD
VCCD
VCCD
VCCD
RESET
PINT
TRST
N.C.
VCCQH
VCCQH
VCCQH
N.C.
VCCS
VCCS
N.C.
N.C.
VCCH
C13
.1UF
RP1
3.3KSIP10C
12
3
4
5
6
7
8
9 10
C71
22pf
Q3
MMBT3906LT1
(SOT23)
1
23
C22
.1UF
D1
LED
RED
C23
.1UF
R6
1K
U4E
74ACT14
(SO14)
11 10
C24
.1UF
C7
.1UF
U28
MAX3100CEE
(QSOP)
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
DIN
DOUT
SCLK
CS
N.C.
IRQ
SHDN
GND X2
X1
CTS
N.C.
RTS
RX
TX
VCC
C25
.1UF
D7
1SMC5.0AT3
RP2
3.3KSIP10C
12
3
4
5
6
7
8
9 10
SOT23
Q4
2N7002
(SOT23)
3
12
D6
MMBD301LT1
1 3
C6
.1UF
Y1A
MHR13FAJ19.6608
(4 PIN SMT)
1
2 3
4
N.C.
GND CLK
VCC
U4F
74ACT14
(SO14)
13 12
C9
.1UF
+
C38
10UF
16V
(TANT)
R1
10
R4
100K
C33
.1UF
F2
55FZ103N
C29
.1UF
SOT23
Q5
2N7002
(SOT23)
3
12
C1
.1UF
E1
21
Y1B
19.6608MHz
(DIP14WIDE)
1
4
7 8
11
14
N.C.
GND
GND CLK
CLK
VCC
+
C89
10UF
16V
(TANT)
R8
330
C2
.1UF
C104
.1UF
RP9A
330SIP8I
1 2
C36
.1UF
RP3
10KSIP10C
1 2
3
4
5
6
7
8
910
7 8
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Delta Tau PMAC MINI PCI Reference guide

Delta Tau
Brand
Delta Tau
Model
PMAC MINI PCI
Type
Reference guide
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