Intel CONTROLLERS 413808 User manual

7.3.1.1 Immediate Data Transfer ....................................................98
7.3.1.2 Split Response Termination................................................99
7.3.2.1 Outbound Writes that are not MSI (Message Signaled Inter-
rupts)100
7.3.2.2 MSI Outbound Writes........................................................100
7.3.5.1 Immediate Data Transfer ..................................................101
7.3.5.2 Split Response Termination..............................................101
7.3.9.1 Conventional PCI Mode ....................................................104
7.3.9.2 PCI-X Mode.......................................................................105
7.4.1.1 Immediate Data Transfer ..................................................107
7.4.1.2 Split Response Termination..............................................107

7.5.3.1 Uncorrectable Address Errors...........................................110
7.5.3.2 Internal Bus Master-Abort.................................................110
7.6.3.1 Internal Bus Master Abort..................................................112
7.6.3.2 Internal Bus Target Abort..................................................112
7.6.3.3 Inbound EROM Memory Write..........................................112
7.9.1.1 Inbound Write Request......................................................115
7.9.1.2 Inbound Read Request .....................................................116
7.9.2.1 Conventional Mode ...........................................................117
7.9.2.2 PCI-X Mode.......................................................................117
7.9.3.1 Conventional Mode ...........................................................118
7.9.3.2 PCI-X Mode.......................................................................118

3.1.2.1 SRAM Memory Array Space.............................................514
3.1.2.2 Memory-Mapped Register Space......................................514
3.1.2.3 North Internal Bus Port Address Decode..........................514
3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....514
3.1.5.1 SRAM State Machine and Pipeline Queues......................514
3.1.5.2 Error Correction Logic.......................................................515

8.3.3.4.1 ECC Example Using the H-Matrix.....................................526

3.2.2.1 Start Phase .......................................................................645
3.2.2.2 Stop Phase........................................................................646
3.2.2.3 ACK/NACK........................................................................646
3.2.2.4 Wait States........................................................................646

1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’)........................765
1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’) ...
766
1.1.2.3 End Point Mode (PCIX_EP# = 0 and HS_SM# = 1)..........766
1.1.2.4 Secondary Clock Outputs..................................................767

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