Texas Instruments TMS320DM646x User manual

Brand: Texas Instruments

Model: TMS320DM646x

Type: User manual

TMS320DM646x DMSoCEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)Module

User's Guide

Literature Number: SPRUEQ6December 2007

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Contents

Preface .............................................................................................................................. 101 Introduction .............................................................................................................. 121.1 Purpose of the Peripheral ..................................................................................... 121.2 Features ......................................................................................................... 121.3 Functional Block Diagram ..................................................................................... 131.4 Industry Standard(s) Compliance Statement ............................................................... 142 Architecture .............................................................................................................. 142.1 Clock Control .................................................................................................... 142.2 Memory Map .................................................................................................... 152.3 Signal Descriptions ............................................................................................. 152.4 Ethernet Protocol Overview ................................................................................... 192.5 Programming Interface ......................................................................................... 202.6 EMAC Control Module ......................................................................................... 312.7 MDIO Module ................................................................................................... 342.8 EMAC Module ................................................................................................... 382.9 Media Independent Interface (MII) ........................................................................... 412.10 Packet Receive Operation ..................................................................................... 452.11 Packet Transmit Operation .................................................................................... 502.12 Receive and Transmit Latency ............................................................................... 502.13 Transfer Node Priority .......................................................................................... 512.14 Reset Considerations .......................................................................................... 512.15 Initialization ...................................................................................................... 522.16 Interrupt Support ................................................................................................ 562.17 Power Management ............................................................................................ 602.18 Emulation Considerations ..................................................................................... 603 EMAC Control Module Registers ................................................................................. 613.1 EMAC Control Module Identification and Version Register (CMIDVER) ................................ 613.2 EMAC Control Module Software Reset Register (CMSOFTRESET) .................................... 623.3 EMAC Control Module Emulation Control Register (CMEMCONTROL) ................................ 623.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) ........................................ 633.5 EMAC Control Module Receive Threshold Interrupt Enable Register(CMRXTHRESHINTEN) ....................................................................................... 643.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) ............................. 643.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) ............................. 653.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) ................... 663.9 EMAC Control Module Receive Threshold Interrupt Status Register(CMRXTHRESHINTSTAT) .................................................................................... 673.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) ........................... 673.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) .......................... 683.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) .................... 693.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) ................ 703.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) ............... 704 MDIO Registers ......................................................................................................... 714.1 MDIO Version Register (VERSION) ......................................................................... 714.2 MDIO Control Register (CONTROL) ......................................................................... 72

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4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 734.4 PHY Link Status Register (LINK) ............................................................................. 734.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 744.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 754.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 764.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................. 774.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ................ 784.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......... 794.11 MDIO User Access Register 0 (USERACCESS0) ......................................................... 804.12 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................... 814.13 MDIO User Access Register 1 (USERACCESS1) ......................................................... 824.14 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 835 Ethernet Media Access Controller (EMAC) Registers ..................................................... 845.1 Transmit Identification and Version Register (TXIDVER) ................................................. 875.2 Transmit Control Register (TXCONTROL) .................................................................. 875.3 Transmit Teardown Register (TXTEARDOWN) ............................................................ 885.4 Receive Identification and Version Register (RXIDVER) .................................................. 895.5 Receive Control Register (RXCONTROL) .................................................................. 895.6 Receive Teardown Register (RXTEARDOWN) ............................................................. 905.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .................................... 915.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................... 925.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................ 935.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................... 945.11 MAC Input Vector Register (MACINVECTOR) ............................................................. 955.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .............................................. 955.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................... 965.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................... 975.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ................................................. 985.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................... 995.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..................................... 1005.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ................................... 1005.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ................................................. 1015.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ........................................... 1015.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .......... 1025.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................... 1055.23 Receive Unicast Clear Register (RXUNICASTCLEAR) .................................................. 1065.24 Receive Maximum Length Register (RXMAXLEN) ....................................................... 1075.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................. 1075.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .................. 1085.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) ....................... 1085.28 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER) .............................. 1095.29 MAC Control Register (MACCONTROL) .................................................................. 1105.30 MAC Status Register (MACSTATUS) ...................................................................... 1125.31 Emulation Control Register (EMCONTROL) .............................................................. 1145.32 FIFO Control Register (FIFOCONTROL) .................................................................. 1145.33 MAC Configuration Register (MACCONFIG) .............................................................. 1155.34 Soft Reset Register (SOFTRESET) ........................................................................ 1155.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ....................................... 116

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5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 1165.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 1175.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 1175.39 Back Off Test Register (BOFFTEST) ....................................................................... 1185.40 Transmit Pacing Algorithm Test Register (TPACETEST) ............................................... 1185.41 Receive Pause Timer Register (RXPAUSE) .............................................................. 1195.42 Transmit Pause Timer Register (TXPAUSE) .............................................................. 1195.43 MAC Address Low Bytes Register (MACADDRLO) ...................................................... 1205.44 MAC Address High Bytes Register (MACADDRHI) ...................................................... 1215.45 MAC Index Register (MACINDEX) ......................................................................... 1215.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP) ............................ 1225.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP) ............................ 1225.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ........................................... 1235.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) ........................................... 1235.50 Network Statistics Registers ................................................................................. 124Appendix A Glossary ...................................................................................................... 133

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List of Figures

1 EMAC and MDIO Block Diagram ........................................................................................ 132 Ethernet Configuration—MII Connections .............................................................................. 153 Ethernet Configuration—GMII Connections ............................................................................ 174 Ethernet Frame Format .................................................................................................... 195 Basic Descriptor Format ................................................................................................... 206 Typical Descriptor Linked List ............................................................................................ 217 Transmit Buffer Descriptor Format ....................................................................................... 248 Receive Buffer Descriptor Format ........................................................................................ 279 EMAC Control Module Block Diagram .................................................................................. 3110 MDIO Module Block Diagram ............................................................................................. 3411 EMAC Module Block Diagram ............................................................................................ 3812 EMAC Control Module Interrupt Logic Diagram ........................................................................ 5613 EMAC Control Module Identification and Version Register (CMIDVER) ............................................ 6114 EMAC Control Module Software Reset Register (CMSOFTRESET) ................................................ 6215 EMAC Control Module Emulation Control Register (CMEMCONTROL) ............................................ 6216 EMAC Control Module Interrupt Control Register (CMINTCTRL) ................................................... 6317 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) ................. 6418 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) ......................................... 6419 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) ........................................ 6520 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) .............................. 6621 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) .............. 6722 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) ...................................... 6723 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) ...................................... 6824 EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) ............................ 6925 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) ............................ 7026 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) ........................... 7027 MDIO Version Register (VERSION) ..................................................................................... 7128 MDIO Control Register (CONTROL) ..................................................................................... 7229 PHY Acknowledge Status Register (ALIVE) ............................................................................ 7330 PHY Link Status Register (LINK) ......................................................................................... 7331 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ........................................ 7432 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ...................................... 7533 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................... 7634 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................. 7735 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................... 7836 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ..................... 7937 MDIO User Access Register 0 (USERACCESS0) ..................................................................... 8038 MDIO User PHY Select Register 0 (USERPHYSEL0) ................................................................ 8139 MDIO User Access Register 1 (USERACCESS1) ..................................................................... 8240 MDIO User PHY Select Register 1 (USERPHYSEL1) ................................................................ 8341 Transmit Identification and Version Register (TXIDVER) ............................................................. 8742 Transmit Control Register (TXCONTROL) .............................................................................. 8743 Transmit Teardown Register (TXTEARDOWN) ........................................................................ 8844 Receive Identification and Version Register (RXIDVER) ............................................................. 8945 Receive Control Register (RXCONTROL) .............................................................................. 8946 Receive Teardown Register (RXTEARDOWN) ........................................................................ 9047 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................................ 9148 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................. 9249 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................................ 9350 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ...................................................... 9451 MAC Input Vector Register (MACINVECTOR) ......................................................................... 9552 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .......................................................... 95

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53 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 9654 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 9755 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 9856 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 9957 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 10058 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 10059 MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 10160 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 10161 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...................... 10262 Receive Unicast Enable Set Register (RXUNICASTSET) .......................................................... 10563 Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 10664 Receive Maximum Length Register (RXMAXLEN) ................................................................... 10765 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 10766 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 10867 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) ..................................... 10868 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) ............................................ 10969 MAC Control Register (MACCONTROL) .............................................................................. 11070 MAC Status Register (MACSTATUS) .................................................................................. 11271 Emulation Control Register (EMCONTROL) .......................................................................... 11472 FIFO Control Register (FIFOCONTROL) .............................................................................. 11473 MAC Configuration Register (MACCONFIG) ......................................................................... 11574 Soft Reset Register (SOFTRESET) .................................................................................... 11575 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 11676 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 11677 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 11778 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 11779 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 11880 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 11881 Receive Pause Timer Register (RXPAUSE) .......................................................................... 11982 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 11983 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 12084 MAC Address High Bytes Register (MACADDRHI) .................................................................. 12185 MAC Index Register (MACINDEX) ..................................................................................... 12186 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) .......................................... 12287 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) .......................................... 12288 Transmit Channel nCompletion Pointer Register (TX nCP) ......................................................... 12389 Receive Channel nCompletion Pointer Register (RX nCP) ......................................................... 12390 Statistics Register ......................................................................................................... 124

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List of Tables

1 EMAC and MDIO Signals for MII Interface ............................................................................. 162 EMAC and MDIO Signals for GMII Interface ........................................................................... 173 Ethernet Frame Description ............................................................................................... 194 Basic Descriptor Description .............................................................................................. 215 EMAC Control Module Interrupts ......................................................................................... 326 Receive Frame Treatment Summary .................................................................................... 487 Middle of Frame Overrun Treatment .................................................................................... 498 Emulation Control .......................................................................................................... 609 EMAC Control Module Registers ......................................................................................... 6110 EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions ..................... 6111 EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions ......................... 6212 EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions ..................... 6213 EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions ............................. 6314 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) FieldDescriptions ................................................................................................................. 6415 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) Field Descriptions .................. 6416 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Field Descriptions .................. 6517 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Field Descriptions ........ 6618 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) FieldDescriptions ................................................................................................................. 6719 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) Field Descriptions ................ 6720 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Field Descriptions ................ 6821 EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Field Descriptions ...... 6922 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) Field Descriptions ..... 7023 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) Field Descriptions ..... 7024 Management Data Input/Output (MDIO) Registers .................................................................... 7125 MDIO Version Register (VERSION) Field Descriptions ............................................................... 7126 MDIO Control Register (CONTROL) Field Descriptions .............................................................. 7227 PHY Acknowledge Status Register (ALIVE) Field Descriptions ..................................................... 7328 PHY Link Status Register (LINK) Field Descriptions .................................................................. 7329 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................. 7430 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ................ 7531 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........ 7632 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ....... 7733 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ..... 7834 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) FieldDescriptions ................................................................................................................. 7935 MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................... 8036 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions .......................................... 8137 MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................... 8238 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions .......................................... 8339 Ethernet Media Access Controller (EMAC) Registers ................................................................. 8440 Transmit Identification and Version Register (TXIDVER) Field Descriptions ....................................... 8741 Transmit Control Register (TXCONTROL) Field Descriptions ....................................................... 8742 Transmit Teardown Register (TXTEARDOWN) Field Descriptions.................................................. 8843 Receive Identification and Version Register (RXIDVER) Field Descriptions ....................................... 8944 Receive Control Register (RXCONTROL) Field Descriptions ........................................................ 8945 Receive Teardown Register (RXTEARDOWN) Field Descriptions .................................................. 9046 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions .......................... 9147 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................ 92

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48 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 9349 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 9450 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................... 9551 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ................................... 9552 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .......................... 9653 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions......................... 9754 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ...................................... 9855 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ................................ 9956 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 10057 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 10058 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 10159 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 10160 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 10261 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 10562 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 10663 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 10764 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ........................................ 10765 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 10866 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) Field Descriptions ............... 10867 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) Field Descriptions ...................... 10968 MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 11069 MAC Status Register (MACSTATUS) Field Descriptions ........................................................... 11270 Emulation Control Register (EMCONTROL) Field Descriptions .................................................... 11471 FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................ 11472 MAC Configuration Register (MACCONFIG) Field Descriptions ................................................... 11573 Soft Reset Register (SOFTRESET) Field Descriptions .............................................................. 11574 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 11675 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 11676 MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................. 11777 MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................. 11778 Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 11879 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 11880 Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 11981 Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 11982 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 12083 MAC Address High Bytes Register (MACADDRHI) Field Descriptions ............................................ 12184 MAC Index Register (MACINDEX) Field Descriptions ............................................................... 12185 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions .................... 12286 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions .................... 12287 Transmit Channel nCompletion Pointer Register (TX nCP) Field Descriptions .................................. 12388 Receive Channel nCompletion Pointer Register (RX nCP) Field Descriptions ................................... 123A-1 Physical Layer Definitions ............................................................................................... 134

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PrefaceSPRUEQ6 – December 2007

Read This First

About This Manual

This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIOmodules, a discussion of their architecture and operation, how these modules connect to the outsideworld, and the registers description for each module.

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.

SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

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Related Documentation From Texas Instruments

SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

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1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

User's GuideSPRUEQ6 – December 2007

Ethernet Media Access Controller (EMAC)/Management

Data Input/Output (MDIO)

This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated intheTMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIOmodules, a discussion of their architecture and operation, how these modules connect to the outsideworld, and a description of the registers for each module.

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHYconfiguration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface thatallows efficient data transmission and reception. This custom interface is referred to as the EMAC controlmodule and is considered integral to the EMAC/MDIO peripheral.

The EMAC module is used to move data between the DM646x DMSoC and another host connected to thesame network, in compliance with the Ethernet protocol. The EMAC is controlled by the ARM CPU of thedevice; control by the DSP CPU is not supported.

The EMAC/MDIO has the following features:•Synchronous 10/100/1000 Mbps operation.•G/MII interface to the physical layer device (PHY).•Full-duplex gigabit operation (half-duplex not supported).•EMAC acts as DMA master to either internal or external device memory space.•Hardware error handling including CRC.•Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.•Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.•Ether-Stats and 802.3-Stats RMON statistics gathering.•Transmit CRC generation selectable on a per channel basis.•Broadcast frames selection for reception on a single channel.•Multicast frames selection for reception on a single channel.•Promiscuous receive mode frames selection for reception on a single channel (all frames, all goodframes, short frames, error frames).•Hardware flow control.•8K-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors withoutaffecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernetpackets without CPU intervention.•Programmable interrupt logic permits the software driver to restrict the generation of back-to-backinterrupts, which allows more work to be performed in a single call to the interrupt service routine.•TI Adaptive Performance Optimization for improved half duplex performance.•Configurable receive address matching/filtering, receive FIFO depth, and transmit FIFO depth.

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1.3 Functional Block Diagram

Configuration bus DMA memory

transfer controller

Peripheral bus

EMAC control module

EMAC module MDIO module

G/MII bus MDIO bus

EMAC/MDIO

interrupts

ARM interrupt

controller

Introduction

•No-chain mode truncates frame to first buffer for network analysis applications.•Emulation support.•Loopback mode.

Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral:•EMAC control module•EMAC module•MDIO module

The EMAC control module is the main interface between the device core processor and the EMACmodule and MDIO module. The EMAC control module contains the necessary components to allow theEMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC controlmodule incorporates 8K-byte internal RAM to hold EMAC buffer descriptors.

The MDIO module implements the 802.3 serial management interface to interrogate and control up to 32Ethernet PHYs connected to the device, using a shared two-wire bus. Host software uses the MDIOmodule to configure the autonegotiation parameters of each PHY attached to the EMAC, retrieve thenegotiation results, and configure required parameters in the EMAC module for correct operation. Themodule is designed to allow almost transparent operation of the MDIO interface, with very littlemaintenance from the core processor.

The EMAC module provides an efficient interface between the processor and the networked community.The EMAC on this device supports 10Base-T (10 Mbits/second) and 100BaseTX (100 Mbits/second) ineither half-duplex or full-duplex mode and 1000BaseT(1000 Mbits/second) in full-duplex mode, withhardware flow control and quality-of-service (QOS) support.

Figure 1. EMAC and MDIO Block Diagram

Figure 1 also shows the main interface between the EMAC control module and the CPU. The followingconnections are made to the device core:•The peripheral bus connection from the EMAC control module allows the EMAC module to read andwrite both internal and external memory through the DMA memory transfer controller.•The EMAC control module, EMAC, and MDIO all have control registers. These registers arememory-mapped into device memory space via the device configuration bus. Along with theseregisters, the control module’s internal RAM is mapped into this same range.•The EMAC and MDIO interrupts are combined into a single interrupt within the control module. Theinterrupt from the control module then goes to the ARM interrupt controller.

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1.4 Industry Standard(s) Compliance Statement

2 Architecture

2.1 Clock Control

2.1.1 MII Clocking

2.1.2 GMII Clocking

Architecture

The EMAC and MDIO interrupts are combined within the control module, so only the control moduleinterrupt needs to be monitored by the application software or device driver. The EMAC control modulecombines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through theARM interrupt controller. See Section 2.16.4 for details of interrupt multiplex logic of the EMAC controlmodule.

The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

In difference from this standard, the EMAC peripheral does not use the Transmit Coding Error signalMTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, theEMAC intentionally generates an incorrect checksum by inverting the frame CRC, so that the transmittedframe is detected as an error by the network.

This section discusses the architecture and basic function of the EMAC/MDIO module.

The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as:•2.5 MHZ at 10 Mbps•25 MHZ at 100 Mbps•125 MHZ at 1000 Mbps

All EMAC logic is clocked synchronously with the PLL peripheral clock. The MDIO clock can be controlledthrough the application software, by programming the divide-down factor in the MDIO control register(CONTROL).

In the 10/100 Mbps mode, the transmit and receive clock sources are provided from an external PHY viathe MTCLK and MRCLK pins. These clocks are inputs to the EMAC module and operate at 2.5 MHZ in 10Mbps mode and at 25 MHZ in 100 Mbps mode. The MII clocking interface is not used in 1000 Mbpsmode. For timing purposes, data is transmitted and received with reference to MTCLK and MRCLK,respectively.

In the 1000 Mbps mode, the transmit and receive clock sources for 10/100 Mbps operation are providedfrom an external PHY via the MTCLK and MRCLK pins, as in the MII clocking. For 1000 Mbps operation,the receive clock is provided by an external PHY via the MRCLK pin. For transmit in 1000 Mbps mode, theclock is sourced synchronous with the data and is provided by the EMAC to be output on the GMTCLKpin.

The EMAC module is internally clocked at 148.5 MHZ. For timing purposes, data in 10/100 Mbps mode istransmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode,receive timing is the same, but transmit is relative to GMTCLK.

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2.2 Memory Map

2.3 Signal Descriptions

2.3.1 Media Independent Interface (MII) Connections

MTCLK

MTXD(7−0)

MTXEN

MCOL

MCRS

MRCLK

MRXD(7−0)

MRXDV

MRXER

MDCLK

MDIO

Physical

layer

device

(PHY)

System

core Transformer

2.5 MHz,

25 MHz or

125 MHz

RJ−45

EMACMDIO

Architecture

The EMAC peripheral includes internal memory that is used to hold information about the Ethernetpackets received and transmitted. This internal RAM is 2K ×32 bits in size. Data can be written to andread from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptorsthat are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512Ethernet packets without CPU intervention.

The packet buffer descriptors can also be placed in the internal processor memory (L2), or in EMIFmemory (DDR). There are some tradeoffs in terms of cache performance and throughput whendescriptors are placed in the system memory, versus when they are placed in the EMAC’s internalmemory. Cache performance is improved when the buffer descriptors are placed in internal memory.However, the EMAC throughput is better when the descriptors are placed in the local EMAC RAM.

The DM646x DMSoC supports both MII interface (for 10/100 Mbps operation) and GMII interface (for10/100/1000 Mbps) operation.

Figure 2 shows a device with integrated EMAC and MDIO interfaced via a MII connection. The EMACmodule does not include a transmit error (MTXER) pin. In the case of transmit error, CRC inversion isused to negate the validity of the transmitted frame.

The individual EMAC and MDIO signals for the MII interface are summarized in Table 1 . For moreinformation, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).

Figure 2. Ethernet Configuration—MII Connections

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Architecture

Table 1. EMAC and MDIO Signals for MII Interface

Signal Type Description

MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing referencefor transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generatedby the PHY and is 2.5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation.MTXD[3-0] O Transmit data (MTXD). The transmit data pins are a collection of 4 data signals comprising 4 bits ofdata. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK and validonly when MTXEN is asserted.MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generatingnibble data for use by the PHY. It is driven synchronously to MTCLK.MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on thenetwork. It remains asserted while the collision condition persists. This signal is not necessarilysynchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in eithertransmit or receive. The pin is deasserted when both transmit and receive are idle. This signal is notnecessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing referencefor receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock isgenerated by the PHY and is 2.5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation.MRXD[3-0] I Receive data (MRXD). The receive data pins are a collection of 4 data signals comprising 4 bits ofdata. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MRCLK and validonly when MRXDV is asserted.MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins aregenerating nibble data for use by the EMAC. It is driven synchronously to MRCLK.MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods toindicate that an error was detected in the received frame. This is meaningful only during datareception when MRXDV is active.MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on thesystem. It is used to synchronize MDIO data access operations done on the MDIO pin. Thefrequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out ofthe PHY by way of an access frame consisting of start of frame, read/write indication, PHY address,register address, and data bit cycles. The MDIO pin acts as an output for all but the data bit cyclesat which time it is an input for read operations.

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2.3.2 Gigabit Media Independent Interface (GMII) Connections

MTCLK

MTXD[7−0]

MTXEN

MCOL

MCRS

MRCLK

MRXD[7−0]

MRXDV

MRXER

MDCLK

MDIO

Physical

layer

device

(PHY)

System

core

Transformer

2.5 MHz,

25 MHz,

RJ−45

EMACMDIO

GMTCLK

or 125 MHz

RFTCLK

Architecture

Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interfaceis available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.

The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbpsmode. In 10/100 Mbps modes, the GMII interface acts like an MII interface and only the lower 4 bits ofdata are transferred for each of the data buses. The individual EMAC and MDIO signals for the GMIIinterface are summarized in Figure 3 .

Figure 3. Ethernet Configuration—GMII Connections

Table 2. EMAC and MDIO Signals for GMII Interface

Signal Type Description

MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing referencefor transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clockwhen in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbpsoperation, and 25 MHZ at 100 Mbps operation.GMTCLK O GMII source synchronous transmit clock (GMTCLK). This clock is used in 1000 Mbps mode only,providing a continuous 125 MHZ frequency for transmit operations. The MTXD and MTXEN signalsare tied to this clock when in Gigabit mode. The clock is generated by the EMAC and is 125 MHZ.RFTCLK I Reference transmit clock (RFTCLK). The reference transmit clock is a continuous clock that providesthe timing reference for transmit operations in 1000 Mbps mode. This 125-MHZ clock is generatedby the PHY.MTXD[7-0] O Transmit data (MTXD). The transmit data pins are a collection of 8 data signals comprising 8 bits ofdata. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK in 10/100Mbps mode, and by GMTCLK in Gigabit mode, and valid only when MTXEN is asserted.MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generatingnibble data for use by the PHY. It is driven synchronously to MTCLK in 10/100 Mbps mode, and toGMTCLK in Gigabit mode.MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on thenetwork. It remains asserted while the collision condition persists. This signal is not necessarilysynchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

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Architecture

Table 2. EMAC and MDIO Signals for GMII Interface (continued)

Signal Type Description

MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in eithertransmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is notnecessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing referencefor receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock isgenerated by the PHY and is 2.5 MHZ at 10 Mbps operation, 25 MHZ at 100 Mbps operation and125 MHZ at 1000 Mbps operation.MRXD[7-0] I Receive data (MRXD). The receive data pins are a collection of 8 data signals comprising 8 bits ofdata. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MRCLK and validonly when MRXDV is asserted.MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins aregenerating nibble data for use by the EMAC. It is driven synchronously to MRCLK.MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods toindicate that an error was detected in the received frame. This is meaningful only during datareception when MRXDV is active.MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on thesystem. It is used to synchronize MDIO data access operations done on the MDIO pin. Thefrequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out ofthe PHY by way of an access frame consisting of start of frame, read/write indication, PHY address,register address, and data bit cycles. The MDIO pin acts as an output for everything except the databit cycles, when the pin acts as an input for read operations.

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2.4 Ethernet Protocol Overview

2.4.1 Ethernet Frame Format

Preamble SFD Destination Source Len Data

7 1 6 6 2 46−1500 4

FCS

Number of bytes

Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC)

Architecture

Ethernet provides an unreliable, connection-less service to a networking application. A brief overview ofthe Ethernet protocol is given in the following subsections. For in-depth information on the Carrier SenseMultiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multipleaccess protocol, see the IEEE 802.3 standard document.

All the Ethernet technologies use the same frame structure. The format of an Ethernet frame is shown inFigure 4 and described in Table 3 . The Ethernet packet, which is the collection of bytes representing thedata portion of a single Ethernet frame on the wire, is shown outlined in bold. The Ethernet frames are ofvariable lengths, with no frame smaller than 64 bytes or larger than RXMAXLEN bytes (header, data, andCRC).

Figure 4. Ethernet Frame Format

Table 3. Ethernet Frame Description

Field Bytes Description

Preamble 7 Preamble. These 7 bytes have a fixed value of 55h and serve to wake up the receivingEMAC ports and to synchronize their clocks to that of the sender’s clock.SFD 1 Start of Frame Delimiter. This field with a value of 5Dh immediately follows the preamblepattern and indicates the start of important data.Destination 6 Destination address. This field contains the Ethernet MAC address of the EMAC port forwhich the frame is intended. It may be an individual or multicast (including broadcast)address. When the destination EMAC port receives an Ethernet frame with a destinationaddress that does not match any of its MAC physical addresses, and no promiscuous,multicast or broadcast channel is enabled, it discards the frame.Source 6 Source address. This field contains the MAC address of the Ethernet port that transmits theframe to the Local Area Network.Len 2 Length/Type field. The length field indicates the number of EMAC client data bytescontained in the subsequent data field of the frame. This field can also be used to identifythe type of data the frame is carrying.Data 46 to Data field. This field carries the datagram containing the upper layer protocol frame, that is,(RXMAXLEN - 18) IP layer datagram. The maximum transfer unit (MTU) of Ethernet is (RXMAXLEN - 18)bytes. This means that if the upper layer protocol datagram exceeds (RXMAXLEN - 18)bytes, then the host has to fragment the datagram and send it in multiple Ethernet packets.The minimum size of the data field is 46 bytes. This means that if the upper layer datagramis less then 46 bytes, the data field has to be extended to 46 bytes by appending extra bitsafter the data field, but prior to calculating and appending the FCS.FCS 4 Frame Check Sequence. A cyclic redundancy check (CRC) is used by the transmit andreceive algorithms to generate a CRC value for the FCS field. The frame check sequencecovers the 60 to (RXMAXLEN - 4) bytes of the packet data. Note that this 4-byte field mayor may not be included as part of the packet data, depending on how the EMAC isconfigured.

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2.4.2 Ethernet’s Multiple Access Protocol

2.5 Programming Interface

2.5.1 Packet Buffer Descriptors

Architecture

Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, whenan EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier SenseMultiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates inhalf-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium,since there are exactly two ports on the local network.

Each port runs the CSMA/CD protocol without explicit coordination with the other ports on the Ethernetnetwork. Within a specific port, the CSMA/CD protocol works as follows:1. The port obtains data from upper layers protocols at its node, prepares an Ethernet frame, and putsthe frame in a buffer.2. If the port senses that the medium is idle it starts to transmit the frame. If the port senses that thetransmission medium is busy, it waits until it senses no signal energy (plus an Inter-Packet Gap time)and then starts to transmit the frame.3. While transmitting, the port monitors for the presence of signal energy coming from other ports. If theport transmits the entire frame without detecting signal energy from other Ethernet devices, the port isdone with the frame.4. If the port detects signal energy from other ports while transmitting, it stops transmitting its frame andinstead transmits a 48-bit jam signal.5. After transmitting the jam signal the port enters an exponential backoff phase. Specifically, whentransmitting a given frame, after experiencing a number of collisions in a row for the frame, the portchooses a random value that is dependent on the number of collisions. The port then waits an amountof time that is multiple of this random value, and returns to step 2.

The buffer descriptor is a central part of the EMAC module and is how the application software describesEthernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptorformat is shown in Figure 5 and described in Table 4 .

For example, consider three packets to be transmitted, Packet A is a single fragment (60 bytes), Packet Bis fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes). Thelinked list of descriptors to describe these three packets is shown in Figure 6 .

Figure 5. Basic Descriptor Format

Bit Fields

Word

Offset 31 16 15 0

0 Next Descriptor Pointer1 Buffer Pointer2 Buffer Offset Buffer Length3 Flags Packet Length