RemoTI Network Processor Developer's Guide SWRU223A
1 Copyright 2009 Texas Instruments, Inc. All rights reserved.
TABLE OF CONTENTS
1 REFERENCES.......................................................................................................................................................................3
2 INTRODUCTION..................................................................................................................................................................4
2.1 PURPOSE ..........................................................................................................................................................................4
2.2 SCOPE ..............................................................................................................................................................................4
3 REMOTI NETWORK PROCESSOR APPLICATION.....................................................................................................4
3.1 FEATURES ........................................................................................................................................................................4
3.2 BUILD CONFIGURATIONS...................................................................................................................................................4
3.3 FILES................................................................................................................................................................................ 8
3.4 ARCHITECTURE ..............................................................................................................................................................11
4 BAUD RATE........................................................................................................................................................................12
5 UART WAKE UP MECHANISM......................................................................................................................................13
6 ADDING NEW NETWORK PROCESSOR INTERFACE COMMANDS....................................................................15
7 UART VS. SPI......................................................................................................................................................................17
8 FLASH PAGE MAP AND MEMORY MAP.....................................................................................................................17
9 STACK AND HEAP............................................................................................................................................................21
10 IEEE ADDRESS..............................................................................................................................................................24
11 NETWORK LAYER CONFIGURATION....................................................................................................................27
12 SERIAL BOOT LOADER..............................................................................................................................................28
12.1 OVERVIEW OF THE SERIAL BOOT LOADER DEMO .............................................................................................................. 28
12.2 SERIAL BOOT LOADING COMMANDS ................................................................................................................................28
12.2.1 Handshake Command...........................................................................................................................................29
12.2.2 Write Command....................................................................................................................................................29
12.2.3 Read Command ....................................................................................................................................................29
12.2.4 Enable Command.................................................................................................................................................30
12.3 BOOT LOADING SEQUENCES ............................................................................................................................................30
12.4 NETWORK PROCESSOR CONFIGURATION FOR SERIAL BOOT LOADING................................................................................ 32
12.5 LOCK BIT PAGE ...............................................................................................................................................................32
13 DMA, PERIPHERAL IO AND TIMERS......................................................................................................................33
14 RF FRONTEND CHIP CONNECTION CONFIGURATION....................................................................................33
15 GENERAL INFORMATION.........................................................................................................................................35
15.1 DOCUMENT HISTORY......................................................................................................................................................35
16 ADDRESS INFORMATION..........................................................................................................................................35
17 TI WORLDWIDE TECHNICAL SUPPORT...............................................................................................................35