Pico Communications E-14 User manual

Brand: Pico Communications

Model: E-14

Type: User manual

PicoE14HardwareReference www.picocomputing.com PicoComputing,Inc.

 (206)283‐2178 150NickersonStreet.Suite311

 Seattle,WA98109

E‐14



HardwareTechnicalReference

Release:14.1.8.12

HardwareVersion:F

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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Contents:

ProductOverview 4

QuickReferenceDatasheet 5

ElectricalSpecifications 6

SystemArchitecture 7

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Features

FieldProgrammableGateArray 8

Power‐PC™Processor 9

CPLDTurboLoader 10

Tri‐ModeEthernetInterface 11

FlashMemory 12

DDR2Memory 13

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I/OInterfaces

AnalogInterface 14

RS‐232SerialInterface 15

DigitalPeripheralInterface 16

CardBusInterface 17

DigitalBusInterface 18

JTAGDebugInterface 19

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Appendices

A–PeripheralI/OConnectorInformation 20

B–CardBusConnectorInformation 21

C–FPGAPinout 22

D–CPLDPinout 38

E–StandardPartNumberListing 30

F–Errata 32

G–FPGAPerformanceEnhancements 33

E–AnalogInterfaceSelectionGuide 34

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RevisionHistory 35

LegalNotices 36

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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ProductOverview:

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ThePicofamiliesofproductarerevolutionaryembeddedplatforms.Withperformancethatoften

exceedsmodernmicrocomputers,ashockinglysmallformfactor,andnominalpowerconsumption

thatislessthanonewatt,thePicofamilyofproductstakescomputingtoawholenewlevel.

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ThePicoE‐14isbasedontherevolutionaryVirtex‐4chip.Thisdevicehastheperformanceandpower

consumptionofacustomchip(ASIC),butiscompletelyreconfigurable!ThePicoE‐14EP(Embedded

Processor)canbeconfiguredwitheithertheFX20FX40orFX60Virtex4FPGA.

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Advanceduserswillenjoytheopensourcedevelopmentkitsthatallowabsolutecontroloverthe

hardware.ThosewhodesireahighlevelprogrammingenvironmentcanuseSimulink®toimplement

customalgorithmsinhardwarewithjusttheclickofabutton.ImpulseC™supportisalsoincludedfor

rapidfirmwaredevelopmentintheCprogramminglanguage.Boardsupportpackagesareavailablefor

operatingsystemssuchasLinuxorμC/OS.

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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Pico E-14 EP Quick Reference Datasheet

Core Technologies

- Virtex-4 FPGA

- PowerPC-405 450 MHz (680 DMIPS)

- 256 MB RAM

- 64 MB FPGA Image Flash

- Analog to Digital and Digital to Analog

Converters

- Gigabit Ethernet (1000/100/10 Mbps)

- 2 RS-232 Serial Ports

- JTAG Hardware / Software Debugging

- 54-bit High Speed Digital I/O Bus

- 16-bit external digital I/O port

- Standalone operation

- JTAG hardware / software debugging

- Open source

Mechanical Specification

- Cardbus Type II

- Stainless Steel Case

- Temperature Range: 0C to +85C

FPGA Performance

- DES > 16 Gbps / 250M Keys / second

- RC4 > 10 Gbps / 12M Keys / second

- > 16 Billion Multiply and Accumulates / second

Typical Applications

- Application on Card (AOC) systems. Vendors

sell their applications packaged with the

platform that they run on.

- Hybrid embedded processor / DSP applications

- Encryption / decryption

- Security algorithms and testing

- Software radio component

- Embedded control systems

- Embedded web servers / applications

- Weight and size constrained environments such

as UAVs, surveillance systems and

environmental monitoring devices.

- Complete development environment for laptop

computers. Ideal for rapid prototyping and

classroom environments.

Analog Capabilities

- 1 High Speed Analog to Digital

- 8 Bit @ 105MS/Sec

- 10 Bit @ 80MS/Sec

- 1 High Speed Digital to Analog

- 8 Bit @ 210MS/Sec

- 10 Bit @ 165MS/Sec

Features

- Complete Cardbus host interface capable of bus

speeds up to 1 Gbps

- DSP capability of the Virtex-4 FPGA

- Bus interface re-configurable to fit other bus nterface

protocols

- Works with Xilinx standard tool set (ISE, EDK, and

Platform SDK)

- Works with Starbridge Systems’ Viva, a graphical

development and modeling tool set designed for

parallel computing and IP portability

- Pico Flash utility for FPGA image and software

executable management. Runs on Windows, Linux,

and Apple Hosts

- Available plug-in for Matlab

- Pico DSP Accelerator / Xilinx System Generator plug-

in for Simulink available

- Available complete board support packages for

PowerPC embedded computing with Xilinx EDK

- Available port of RTCA DO-178B compliant UCOS-II

deterministic / pre-emptive kernel

- Available Linux port

- Available port of Green Hills Integrity RTOS

- Dynamic image swapping: unique design allows for

many FPGA images and user software images to be

stored on the PICO E-14's flash memory at one

time. FPGA and software images are associated

(paired). This allows image sets to be swapped

dynamically. Applications can store data in SDRAM.

This data can then be used by subsequent image

sets seamlessly.

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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PicoE‐14ElectricalSpecifications

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 Minimum Nominal Maximum

DCInputVoltage 3.15V 3.3‐5.0V 5.5V

PowerConsumption10W*

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RecommendedTemperatureRange 0°C 10°C 70°C

MaximumAllowableTemperatureRange 0°C 85°C

ContinuousStorageTemperatureRange‐50°C 30°C 125°C

RelativeHumidity(Non‐Condensing) 0% 95%

Note:Ifthecarddrawsmorethan10wattsthepowersuppliescutoffandresetthe

card

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PowerConsumption

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ThegraphbelowhaspowerconsumptionrunningPicoComputing’sprimaryboot.Theprimaryboot

haseverythingrunningonthecard,exceptD/A,A/D,andEthernet.Thelowercharthaspower

consumptionnumbersforprimarybootimagewith10/100andGigaBitethernetrunning.

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WithGigaBitEthernet

 Voltage(V) Current(A)

 Power(W)

FX20 3.3 1.0 3.3

FX60 3.3 1.3 4.3

  

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NOTE:TheCardBusslotisratedto3.3W,andbecauseofthehigherpowerrequirementoftheFX60,

wedonotrecommendrunningtheFX60inthelaptop.

WithoutEthernet

 Voltage(V) Current(A) Power(W)

FX20 3.3 0.7 2.31

FX60 3.3 0.8 2.64

  

With10/100Ethernet

 Voltage(V) Current(A) Power(W)

FX20 3.3 0.8 2.64

FX60 3.3 1.0 3.3

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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SystemArchitecture

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AtthecoreofthePicoE‐14isaVirtex‐4FPGA.TheFPGAcanbedynamicallyconfiguredtoperformany

numberofspecializedtaskssuchas:protocolprocessing,encryption,orcomplexmathematical

functions.EmbeddedsystemsbenefitfromtheintegratedPower‐PC™processoravailable ontheEP

seriescards.

DDR2 RAM Flash ROM

Gigabit Ethernet

Analog Converters

Serial Transceiver

JTAG

GPIO

RAM

DSP

Slices

I/O

Figure 1

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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FieldProgrammableGateArray

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ThecoreofthePicoE‐14isahighperformanceVirtex‐4FPGA.IncludedintheFPGAaretheFPGA

Fabric,aPower‐PC™processor,ultrahigh‐speedDSPslicesandDDR2RAM.

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FPGAFabric:

The“Fabric”ofanFPGAcomprisesanarrayoflogicelementsthatcan

beconnectedinvirtually

unlimitedpatterns.Thesepatternsoflogicelementscanbeusedtoperformbasicmathematical

functionssuchasadditionandsubtraction,orcanbegroupedtogethertoperformcomplexfunctions

likeFastFourierTransforms.Logicelementscanevenbeconnectedtocreateacustomsoftprocessor.

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TheadvantageoftheFPGAisthattheinternallogiccanbeoptimizedforaspecificapplication.FPGAs

arealsoabletoexecuteoperationsinparallel,notbeinglimitedbysequentialexecutionlikea

traditionalprocessor.FPGAoperationscanbeexecutedinaparallel,pipelinedorevenan

asynchronousmanner.TheFPGAallowsincredibleapplicationspeedwithverylowpower

consumption.Yourimaginationisreallythelimit.

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DSPSlice:

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EmbeddedwithintheFPGAarespecialareasthataredesignedtofacilitatehighspeed“digitalsignal

processing.”TheseareasarecalledDSPslices.TheDSPslicecanbeconfiguredinavarietyofdifferent

ways.ForexampleoneDSPslicecanbeconfiguredtobeonetapofanFIRfilter.DSPslicesarefully

pipelinedandfeatureincrediblespeed.WhenconfiguredforFIRfilteringtheDSPslicehasa

guaranteedperformanceof500MHzwithalatencyofonecycle.An18x18multiplyandaccumulate

alsorunsat250MHzwithalatencyoftwocycles.Smallerdatawidthsallowhigherclockspeeds.

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FPGAResources:

FreeFPGACores www.opencores.org

Virtex‐4Website www.xilinx.com/virtex4

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E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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PowerPC™Processor

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PPC405x3ProcessorIntroduction:

FPGAsarerenownedfortheirabilitytoprocessparallellogic,buttheytypicallyhaveahardtime

emulatingahighperformanceprocessor.TogetthebestofbothworldstheVirtex‐4™featuresan

embeddedPowerPCProcessor.SincetheprocessorsharesthesamedieastheFPGAitseamlessly

interfaceswiththeFPGAfabric.

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AnewfeatureoftheVitex‐4FPGAistheadditionofanauxiliaryprocessorinterface.TheAPUisthe

highestspeedinterfacebetweenthePower‐PC™processorandtheFPGAfabric.Uptofourcustom

instructionsmaybeimplementedintheFPGA,whichareaccessiblefromthePower‐PC™.

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BoardsupportpackagesarecurrentlyavailableforμC/OS,LinuxandIntegrity.Boardsupportsource

codeisavailableopensourceundertheGPL.

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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CPLDTurboLoader

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ACPLD(ComplexProgrammableLogicDevice)isasmallerversionofanFPGA(describedabove)with

permanentFlashstoragebuiltin.ThePicoE‐14containsoneCPLDthatloadsandreconfiguresthe

FPGA.ThePicofirmwareguidedescribeshowtoaccesstheCPLDImageManager.



CPLDResources:

XilinxCPLDWebsite www.xilinx.com/cpld

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E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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Tri‐ModeEthernetInterface

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ThePicoE‐14featurestheMarvellAlaskaseries88E1111tri‐modeEthernettransceiver.OnEPseries

partstheMAC(Middleaccesscontroller)isimplementedontheFPGAdie.OnLOseriespartstheMAC

mustbeimplementedinfirmware.CommunicationbetweentheMACandPHYtakesplaceoveran

industry

standardMII/GMIIinterface.



TheEthernettransceiverfeatures10/100/1000full/halfduplexoperation.Itwillautomatically

configurethephysicalinterfaceontheflyforcrossoverorstraightthroughoperation.ThePHYcan

evenautomaticallycorrectforcommonwiringmistakes.ThePHYhasabuiltinTimeDomain

Reflectometerthatcandiagnosecable

problemsandpinpointtheirdistanceawayfromthe

transceiver.

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IncontrasttothePicoE‐12,theEthernetinterfaceonthePicoE‐14ismagneticallyisolatedallowing

directconnectionstoanindustrystandardhuborswitch.



TheMarvell88E1111istheonlychiponthePicoE‐14thatrequiresanNDAforaccesstothe

datasheets.Ifyouareinterestedinsomeoftheadvancedfeaturesnotsupportedbythenativedriver,

contactPicoComputingforassistanceinobtaininganNDAfromMarvell.Usersarewarnednotto

contactMarvelldirectly.



EthernetResources:

Marvell88E1111Webpage http://www.marvell.com/products/transceivers/singleport/88e1111.jsp

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E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.

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FlashMemory



ThePicoE‐14comesequippedwithatleast64megabytesofFlashROM.TheFlashROMisdividedinto

512sectorsthatcanbeerasedindependently.MostofthespaceontheROMisreservedfortheuser.



TheFlashROM’saddressbuscanbecontrolledbyeithertheTurboLoader

ortheFPGA,butnotboth.

Duringpower‐uporreboot,theTurboLoaderisincontroloftheFlashROMAddressbus.Atallother

timestheFPGAisincontroloftheaddressbus.



Figure2



TypicalFlashROMAllocationTable:



Byteaddresses Description FlashSectors

0x00000000‐0x0000FFFF TupleDataandconfigurationmanagement 0

0x00010000‐0x0006FFFF PrimaryFPGAImage 1‐6

0x000A0000‐0x000FFFFF BackupFPGAImage 7‐12

0x000D0000‐0x0012FFFF SecondaryImageincludingbootloader 13‐19

0x00140000‐0x01FFFFFF OtherFPGAimages,executablesanddatafiles 20‐511



TheFlashROMhasasimple,openfilesystemthatallowstheusertostoreFPGAimages,ELFbinary

files,orotherdata.TheprimaryimageisusedtoboottheFPGAinitially,andthebackupimageisonly

invokediftheprimaryimagefailstoloadcorrectly.ExecutablefilesareinELFformatandareloadedby

aloaderwithinthesecondaryimage.Theprimaryimagecaneitherloadthesecondaryimageorpause

forthePCtoaccessandmanagethefilesystem.



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





DDR2Memory



ThePicoE‐14comesequippedwith256MBofPC‐266DDR2memory.Therearefour256Mbchips

eachwith16bitdatapathsthataregroupedintotwo32bitbanks.From0°Cto+95°C,theramcanrun

at266MHz.Foroperationattemperaturesbelow0°C,specialfirmwarewithreducedramtimingsis

required.Thetemperaturecompensatedself‐refreshmodemustbedisabledbelow‐20°C.



16x16

(MSBs)

16x16

(LSBs)

FPGA

Bank 1

Bank 2

16x16

(MSBs)

16x16

(LSBs)



Figure3

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





AnalogInterface(Optional)



ThePicoE‐14alsocomesequippedwithtwohigh‐speedanalogconverterseachcapableof14‐bit

resolution.Bydefault,bothanalogconvertersarepowereddownuntilthesleeplinesaredrivenlow

andtheamplifierlinesaredrivenhighbytheFPGA.Bothconvertersarecapacitivelycoupledwithpull‐

downresistorsontheoutputtofilteroutanyDCsignalcomponents.Bothamplifiersareconfigured

forminimumnoiseandunitygain.



8‐Bit,80MSPSAnalog‐to‐DigitalConverter(ADC)*



TheADCisconfiguredtoutilizetheinternal1.0Vreferencevoltageandmaximumfullscaleinput,

givingita2Vpk‐pkinput.Currently,theADCissetuptoacceptinputvoltagesbetween0Vand2V.

Clockmodesandinputdataformatissetbythesystemutilizingconfigurationpinsavailabletothe

FPGA.



8‐Bit,165MSPSDigital‐to‐AnalogConverter(DAC)*



TheDACisconfiguredtoutilizetheinternal1.2Vreferencevoltageandmaximumfull‐scaleoutput,

givingita2Vpk‐pkoutput.SincetheDACactuallyoutputscomplementarycurrents,theamplifieris

alsoutilizedasacurrenttovoltageconverterandvoltageshifter.Thisallowsthevoltagetobebuffered



withinthe0Vto3Vrailvoltages.Currently,theDACissetuptooutputbetween.5Vand2.5V.This

givesusacomfortable.5Vbetweenourmaximumoutputsandrailvoltages.Clockmodesandinput

dataformatissetbythesystemutilizingconfigurationpinsavailabletotheFPGA.



ADC

AMP

Input

DAC

AMP

Output

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





*PleaserefertotheAnalogInterfaceSelectionGuideinAppendixEforcompatible8‐12‐bitconverters

RS‐232SerialTransceiver



ThePicoE‐14containsoneasynchronousRS‐232serialtransceiverthatalsomeetsEIA/TIA‐232and

V.28/V.24specificationsatamaximumdatarateof250kBps.Becausetheserialtransceiverisdirectly

connectedtotheFPGAanybithigh‐levelprotocolcanbeimplementedinlogic.PicoComputing

supportsvariousasynchronous,synchronousandmilitaryserialprotocols.



RS‐232isthemostcommonphysicallayerprotocolforserialdata.Itisthestandardusedonserialmice

forcomputers,modems,consumerGPSreceiversandevensomemilitaryradios.Onlyonewireis

neededtosendasignalonanRS‐232link.AtotaloftwodevicesareallowedonasingleRS‐232link.



Inaddition,therearetwopossiblelogicstatesonanRS‐232line(highandlow).Thehighvoltageis

positiveandthelowvoltageisnegative.



PhysicalLayerSpecifications:

Standard Noise

Immunity

Max

Distance

Max

Speed

Max

Connections

RS‐232

Satisfactory 50ft 250kBps* 1Tx/1Rx

*Maximumspeeddecreaseswithincreasedcablelength.

*TheoldRS‐232,422and485standardsarenowobsoleteandhavebeenreplacedbyEIA/TIA‐232,422

and485.



SerialTransceiverSpecifications:

MaximumContinuousPositiveInputVoltage +25VDC

MaximumContinuousNegativeInputVoltage‐25VDC

ESDProtectionLimit +/‐15,000V

MaximumShortCircuitDurationonOutput Infinite



TypicalRS‐232OutputVoltage +/‐5.4V



RS‐232MaximumLowInputThreshold* 1.2V

RS‐232MinimumHighInputThreshold 1.5V

*RS‐232Receiverscanacceptdigitalinputs



E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.







DigitalPeripheralInterface



ThePicoE‐14features16GPIOlinesthatareusedforexternalperipheralsupport.PullingtheDIAG_EN

pinlowreplaces4GPIOsignalswithJTAGsignals.



AllGPIOsignalshaveuserselectablepull‐up,pull‐down,keeperorHI‐Ztermination.Drivestrengthis

alsouserselectablebetween2and24mA.AllGPIOscanbeconfiguredforinput,outputandbi‐

directionalmodeandareequippedwithESDprotection.



DIAG_ENState JTAG GPIO

Float/High Disabled Enabled

Low Enabled Disabled



ElectricalSpecifications Minimum Nominal Maximum

HighVoltage 1.7V 2.5V 2.9V

LowVoltage‐0.2V 0V 0.7V

InputImpedance(PulldownsDisabled) HI‐Z

DriveStrength(Selectable) 2mA 24mA



ESDWithstandVoltage(HumanBodyModel)  2KV



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





CardBusInterface



ThePicoE‐14canrunasastandaloneproductorbeconnectedtoahostusingtheCardBusconnector.

Bydefault,thePicoE‐14shipswithfirmwarethatisreadyforuseasaCardBusslavedevice,butitalso

supportsbusmastering.Thatsamefirmwarealsoprovidesthemeanstoswitchintostandlonemode.



CardBusisa32‐bitinterfacewithamaximumspeedof33MHz.ThePicoE‐14hardwareisdesignedto

supportstandardPCMCIAaswellasDMAmode.TheCardBusstandardspecifiesthatallCardBushosts

bebackwardcompatiblewithPCMCIA.



SinceCardBussystemscanonlybe3.3V,no

digitaltranslatingtransceiversarerequiredtoconnectwith

ahost.ThisallowsdirectconnectiontotheVirtex‐4FPGAforreducedpowerconsumption.Withthis

design,itiseasilypossibletoreversetheCardBusinterfaceandusethePicoE‐14asahostcontroller

forotherCardBusandPCMCIA

cards.



ThosewhoareinterestedinalternateinterfacesshouldcontactPicoComputing.ThePCMCIAdecoder

sourcecodeandsupportisavailable.



PCMCIAInterfaceResources:

CompactFlashAssociation www.compactflash.org

PCMCIAWebsite www.pcmcia.org



For more information on standlone, reference the Standalone documentation located in the doc directory of where Pico

Utility is installed.

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.







DigitalBusInterface



WhenthePicoE‐14isnotconnectedtoaCardBushost,thedigitalbuscanbereconfiguredtoconnect

withawidevarietyofhigh‐speeddigitalbussesandperipherals.Allsignalshaveuserselectablepull‐

up,pull‐down,keeperorHI‐Ztermination.Drivestrengthisalsouserselectablebetween2and24mA.

Allpinscanbeconfiguredforinput,outputandbi‐directionalmode.



Withpropertermination,speedsofover200MHzarepossible.Theexternaldigitalbusissetto

transmitandreceiveat3.3Vonly.



ElectricalSpecifications(DC) Minimum Nominal Maximum

PositiveSupplyInputVoltage(Vcc) 3.15V 3.3V 5.5V

LowLevelInputVoltage 0V 0V 0.7V

HighLevelInputVoltage 2V 3.0V 3.3V



DriveStrength 2mA 24mA



E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.







JTAGDebugInterface



ThePicoE‐14isequippedwithaJTAGdiagnosticportthatallowsreal‐timedebuggingofhardware,

firmwareandsoftware.UseoftheexternalJTAGportdisablesfourexternalGPIOpinsaswellasthe

internalJTAGloopback.



SomeJTAGprogramsrequirethelengthoftheinstructionregister(IR).TheIRlengthislistedbelowfor

alldevicesintheJTAGchain.



Device Instructionregisterbitlength

 FX20 FX60

FPGA 10 14

TurboLoader 8

EthernetPHY 8



FPGA

PowerPC

IR= 10

EthernetTurbo Loader

TDI TDO

IR= 8



Figure4



ThePrimaryImageintheFlashROMcontainsanembeddedJTAGdiagnosticport.Thisallowsauserin

WindowsorLinuxtodebugsoftwarewithoutanexternalJTAGcable.TheinternalJTAGdiagnosticloop

backlooksjustlikeaParallelPortIVdiagnosticcablewhenusedwiththePicoE‐14driver.



FX20: IR = 10

FX60: IR = 14

E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.







AppendixA

–

PeripheralI/OConnectorInformation



ConnectorInformation

Description Brand PartNumber

MatingConnector Hirose NX30TA‐32PAA(50)

MatingConnectorBackshell Hirose NX‐32TA‐CV1(50)

*ConnectorsarealwaysinstockatPicoComputing



PeripheralI/OConnectorPinout

1 ETHER_OUT_DD‐ Ethernet(MagneticallyIsolated)

2 ETHER_OUT_DD+ Ethernet(MagneticallyIsolated)

3 GPIO_15_FILTERED GeneralpurposeI/O

4 GPIO_14_FILTERED GeneralpurposeI/O

5 GPIO_13_FILTERED GeneralpurposeI/O

6 GPIO_12_FILTERED GeneralpurposeI/O

7 ETHER_OUT_DC‐ Ethernet(MagneticallyIsolated)

8 ETHER_OUT_DC+ Ethernet(MagneticallyIsolated)

9 GPIO_11_FILTERED GeneralpurposeI/O

10 GPIO_10_FILTERED GeneralpurposeI/O

11 GPIO_9_FILTERED GeneralpurposeI/O

12 GPIO_8_FILTERED GeneralpurposeI/O

13 ETHER_OUT_DB‐ Ethernet(MagneticallyIsolated)

14 ETHER_OUT_DB+ Ethernet(MagneticallyIsolated)

15 GPIO_7_FILTERED GeneralpurposeI/O

16 GPIO_6_FILTERED GeneralpurposeI/O

17 GPIO_5_FILTERED GeneralpurposeI/O

18 GPIO_4_FILTERED GeneralpurposeI/O

19 ETHER_OUT_DA‐ Ethernet(MagneticallyIsolated)

20 ETHER_OUT_DA+ Ethernet(MagneticallyIsolated)

21 DAC_OUTPUT D/AConverteroutput

22 SERIAL_RX_FILT RS‐232Serialreceiverinput

23 SERIAL_TX_FILT RS‐232Serialdriveroutput

24 ADC_INPUT A/DConverterinput

25 PIC_TRIGGER_EXT NOTCONNECTED

26 2.5V_EXT 2.5V0.45Aperipheralpower

27 GPIO_3/TDI_FILT GeneralpurposeI/OorJTAGTDI

28 GPIO_2/TDO_FILT GeneralpurposeI/OorJTAGTDO

29 GPIO_1/TMS_FILT GeneralpurposeI/OorJTAGTMS

30 GPIO_0/TCK_FILT GeneralpurposeI/OorJTAGTCK

31 D\I\A\G\_\E\N\_\ JTAGportenablewhenshortedtoground

32 GND_EXT Groundreturn



NOTE:Pin1indicatorontheboardisactuallyPin32indicator



E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.







PeripheralConnectorPin#1Location



Figure5



AppendixB

–

CardBusConnectorInformation



ConnectorInformation

Description Brand PartNumber

CardBusHeader Hirose IC9‐68RD‐0.635SF‐(51)

ThePicoE‐14willmatewithanyType‐IICardBusHeader



ThefunctionanddirectionofthepinsontheCardBusinterfacecanbeeasilychanged.Pleaseseethe

“DigitalBusInterface”sectionformoreinformation.



CardBusConnectorPinout

Name Pin Description Dir

GND 1 CardGround PWR

CAD0 2 CardBusData/Address0 IO

CAD1 3 CardBusData/Address1 IO

CAD3 4 CardBusData/Address3 IO

CAD5 5 CardBusData/Address5 IO

CAD7 6 CardBusData/Address7 IO

C\C\/\B\E

 7 CommandandByteEnable IO

CAD9 8 CardBusData/Address9 IO

CAD11 9 CardBusData/Address11 IO

CAD12 10 CardBusData/Address12 IO

CAD14 11 CardBusData/Address14 IO

C\C\/\B\E

 12 CommandandByteEnable IO

CPAR 13 Parity IO

C\P

E\R\R

 14 ParityError IO

C\G

 15 Grand I

C\I

 16 CardIntertRequest O

VCC 17 CardPower(3.3V) PWR

VPP 18 CardProgrammingVoltage(NotUsed) PWR

CCLK 19 CardBusClock I

C\I

R\D\Y

 20 InitiatorReady IO

C\C\/\B\E

 21 CommandandByteEnable IO

CAD18 22 CardBusData/Address18 IO

CAD20 23 CardBusData/Address20 IO

CAD21 24 CardBusData/Address21 IO

CAD22 25 CardBusData/Address22 IO

CAD23 26 CardBusData/Address23 IO

CAD24 27 CardBusData/Address24 IO

CAD25 28 CardBusData/Address25 IO

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Pico Communications E-14 User manual

Brand: Pico Communications

Model: E-14

Type: User manual

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Pico Communications E-14 User manual

Pico Communications E-14 User manual

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