NXP TEA175X User guide

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User guide

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UM10403
90 Watt notebook adapter with TEA1752T and TEA1791T
Rev. 01 — 28 May 2010 User manual
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Keywords GreenChip III, TEA1752T, GreenChip SR, TEA1791T, PFC, flyback,
synchronous rectification, high efficiency, adapter, notebook, PC power
Abstract This manual provides the specification, performance, schematics, bill of
materials and PCB layout of a 90 W notebook adapter using the
TEA1752T and TEA1791T. For design details on the TEA1752T and
TEA1791T please refer to the application notes.
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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors
UM10403
90 Watt notebook adapter with TEA1752T and TEA1791T
Revision history
Rev Date Description
01 28 May 2010 First Draft
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1. Introduction
This manual describes a universal input, 19.5 V, 4.62 A single output power supply using
TEA1752T and TEA1791T devices from the GreenChip-III and GreenChip-SR family of
NXP Semiconductors. It contains the specification of the power supply, circuit diagram,
the component list to build the supply, the PCB layout and component positions,
documentation of the PFC choke and transformer, along with test data and oscilloscope
pictures of the most important waveforms.
The GreenChip-3 combines the control and drive for both the PFC and the flyback stages
into a single device. The TEA1752T: provides complete SMPS control functionality to
comply with the IEC61000-3-2 harmonic current emission requirements, obtain a
significant reduction of components, save PCB space and give a cost benefit. It also offers
extremely low power consumption in no-load mode, which makes it suitable for the
low-power consumer markets. The built-in green functions ensure high efficiency at all
power levels, which results in a design that can easily meet all existing and proposed
energy efficiency standards such as: CoC (Europe), ENERGY STAR (US), CEC
(California), MEPS (Australian and New Zealand), and CECP (China).
The GreenChip SR is a synchronous rectification control IC that needs no external
components to tune the timing. Used in notebook adapter designs, the GreenChip SR
offers a wide VCC operating range between 8.5 V and 38 V, minimizing the number of
external components required and enabling simpler designs. In addition, the high driver
output voltage (10 V) makes the GreenChip SR compatible with all brands of MOSFETs.
WARNING
Lethal voltage and fire ignition hazard
The non-insulated high voltages that are present when operating this product, constitute a
risk of electric shock, personal injury, death and/or ignition of fire.
This product is intended for evaluation purposes only. It shall be operated in a designated test
area by personnel that is qualified according to local requirements and labor laws to work with
non-insulated mains voltages and high-voltage circuits. This product shall never be operated
unattended.
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2. Specification
Mains input voltage: 90 V to 264 V; 47 Hz to 63 Hz
DC output: 19.5 V; ±2 %
Maximum continuous output current: 4.62 A
Peak output current: 5.7 A
Efficiency: > 88.5 % at maximum load
ENERGY STAR active mode efficiency: > 89.5 %
No load power consumption: 0.2 W
Dynamic load response (peak-to-peak): 700 mV
Output ripple and noise (peak-to-peak): 100 mV
CISPR22 class B conducted EMI (15 dB margin)
EN61000-4-2 immunity against ESD ( ±12 kV air discharge)
EN61000-3-2 A14 (harmonics) compliance
Short Circuit Protection (SCP); input power < 1.2 W during SCP test
OverCurrent Protection (OCP); input power < 2.2 W during OCP test
Latched output OverVoltage Protection (OVP): < 24 V
Latched OverTemperature Protection (OTP); 120 °C
Fast Latch Reset (FLR): < 2 s
Fig 1. 90 W TEA1752T and TEA1791T demo board
001aak8
26
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3. Performance data
3.1 Test setup
3.1.1 Test equipment
AC source: Agilent 6812B
Power meter: Yokogawa WT210 with Harmonics option
DC electronic load: Chroma, Model 63103
Digital oscilloscope: Yokogawa DL1640L
Current probe Yokogawa 701933 30A; 50MHz
100 MHz, high voltage differential probe: Yokogawa 700924
500 MHz, low voltage differential probe: Yokogawa 701920
Multimeter: Keithley 2000
EMC receiver: Rohde & Schwarz ESPI-3 + LISN ENV216
3.1.2 Test conditions
Adapter on the lab-table with the heat sinks downwards
The adapter has no casing
Ambient temperature between 20 °C and 25 °C
Measurements were made after stabilization of temperature according to "test method
for calculating the efficiency of single-voltage external AC-DC and AC-AC power
supplies" of ENERGY STAR
3.2 Efficiency
3.2.1 ENERGY STAR efficiency
To market adapters as ENERGY STAR efficient they have to pass the active mode and
no-load criteria as stated in the ENERGY STAR standard for External Power Supplies;
EPS2.0. The minimum active-mode efficiency is defined as the arithmetic average
efficiency at 25 %, 50 %, 75 % and 100 % of the rated output power as printed on the
nameplate of the adapter.
3.2.1.1 Active mode efficiency
Test Conditions:
The adapter is set to maximum load and well pre-heated until temperature stabilization is
achieved. Temperature stabilization is established for every load step before recording
any measurements.
Remark: The output voltage is measured at the end of the output cable (2 × 20 mΩ).
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Criteria to pass:
To comply with ENERGY STAR EPS2.0, the arithmetic average of the four efficiency
measurements must be greater than, or equal to, 87 %. Universal mains adapters have to
pass the criteria at both 115 V; 60 Hz and 230 V; 50 Hz. To meet this criteria, the PFC
must be off at 25 % load and preferably on at 50 % load.
3.2.1.2 No-load input power
Test Conditions:
The adapter is set to maximum load and pre-heated. After 5 minutes the load is removed.
The no-load input power measurements were recorded after stabilization of the input
power reading.
Criteria to pass:
To comply with ENERGY STAR EPS2.0, the input power must be less than 0.5 W.
Universal mains adapters have to pass the criteria at both 115 V; 60 Hz and 230 V; 50 Hz.
The adapter is set to maximum load and pre-heated. After 5 minutes the load is removed.
The no-load input power measurements were recorded after stabilization of the input
power reading.
Table 1. Active mode efficiency at 115 V; 60 Hz
Load (%) I
O
(A) V
O
(V) P
O
(W) P
I
(W) Efficiency
(%)
Power
factor
100 4.628 19.173 88.72 98.94 89.67 0.986
75 3.472 19.246 66.81 73.74 90.61 0.979
50 2.315 19.318 44.73 49.33 90.67 0.965
25 1.160 19.383 22.49 24.69 91.08 0.450
Average - - - - 90.51 -
Table 2. Active mode efficiency at 230 V; 50 Hz
Load (%) I
O
(A) V
O
(V) P
O
(W) P
I
(W) Efficiency
(%)
Power
factor
100 4.628 19.175 88.73 98.41 90.17 0.945
75 3.472 19.247 66.82 74.31 89.92 0.921
50 2.316 19.319 44.73 50.49 88.60 0.878
25 1.160 19.385 22.49 24.75 90.87 0.378
Average - - - - 89.89 -
Table 3. PFC on and off level as a function of the mains input voltage
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
Output current (A) (PFC on) 1.75 1.83 1.88 1.91 1.86
Output current (A) (PFC off) 1.35 1.36 1.34 1.35 1.31
Table 4. No-load input power
No-load input power as a function of the mains input voltage.
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
Input power P
I
(W) 0.137 0.139 0.142 0.182 0.200
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3.2.1.3 Full load efficiency PFC plus flyback stage
Test conditions:
Before any measurements were recorded, the adapter is set to maximum load and is
preheated till the readings were stabilized.
Remark: The output voltage is measured at the end of the output cable. (2 × 20 mΩ)
Criteria to pass:
The efficiency (η) must be > 88 % at the maximum continuous output load.
3.3 Timing and protection
3.3.1 Switch-on delay and output rise time
Test conditions:
The electronic load is set to Constant Current (CC) mode and V
on
= 0 V. The electronic
load is set to the maximum continuous output current.
Criteria to pass:
Switch-on delay: two seconds maximum after the AC mains voltage is applied to the
time when the output is within regulation
Output rise time: The output voltage must rise from 10 % of the maximum to the
regulation limit within 30 ms. There must be a smooth and continuous ramp-up of the
output voltage. No voltage with a negative polarity must be present at the output
during start-up
No output bounce or hiccup is allowed during switch-on.
There be must be sufficient margin between the FBCTRL signal and the 4.5 V
time-out trigger level to avoid false triggering of the time-out protection due to
component tolerances
Table 5. PFC plus flyback stage
Total converter efficiency (at full load) as a function of the mains input
Mains supply V; Hz I
I
RMS (A) P
O
(W) P
I
(W) Efficiency
(%)
Power factor
90; 60 1.130 88.74 100.24 88.53 0.989
100; 50 1.013 88.76 99.58 89.14 0.987
115; 60 0.877 88.72 98.94 89.67 0.986
230; 50 0.456 88.73 98.41 90.17 0.945
264; 50 0.402 88.66 98.26 90.24 0.929
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a. Mains input 90 V; 60 Hz; delay time 484 ms b. Mains input 264 V; 50 Hz; delay time 484 ms
Load = 4.62 A
CH1: mains input
CH2: VCC pin TEA1752T
CH3:FBCTRL pin TEA1752T
CH4: output voltage
Load = 4.62 A
CH1: mains input
CH2: VCC pin TEA1752T
CH3: FBCTRL pin TEA1752T
CH4: output voltage
Fig 2. Delay between switch-on and output in regulation
019aaa009 019aaa010
a. Mains input 90 V; 60 Hz; output rise time 12.64 ms b. Mains input 264 V; 50 Hz; output rise time
12.24 ms
Load = 4.63 A
CH1: mains input
CH2: FBCTRL pin TEA1752T
CH3: FBSENSE pin TEA1752T (soft start)
CH4: output voltage
Load = 4.63 A
CH1: mains input
CH2: VCC pin TEA1751T
CH3: FBSENSE pin TEA1751T (soft start)
CH4: output voltage
Fig 3. Output rise time at full load start-up
019aaa011
019aaa012
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3.3.2 Brownout and brownout recovery
The voltage on the VINSENSE pin is monitored continuously to prevent the PFC from
operating at very low mains input voltages.
Test Conditions:
The mains input voltage is decreased from 90 V down to 0 V and then increased from 0 V
to 90 V. The electronic load is set to Constant Current (CC) mode and V
on
=0V. The
electronic load is set to the maximum continuous output current.
Criteria to pass:
The adapter must survive the test without damage and excessive heating of
component
The output voltage must remain within the specified regulation limits or switch-off
No output bounce or hiccup is allowed during switch-on or switch-off
The adapter must power-up before the AC line input voltage reaches 85 V (maximum)
3.3.3 Output short circuit protection
To protect the adapter and application against an output short circuit or a single fault open
(flyback) feedback loop situations, time-out protection is implemented. When the voltage
on FBCTRL pin rises above 4.5 V (typical.), a fault is assumed and switching is blocked.
The time-out protection must not trigger during a normal start-up with the maximum
continuous output current.
a. AC mains input from 90 V to 0 V b. AC mains input from 0 V to 90 V
brownout voltage =
Load = 4.62 A
CH1: mains input
CH2: VINSENSE pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
brownout recovery voltage =
Load = 4.62 A
CH1: mains input
CH2: VINSENSE pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Fig 4. Brownout and brownout recovery
019aaa013 019aaa014
108 2() 76 V= 121 2() 86 V)=
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Test Conditions:
There are two test conditions:
1. The adapter is switched on with 4.62 A output load. After startup a short circuit is
applied manually at the end of the output cable
2. Before the adapter is switched on a short circuit is applied to at the end of the output
cable
Remark: An output short-circuit is defined as an output impedance of less than 0.1 ohm.
Criteria to pass:
The adapter must be capable of withstanding a continuous short-circuit at the output
without damaging or overstressing the adapter under any input conditions
The average input power must be less than 3 W during the short-circuit test
After removal of the short circuit, the adapter must recover automatically
a. Mains input 90 V; 60 Hz b. Mains input 264 V; 50 Hz
Load before short circuit = 4.62 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Load before short circuit = 4.62 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: FBDRIVER pin TEA1752T
CH4: output voltage
Fig 5. Output short-circuit, triggering of the time-out protection
019aaa015
019aaa016
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a. Output short-circuit during normal operation b. Output short-circuit applied before start-up
Load before short circuit= 4.62 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Load = short circuit
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Fig 6. Output short-circuit at 90 V; 60 Hz
019aaa017
019aaa018
a. Output short-circuit during normal operation b. Output short-circuit applied before start-up
Load before short circuit = 4.62 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Load = short circuit
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Fig 7. Output short-circuit at 264 V; 50 Hz
019aaa019
019aaa020
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3.3.4 Output OverCurrent protection (OCP)
Test Conditions:
The electronic load is set in Constant Current (CC) mode
The load is increased from the maximum continuous value in small steps until the
over current protection is triggered. The input power is measured after triggering over
the over current protection without changing the load setting
Criteria to pass:
The output power must be limited to less than 150 W, just before the triggering of the
over current protection
The average input power must be less than 3 W once the over current protection has
been triggered
3.3.5 Output OverVoltage Protection (OVP)
Test Conditions:
The adapter is switched on without a load at the output
An output over-voltage is created by applying a short circuit across the opto LED of
U2
Criteria to pass:
The output voltage must not exceed 25 V or stabilize between 25 V and the rated
output voltage
The voltage on the TEA1752T VCC pin must not exceed the absolute maximum rating
of 38 V
When OVP is triggered, the primary side controller must shut down and stay in a
latched mode
A single point fault must not cause a sustained overvoltage condition at the output
Table 6. Output short circuit input power
Output short circuit input power as a function of the mains input voltage
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
Input power P
I
(W) 1.113 1.013 0.877 0.456 0.402
Table 7. Output over current protection and input power as a function of the mains input
voltage.
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
Over current trigger level (A) 6.45 6.47 6.47 6.05 6.05
Input power P
I
(W) 1.92 1.89 1.82 2.17 2.11
Table 8. Output over-voltage protection
Output over-voltage at no-load as a function of the mains input voltage with protection mode latched
Mains supply (V; Hz) 90; 60 100; 50 115; 60 230; 50 264; 50
Output OVP trip point (V) 23.8 23.8 23.7 23.8 23.7
VCC maximum during
OVP (V)
27.5 27.5 27.5 27.1 27.0
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3.3.6 OverTemperature protection (OTP)
An accurate external over temperature protection (TEA1752T’s LATCH pin, RT2, R26 and
C19) is provided on the demo board to protect the flyback transformer against overheating
(see Figure 14
). Normally, the flyback transformer is the most heat sensitive component.
Test Conditions:
The NTC temperature sensor, glued to the transformer, is heated using a heat gun.
Criteria to pass:
The IC must latch off the output at a VLATCH trip level of 1.25V. No output bounce or
hiccup is allowed
a. Mains input 90 V; 60 Hz b. Mains input 264 V; 50 Hz
Load before short circuit = 0 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Load before short circuit = 0 A
CH1: drain flyback MOSFET
CH2: FBCTRL pin TEA1752T
CH3: VCC pin TEA1752T
CH4: output voltage
Fig 8. Output OverVoltage Protection
019aaa021 019aaa022
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3.3.7 Fast latch reset
A Fast Latch Reset function (FLR) enables latched protection to be reset without
discharging the bulk elcap. The latch protection is reset as soon as the voltage on
VINSENSE pin drops below 0.75 V and is then raised to 0.87 V.
Test conditions:
The output is not loaded
The test sequence is as follows:
The latch protection is triggered by an OVP caused by a short-circuit across the
OPTO led
The mains input is switched off and the voltage on pin VINSENSE dropped below
0.75 V
The mains input is switched on and, as soon as the voltage on pin VINSENSE
rises above 0.87 V, the latch is reset
Remark: Both live and neutral must be switched.
Criteria to pass:
The latch must be reset within 3 seconds after switching off and switching on, the mains
input voltage.
OTP trigger temperature 108 °C
Load before short-circuit = 0 A
CH1: V
out
CH2: TEA1752T VCC pin
CH3: Mains input voltage
CH4: TEA1752T LATCH pin
Fig 9. External OverTemperature Protection (OTP)
001aak80
4
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3.4 Output regulation and characterization
3.4.1 Load regulation
Test conditions:
The output voltage deviation is measured while the load current on the output is
increased from 0 A to 4.62 A
The measurement is repeated for different mains input voltages
Remark: The output voltage is measured at the end of the output cable (2 × 20 mΩ).
Criteria to pass:
The output load regulation must remain within 2 %.
The load regulation is calculated using Equation 1
.
(1)
where V
O(nom)
= 19.5 V.
a. Mains input 90 V; 60 Hz; FLR = 1.6 s b. Mains input 264 V; 50 Hz; FLR = 1.3 s
CH1: V
out
CH2: VCC pin TEA1752T
CH3: AC mains input
CH4: VINSENSE pin TEA1752T
CH1: V
out
CH2: VCC pin TEA1752T
CH3: AC mains input
CH4: VINSENSE pin TEA1752T
Fig 10. Fast Latch Reset (FLR)
001aak80
5
001aak80
6
Table 9. Load regulation
Output voltage as a function of the output load and the mains input voltage
Mains supply V; Hz 90; 60 90; 60 264; 50 264; 50
V
O
; I
O
(V; A) 19.558; 0 19.325; 4.62 19.559; 0 19.324; 4.62
V
Omax()
V
Omin()
V
O nom()
-------------------------------------------
100 %×
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Load regulation at 90 V; 60 Hz is calculated as follows:
(2)
Load regulation at 264 V; 50 Hz is calculated as follows:
(3)
3.4.2 Line regulation
Test conditions:
The output voltage deviation is measured while the mains voltage on the input is
increased from 90 V to 264 V
The measurement is repeated for different mains input voltages
Remark: The output voltage is measured at the end of the output cable. The load current
is 4.62 A.
The line regulation is calculated using the following equation:
(4)
Criteria to pass:
The output voltage deviation must remain within 0.05 %.
Load regulation at 90 V; 60 Hz is calculated using the following equation:
(5)
3.4.3 Ripple and noise PARD (Periodic And Random Deviation)
Ripple and noise are defined as the periodic or random signals over a frequency band of
10 Hz to 20 MHz.
Test Conditions:
The measurement is made with an oscilloscope set to bandwidth of 20 MHz
The output is shunted at the end of the output cable, by a 0.1 μF ceramic disk
capacitor and a 22 μF electrolytic capacitor, to simulate loading
Criteria to pass:
The output ripple and noise must remain within the specified limits 100 mV (peak-to-peak)
at a maximum load current of 4.62 A.
19.558V 19.325V
19.5V
-----------------------------------------------
100 %× 1.19 %=
19.559V 19.324V
19.5V
-----------------------------------------------
100 %× 1.21 %=
Table 10. Line regulation
Output voltage (at full load) as a function of the mains input voltage
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
V
O
(V) 19.325 19.325 19.325 19.324 19.324
V
Omax()
V
Omin()
V
O nom()
-------------------------------------------
100 %×
19.325V 19.324V
19.5V
-----------------------------------------------
100 %× 0.005 %=
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3.4.4 Dynamic load response
Test Conditions:
The adapter is subjected to a load change from 0 % to 100 % at a slew rate of
1A/ms
The frequency of change is set to give the best readability of the deviation and setting
time
Remark: The voltage is measured at the end of the output cable.
Criteria to pass:
The output is not allowed to have an overshoot or undershoot beyond the specified limits
(+1 V to 0.5 V) after a load change.
Table 11. Ripple and noise PARD
Ripple and noise (at maximum load) as a function of the mains input voltage.
Mains supply V; Hz 90; 60 100; 50 115; 60 230; 50 264; 50
PARD (mV) 94 94 94 83 83
Table 12. Dynamic load response
Deviation of the output voltage at a load step from 4.62 A to 0 A and from 0 A to 4.62 A
Mains supply V; Hz 90; 60 230; 50
Deviation (mV
p-p
) 700 700
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CH1: PFC bus voltage
CH2: output current
Ch3: PFCTIMER pin
Ch4: output voltage
CH1: PFC bus voltage
CH2: output current
Ch3: PFCTIMER pin
Ch4: output voltage
a. Mains input 90 V; 60 Hz b. Mains input 90 V; 60 Hz (detail picture)
CH1: PFC bus voltage
CH2: output current
Ch3: PFCTIMER pin
Ch4: output voltage
CH1: PFC bus voltage
CH2: output current
Ch3: PFCTIMER pin
Ch4: output voltage
c. Mains input 230 V; 50 Hz d. Mains input 230 V; 50 Hz (detail picture)
Fig 11. Dynamic load response
019aaa023 019aaa024
019aaa025 019aaa026
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4. ElectroMagnetic Compatibility (EMC)
4.1 Conducted emission
Test Conditions:
The adapter is subjected to maximum load
The ground connection of the output cable is connected to EMC ground
Criteria to pass:
CISPR22 Class B with -10 dB production margin
(1) QP limit
(2) AV limit
(3) Peak reading
The conducted EMI measurement of 110 V neutral is close to 110 V line
Fig 12. Conducted EMI 110 V line
001aak816
f (MHz)
10
-1
10
2
101
40
60
20
80
100
(dBuV)
0
(1)
(2)
(3)
x
2
x
1
Table 13. Conducted EMI measurement 110 V line
Refer to Figure 12
points 1 and 2 on the peak reading graph
No. Frequency Correction
factor
Reading dBμV Emission dBμV Limit dBμV Margins dB
MHz dB QP AV QP AV QP AV QP AV
1 0.20112 0.12 32.67 27.68 32.79 27.80 63.56 53.56 30.77 25.76
2 24.36328 1.50 35.94 30.50 37.44 32.00 60.00 50.00 22.56 18.00
UM10403_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 01 — 28 May 2010 20 of 32
NXP Semiconductors
UM10403
90 Watt notebook adapter with TEA1752T and TEA1791T
4.2 Immunity against lighting surges
Test conditions:
Combination wave: 1.2/50 μs open circuit voltage and 8/20 μs short circuit current
Test voltage: 2 kV
L1 to L2: 2 Ω; L1 to PE, L2 to PE and L1 + L2 to PE: 12 Ω
Phase angle: 0 °, 90 °, 180 ° and 270 °
Number of tests: 5 positive and 5 negative
Pulse repetition rate: 20 s
Test result:
There is no disruption of functionality
(1) QP limit
(2) AV limit
(3) Peak reading
The conducted EMI measurement of 230 V neutral is close to 230 V line
Fig 13. Conducted EMI 230 V line
001aak817
f (MHz)
10
-1
10
2
101
40
60
20
80
100
(dBuV)
0
(3)
(2)
(1)
x
1
x
2
x
3
Table 14. Conducted EMI measurement 230 V line
Refer to Figure 13
points 1, 2 and 3 on the peak reading graph.
No. Frequency Correction
factor
Reading dBμV Emission dBμV Limit dBμV Margins dB
MHz dB QP AV QP AV QP AV QP AV
1 0.18906 0.09 38.38 37.05 38.47 37.14 64.508 54.08 25.01 16.94
2 0.43516 0.20 32.37 24.52 32.57 24.72 5715 47.15 24.58 22.43
3 25.11328 1.14 38.45 32.14 39.59 33.28 60.00 50.00 20.41 16.72
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NXP TEA175X User guide

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