NXP P80C51FA-4A User guide

UM10113

User manual for the PNX2015 family

Rev. 01 – 6 May 2005 User manual

Document information

Info Content

Keywords TV810 platform, PNX8550, ATV, ATSC, Jaguar, HD subsystem, AVIP1, AVIP2,

Columbus, TV microcontroller.

Abstract This user manual provides a functional overview of PNX2015, together with detailed

descriptions of major functional blocks.

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PNX2015 User Manual

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

Revision history

Rev Date Description

01 20050506 Objective data

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1. Introduction

The Functional Overview section of this User Manual contains three IC level overviews:

• Interfaces

IC interfaces and configuration of AVIP 1 and 2 in the PNX2015

• Top level, structure

IC wide signal and power requirement

• Subsystems

Summary of IP block functions

The main body of the manual describes the IP blocks that the PNX2015 contains:

• AVIP

Dlink audio video input interface IP block. This section is applicable to both AVIP 1

and AVIP 2

• Columbus

3D comb filter and spatial/temporal noise reduction block description

• HD subsystem

This module subdivides to further IP block descriptions

• LVDS transmitter

30 bit input (from PNX8550 QVCP) IP block description

• TV microcontroller

Standby micro (containing an 80C51 CPU core) description

The end sections include Limitations, Glossary and Contents.

This user manual provides:

This User Manual contains a description of the PNX2015 components and its internal IP

blocks. The Internal IP bock descriptions contain register listings and show how the IP

blocks perform their function. There are IC inter connectivity descriptions to the PNX8550

and Video coprocessor. There are explanations of the video audio and programming

interfaces.

This user manual does not provide:

Since the PNX2015 is a component within a system this document is not a Use Case

based programming guide. The register descriptions do not contain recommended

programming values. The PNX2015 has a memory bases architecture which provides for

flexible configuration to meet Use Case requirements. There are therefore no

configuration descriptions for the PNX2015.

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2. Functional overview

2.1 Introduction

The PNX2015 is a prime component for the mid-to high-end market segment of the ATSC,

DVB and Flat Panel markets. Through the addition of various hardware and software

components, systems can meet high-end requirements of connectivity and picture

performance.

The PNX2015 accompanies the PNX8550 and provides the following functionality, in

addition to that provided by PNX8550:

• Dual analog audio/video decoding.

• Full audio processing.

• Analog video improvement, e.g. 3D comb filter, noise reduction and noise

measurement (Columbus).

• Second channel HD decode with memory based scaler.

• Interface to additional external video improvement IC’s.

• RGB via standard LVDS interface for LCD panels.

• Embedded TV microcontroller.

An example system diagram is shown in Figure 1

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In terms of functional blocks the PNX2015 can be described as follows:

• Audio Video Input Processor 1 (AVIP1).

• Audio Video Input Processor 2 (AVIP2).

• 3D comb filter with spatial and temporal noise reduction (Columbus).

• High Definition MPEG decoder (HD Subsystem).

• Standby microcontroller for low-power control.

The PNX2015 block diagram is shown in Figure 2

.

Fig 1. System diagram

MATRIX

Up to 1366 × 768 at 60 p/s

Up to 1280 × 768 at 60 p/s

Up to 1920 x 1080 at 50 Hz

PNX2015

STANDBY

MICROPROCESSOR

DUAL DIGITAL

COLOR DECODER

FULL 5.1 CHANNEL AUDIO

PNX8550

SDRAM

32 MB TO 128 MB

MIPS32 AT 250 MHz

PIXEL OSD, TV CONTROL

NM, MBS, AV PIP

CONNECTIVITY

SDRAM

16 MB TO 32 MB

FLASH

8 MB TO 32 MB

32

SPI

64 kB

TUNER/SAW

TDA9975

PNX3000

IF, SWITCH

CHANNEL

DECODER

CHANNEL

DECODER

AUDIO

AMPLIFIER

16

DVI

HDMI

RGB

Optional

Video

Coprocessor

AUDIO

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2.2 Feature summary

• Detection of PAL, NTSC or SECAM analog sources and 1

fH

and 2

fH

component video

input sources. (1

fH

= 13.3 MHz, 2

fH

= 27 MHz).

• Support for 1

fH

and 2

fH

video sources; progressive and interlaced.

• 3D comb filters for PAL/NTSC standards.

• Spatial and temporal noise reduction for PAL, NTSC and SECAM analog sources.

• Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC and Gemstar™).

• Global multi-standard audio demodulation and decoding (FM, AM, NICAM, BTSC,

A2).

• Dolby

®

ProLogic

®

ll multi-channel audio decoding and post-processing.

• Advanced, fully programmable audio post-processing functions (VDS, VDD, bass

management and graphic equalizer).

• RGB via standard LVDS interface for National™ (18/24-bit) and THine™

(18/24/30-bit).

• High and Standard Definition digital video input interface.

• Hardware decoding of two SD streams (MPEG2 MP@ML) or one HD (MPEG2

MP@HL).

• Embedded TV Microcontroller for TV control and system power management.

• Two independent tunnel interfaces for PNX8550 and video coprocessor.

Fig 2. PNX2015 block diagram

DCS SECURITY T

DCS CONTROLLER

GLOBAL REGISTERS

I2C

T

LVDS_Tx T

RESET T

TIMESTAMP UNIT

JTAG

T

GENERIC INTERRUPT

CONTROLLER

T

S

I

VIPT W

VO-1T

MEMORY CONTROLLERT

R

VO-2T R

MBS_V2T

T

R

W

DMA_GATE

R

W

CLOCKSCAB T

DLINK

I2C

VIDDEC T

DCU T

ITU-FORMATTER T

T

S

I

HD SUBSYSTEM

COLUMBUS

streaming

connection

NORTH TUNNEL

(Bridge to VIDEO

COPROCESSOR)

T

R

W

COLUMBUS

S

COLUMBUS

FILTER MONITOR

T

PMAN1

MONITOR

T

GENERAL PURPOSE

REGISTERS

T

DEMDEC DSP

PI-CONTROLLER

AUDIO DSP

and 12 x DAC

T

PMAN1

SECURITY

T

PMAN1

ARBITER

T

PMAN2

SECURITY

T

PMAN2

MONITOR

T

SOUTH TUNNEL

(Bridge to PNX8550)

I

T

VMPG

R

W

DCSN

PMAN1

PMAN2

PI

DLINK

I2C

VIDDEC T

DCU T

ITU-FORMATTER T

T

S

I

GENERAL PURPOSE

REGISTERS

T

DEMDEC DSP

PI-CONTROLLER

AUDIO DSPT

T

AVIP-1

AVIP-2

TV MICROCONTROLLER

80C51 CORE

(CPU, T0,

T1, PCON,

INTERRUPTS)

PROGRAM

MEMORY

62 kB

(SRAM)

UART

PORTS

0 TO 6

PCA

0 TO 6

SPIWATCHDOGTIMER2

BOOT

2 kB

(ROM)

PWM

0 TO 1

ADC

M/S

I2C

DATA

MEMORY

256 + 4096

BYTES

(SRAM)

T=TARGET

I=INITIATOR

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• Memory interface for DDR/GDDR SDRAM and SPI™ for external flash.

• Three digital video outputs 8/10-bit YUV 4:2:2.

Three versions of the PNX2015 are available, the features are shown in Tabl e 1

.

2.3 Interfaces

2.3.1 Video

Figure 3 shows the main video interfaces of PNX2015, and how the video signals are

connected between subsystems.

Table 1: PNX2015 versions

Type number Features

3D NTSC 3D PAL DPL2 BBE™ dbx™

PNX2015E/M1C02 33

PNX2015E/M1C03 333

Fig 3. PNX2015 subsystems

AVIP-1

DLINK1

SYNC

COLUMBUS

0-9

10-19

VO-1

memory

controller

DV1

DV2

DV1MUX

DV3MUX

DV2MUX

PNX8550

direct

0-9

10-19

VO-2

HUB

PNX3000-1

AVIP-2

VIP

DLINK2

SYNC

PNX3000-2

DV4

DV5

video

SOUTH

TUNNEL

RX/TX

MBS

MEMORY

CONTROLLER

VMPG

LCD panel

PNX8550

DV3

PNX8550

NORTH

TUNNEL

RX/TX

LVDS_TX

TA, TB, TC, TD, TE, CLK

HD SUBSYSTEM

COLMUX

PNX2015

RGB,

HV

PNX8550

video

coprocessor

PNX8550

16-bit

200 MHz

DDR

D

L

I

N

K

D

L

I

N

K

VIDDEC

DCU

ITU

656

AUDIO

VIDDEC

DCU

ITU

656

AUDIO

TV

Microcontroller

PNX8550

Power Control

DSP/DEMDEC

SYNC

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Table 2 to Table 4 show the outputs available on the three Digital Video output ports. Each

DV port can independently select the required (8/10-bit YUV) output source. There is no

link between the DV outputs.

The DV1 and DV2 ports can be used in combination to output a 16/20-bit semi-planar

signal. In this mode DV1 outputs the Y (lower 10-bits) component, and DV2 the UV (upper

10-bits) component.

The DV Input ports can be used as a standard 656 interface 8/10-bit with DV4 only, or as a

16/20-bit semi-planar mode with the addition of DV5. One clock is provided for DV4 and

DV5, so they may not be used independently.

The use of video data bus bits on DV1 to DV5, and their connections for the SD and HD

capture modes are shown in Tabl e 7

and Table 6. DV1, DV2 and DV3 are outputs, DV4

and DV5 are inputs.

In all modes, the MSB of the data words is always placed on pin [9], i.e. in any 8-bit mode

the valid data occupies the upper 8 most significant bit positions of the 10-bit input.

Table 2: Output port DV1 - signal combinations

Select DV1

0 Default AVIP1

1 AVIP2

2Columbus

3 VO-1 (lower) 656 mode = YUV; semi-planar = Y

4 VO-2 (lower) 656 mode = YUV; semi-planar = Y

Table 3: Output port DV2 - signal combinations

Select DV2

0 VO-1 656 mode = YUV; semi-planar = N/A

1 Default VO-2 656 mode = YUV; semi-planar = N/A

2 VO-1 (upper) 656 mode = N/A; semi-planar = UV

3 VO-2 (upper) 656 mode = N/A; semi-planar = UV

Table 4: Output port DV3 - signal combinations

Select DV3

0 AVIP1

1 Default AVIP2

2Columbus

3 VO-1 656 mode = YUV; semi-planar = N/A

Table 5: DV input port signal combinations (DV4, DV5)

Input port 656 mode Semi-planar mode

DV4 YUV Y

DV5 - UV

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2.3.1.1 Multi-mode video output

2.3.1.2 Multi-mode video input

2.3.2 Audio

The audio interfaces allow for up to six I

2

S[9] digital inputs, and six I

2

S digital outputs. All

I

2

S interfaces share a common clock system and Word Select signal. The I

2

S clock

system can be configured as Master or Slave.

Table 6: Multi-mode video output connections (DV1, DV2, DV3)

Signal Port 656 mode Semi-planar

10-bit 8-bit 20-bit 16-bit

DV1_DATA [9:2] DV1 YUV [9:0] YUV [7:0] Y [9:0] Y [9:2]

DV1_DATA [1:0] not used not used

DV2_DATA [9:2] DV2 YUV [9:0] YUV [7:0] UV [9:0] UV [9:2]

DV2_DATA [1:0] not used not used

DV3_DATA [9:2] DV3 YUV [9:0] YUV [7:0] not used not used

DV3_DATA [1:0] not used

Table 7: Multi-mode video input connections (DV4, DV5)

Signal Port 656 mode Semi-planar

10-bit 8-bit 20-bit 16-bit

DV4_DATA [9:2] DV4 YUV [9:0] YUV [7:0] Y [9:0] Y [9:2]

DV4_DATA [1:0] not used not used

DV5_DATA [9:2] DV5 not used YUV [7:0] UV [9:0] UV [9:2]

DV5_DATA [1:0] not used not used

Fig 4. Audio interface

DLINK

AVIP2

IN1

I2S-IN-SD1

DLINK2

PNX2015

DLINK1

IN2

I2S-IN-SD2

IN3

I2S-IN-SD3

IN4

I2S-IN-SD4

IN5

I2S-IN-SD5

IN6

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

I2S-IN-SD6

PNX3000-2

PNX8550

L, R

C, SW

SL, SR

SUB delayed

MAIN delayed

PNX3000-1

I2S-OUT-SD1

speakers, headphones,

line-out

C, SW processed

SL, SR processed

MAIN not delayed

PNX8550

L, R processed

PNX8550

SUB not delayed

I2S-OUT-SD2

I2S-OUT-SD4

I2S-OUT-SD6

DLINK

AVIP1

12 DACS

IN1

IN2

IN3

IN4

IN5

IN6

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

I2S-OUT-SD3

I2S-OUT-SD5

I2S-OUT-SD6

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Figure 4 shows the interconnections between the two AVIP instances and the connections

to the I

2

S device pins. The legend shows the suggested signal content when used with

PNX8550, although the assignment of signals to the I

2

S channels and DAC outputs is fully

flexible. Audio DACs are only present on AVIP1, otherwise the two AVIP audio sections

are identical.

In single MPIF AvPip mode the suggested routing of the sub channel is to I2S_OUT_SD4.

2.3.3 Audio/video flow

Fig 5. Audio/video flow diagram

I

2

C-bus UART AV linkkeyboard

to flat panel

display

PNX8550

video

coprocessor

PNX3000

PNX8550

dual SD or single

HD input

(TDA9975)

speakers

remote

control

PNX2015

MEMORY

BASED SCALER

VIDEO MPEG

DECODER

DEMDEC 1

DSP

DEMDEC 2

DSP

AUDIO 1

DSP

MUX

VO-2

HUB

DV2

DV1

DV3

DV5

DV4

DLINK1

DLINK2

VO-1

VIP

NORTH TUNNEL SOUTH TUNNEL

MEMORY CONTROLLER

16-BIT 200 MHz DDR

16

COLUMBUS

AUDIO 2

DSP

LVDS

TV MICROCONTROLLER SUBSYSTEM

VIDDEC 1

VIDDEC 2

12 × DACS

direct

stream

30

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2.3.4 Control

The AVIP and Columbus subsystems are controlled via I

2

C interfaces as shown in

Figure 6

.

The main method of control for the HD subsystem is via MMIO commands across the

south tunnel interface, once the tunnel is initialized using the I

2

C.

The TV Microcontroller has a master/slave I

2

C interface, which is mainly used by the TV

Microcontroller to control the devices in the system.

The I

2

C module implements a master/slave I

2

C interface with integrated shift register

timing generation and slave address recognition. It is compliant to the I

2

C specification

Ref. 1

. The I

2

C standard mode (100 KHz SCL) and fast mode (400 KHz SCL) are

supported. Extended 10-bit addressing is not supported.

Table 8: Control interface

Block Sub-address Sub-address width Data width

AVIP1 8A(W), 8B(R) 32-bit 32-bit

AVIP2 88(W), 89(R) 32-bit 32-bit

Columbus B0(W), B1(R) 8-bit 8-bit

HD subsystem A0(W), A1(R) 32-bit 32-bit

TV Microcontroller via SW config 8-bit 8-bit

Fig 6. Control interface

TV

MICROCONTROLLER

TV MICROCONTROLLER

I

2

C-bus interface

address

sub-address width

data width

UART

refer to microcontroller section

master/slave 400 kHz

via SW config

8-bit

HD

I

2

C-bus interface

address

sub-address width

data width

TUNNEL

refer to HD section

slave 400 kHz

A0(W), A1(R)

32-bit

UART

I

2

C_µP

tunnel

south

I

2

C_HD

I

2

C_COL

I

2

C_AVIP

HD SUBSYSTEM

COLUMBUS

interface

address

sub-address width

data width

slave 400 kHz

B0(W), B1(R)

8-bit

COLUMBUS

AVIP2

interface

address

sub-address width

data width

slave 400 kHz

88(W), 89(R)

32-bit

AVIP2

AVIP1

interface

address

sub-address width

data width

slave 400 kHz

8A(W), 8B(R)

32-bit

AVIP1

PNX2015

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2.3.5 Test (JTAG)

A JTAG interface is used for both IC testing via a TAP controller and boundary scan. A

single boundary scan chain is provided for the whole of the PNX2015. Pads that are not

included in the boundary scan chain are:

• Power supplies.

• Analog input and output.

• DDR/GDDR SDRAM Interface.

• LVDS interface.

The Boundary Scan Description Language (BSDL) file detailing the TAP Controller ID and

Instructions is available on request from Philips Semiconductors.

2.4 Top level structure

The following paragraphs describe the top-level structure of the PNX2015 with respect to

clocking, reset, interrupts and power supplies. Details of the subsystem implementation

can be found in Section 2.5

.

2.4.1 Clocking

The PNX2015 requires two clock sources, one for the TV Microcontroller subsystem and

one for the remaining subsystems. These may be from a clock generator source, or from a

crystal. See Figure 8

.

The TV Microcontroller supports either 16 MHz or 24 MHz external crystal.

The HD, AVIP1 and AVIP2 require a clock of 27 MHz. Columbus receives a clock from

either AVIP1 or AVIP2, depending on the selected input source. To ensure

synchronization of video streams processed across the PNX8550 and PNX2015 devices,

the 27 MHz is be supplied from PNX8550.

See PNX2015 Limitations Section 8.1

for voltage divider network.

Remark: An external crystal may be used for testing purposes only.

2.4.2 Reset

The PNX2015 has two external reset signals, one for the TV Microcontroller subsystem,

and one for the remaining subsystems. This is shown in Figure 7

and Figure 8. The TV

Microcontroller reset is active high and held high for at least 30 clock cycles after the

crystal frequency has become stable.

The reset for AVIP1 and AVIP2, Columbus and the HD subsystem is derived from a single

input. The signal is active low and held low for at least 30 clock cycles after the 27 MHz

clock is applied. The reset signal is extended within the subsystems for up to 1.2 ms to

allow for all blocks to initialize correctly. After the 1.2 ms period communication with the

subsystems can commence.

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2.4.3 Interrupts

The PNX2015 has an interrupt structure based on the individual subsystems. The details

of all interrupt sources and control can be found in the subsystem descriptions.

The PNX2015 provides:

• Four interrupt outputs, one each from AVIP1 and AVIP2 and two from the HD

• Four interrupt inputs, two for the TV Microcontroller and two for the HD

Fig 7. Reset path for PNX2015

PNX2015 Main

Part

PNX8550

PNX2015

Microcontroller

Reset uC

(positive logic)

Reset

PNX8550

Reset

System

MC_RESET

IO port

RESET_IN

SYS_RSTN_OUTRESET_IN

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2.4.4 Power supplies

The PNX2015 requires the following:

• 1.2 V for core logic

• 2.5 V for DDR-SDRAM and tunnel interfaces

• 3.3 V for periphery (excluding DDR and Tunnel)

and for the TV Microcontroller:

• 1.2 V for MC core

• 3.3 V for MC periphery

Columbus input video data is clocked by AVIP1/2

Fig 8. Clock, reset and interrupts

TV

MICROCONTROLLER

XTAL

RST

INT0

INT1

HD_EXINT0

HD_EXINT1

MC_RESET

RESET_IN

reset

16 MHz

or 24 MHz

27 MHz

or XTAL

HD SUBSYSTEM

INT_HD1

INT_HD2

INTAVIP1

INTAVIP2

COLUMBUS

AVIP2

PNX2015

AVIP1

27 MHz

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2.5 Subsystems

The following paragraphs describe in more detail the functions of the various subsystems.

The processor referred to by the term CPU has different meanings depending on where it

occurs in this User Manual:

• In the DDR SDRAM section of the HD subsystem, CPU refers to a low latency MTL

port of DDR SDRAM controller.

• In the TV microcontroller section CPU refers to the PNX2015 TV micro core

processor.

• In the remainder of the document, CPU refers to a processor in the PNX8550 (MIPS

or Trimedia).

2.5.1 AVIP1 and AVIP2

Each AVIP performs input decoding of single stream analog audio and single stream

analog video signals. In addition, AVIP1 provides processing and presentation of all audio

output streams in the system.

The AVIPs support the following features:

• Detection of PAL, NTSC or SECAM, and various 1f

H

and 2f

H

component video input

sources.

• Full support for 1f

H

and 2f

H

video sources; progressive and interlaced.

• Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).

• ITU-656 output interface.

• Global multi-standard audio demodulation and decoding.

• Dolby

®

Pro Logic

®

II multi-channel audio decoding and post-processing.

• Advanced fully programmable audio post-processing functions, including

psychoacoustic spatial algorithms for optimal loudspeaker matching.

Fig 9. Subsystem power supplies

PNX2015

AVIP1

1.2 V

3.3 V

2.5 V

1.2 V

3.3 V

GND

AVIP2

HD SUBSYSTEM

COLUMBUS

TV

MICROCONTROLLER

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2.5.2 Columbus

This block provides the following picture improvement functions:

• Enhanced 2D comb for PAL and NTSC.

• 3D field comb for PAL and NTSC.

• 3D frame comb for PAL and NTSC.

• Spatial noise reduction for all component video standards.

• Temporal noise reduction for all component video standards.

The comb filter is controlled via a separate I

2

C interface on the PNX2015, this is to ensure

registers containing measurement are accessed at appropriate times. The measurement

information is also available as ancillary data within the video stream (ITU-656).

For certain features of the comb filter access to external memory is required. The

PNX2015 has a unified memory that both comb filter and HD subsystem’s share

concurrently.

A functional block diagram is shown in Figure 140

.

2.5.3 HD subsystem (High Definition)

The HD subsystem performs MPEG video decoding for up to MP@HL streams. It

interfaces with PNX8550 and video coprocessor via tunnel interfaces (high bandwidth, low

pin count interface), HD/SD video using DV4 and DV5 inputs and PNX8550 using DV1,

DV2 and DV3 outputs.

The HD subsystem can also perform horizontal and vertical scaling of video images, and

perform a range of video measurements on a stream.

A functional block diagram of the HD subsystem is shown in Figure 164

.

2.5.4 LVDS transmission interface

The LVDS transmission interface connects to compatible LCD and flat panel displays. The

block uses the LVDS technology as per the TIA/EIA standard. The protocol for video

output encoding is selectable and can be THine™ or National™ semiconductors format.

The following features are supported in the LVDS transmitter IP:

• Single-link transmission of RGB video pixel data.

Up to 30 bits of RGB pixel data, synchronization signals (HS and VS), data valid

indication signal (DE), and up to two user-defined control bits (UD1 and UD2) sampled

at the input using a 13.5 MHz to 86 MHz input clock.

• Transmission of two user defined control bits with four selectable values for each bit.

• Either 30, 24 or 18 bpp (i.e. 10, 8 or 6 bits-per-component) selectable video data

transmission formats.

• Selectable polarity for the data valid (DE) input signal - programmable high or low

level to designate (qualify) active video data.

• Support for selectable output transmission formats:

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National™ semiconductor and THine™ formats for 18, 24 and 30 bits per pixel.

• Optional substitution of invalid pixel data by zero (RGB) values.

• Selectable diagnostic modes (stress test and pattern test).

• Selectable clock strobe - positive or negative edge of the clock for input data

sampling.

An example of a system set-up is shown in Figure 245

.

2.5.5 TV Microcontroller

The TV Microcontroller is the system power controller and supports the following

functions:

• System power management; control and detection of power supplies.

• User interfacing via keyboard or remote control.

• Communication with external sources via AV_LINK Ref. 4.

The TV Microcontroller subsystem consists of an 80C51 core, together with extended

memory and peripherals required for TV systems.

The TV Microcontroller is isolated from the other (Main) subsystems within the PNX2015,

having its own power domain with 1.2 V and 3.3 V supplies, together with separate

clocking and reset. This allows the TV Microcontroller to be active while all other

subsystems are inactive, by either clock being disabled, or powered down, or by being

held indefinitely in reset as shown in Tabl e 9

.

The above table is the only legal reference to Power Down modes. This table supersedes

all other imported IP references to Power Down modes that may be embedded within the

User Manual. Any references outside of this table should be considered illegal. The

Standby and Power Down modes embedded in IP blocks should not be used.

A functional block diagram is shown in Figure 253

.

2.6 External memory requirements

The PNX2015 requires two external memories:

Table 9: Power supply connections for standby and other subsystem power saving modes

Signal/Supply

description

Signal/Supply Pin

name

Power down

(Standby)

Clk disabled

(27MHz)

Indefinite Reset Main PNX2015

Operational

3.3V Main VDDD3.3V Not powered Powered Powered Powered

2.5V Main VDDD2.5V Not powered Powered Powered Powered

1.2V Main VDDD1.2V Not powered Powered Powered Powered

27 MHz CLK XTALI Disabled Disabled Enabled Enabled

Reset Main (active

low)

RESET_IN Low Low Low High

3.3V Micro VDDD(MCIO) Powered Powered Powered Powered

1V2 Micro VDDD(MC_CORE) Powered Powered Powered Powered

Reset Micro (active

high)

MC_Reset Low Low Low Low

User manual Rev. 01 – 6 May 2005 18 of 795

Philips Semiconductors

UM10113

PNX2015 User Manual

• 512 k bit (64 × 8) SPI Flash connected to the TV Microcontroller via the Motorola

SPI™ interface. This enables the Microcontroller to download code during the initial

boot sequence.The SPI is a master only, and cannot be used in slave mode. (See

Section 7.14.3

).

• 64 Mbits, 128 Mbits or 256 Mbits (8 MB, 16 MB or 32 MB) DDR

1

SDRAM connected

to the DDR memory controller interface. See memory controller Section 5.1.14

.

2.7 Power management

The PNX2015 has two separate power domains for the device. The first is for the TV

Microcontroller subsystem the second is for the remaining AVIP, Columbus and HD

subsystems. There are various modes with associated levels of power dissipation for the

PNX2015. The following lists the modes in increasing level of power consumption.

Mode 1

Power is applied to the TV Microcontroller only. The TV Microcontroller is running from the

16 (or 24) MHz XTAL. All TV Microcontroller functions are available.

Mode 2

27 MHz clock is applied to the system and all subsystems are active.

2.7.1 Power supply sequencing

On power-up, the clock module will output all clocks to modules, defaulting to the 27 MHz

xtal_clk clock. Reset of all modules and the boot-up sequence executed by the Boot block

will run on the 27 MHz clock. During boot up the boot block will program all PLLs with their

operating frequencies. After the 300 us PLL settling time, the boot block will set the

exit_reset registers for these clocks and the clock module will switch these bus clocks from

27 MHz xtal_clk to their individual frequencies.

Power ON sequence

1. Apply power to V

DDD1.2V

.

2. Allow V

DDD1.2V

to stabilize (approx.100 ms).

3. Apply power to V

DDD2.5V

.

4. Apply power to V

DDD3.3V

.

When the power supply to the TV Microcontroller is applied first, the same ordering of

power supply sequence is used; firstly for the TV Microcontroller and subsequently the

remainder of the PNX2015.

Power OFF sequence

1. Power may be removed simultaneously from V

DDD3.3V

, V

DDD2.5V

and V

DDD1.2V

.

2. Otherwise, remove V

DDD3.3V

followed by V

DDD2.5V

and V

DDD1.2V.

1. For frequencies equal to or below 200Mhz use DDR, for frequencies above 200MHz GDDR should be used.

User manual Rev. 01 – 6 May 2005 19 of 795

Philips Semiconductors

UM10113

PNX2015 User Manual

Remark: If supply sequencing is used and other parts of the system are powered ahead

of the PNX2015, it is important to ensure that the 3.3 V supply to the PNX2015 is cleanly

applied. i.e. no back-feeding of 3.3 V supply from other devices (or higher voltage rails that

are powered first). This can occur with pull-ups or termination resistors to a system 5 V

supply (e.g. I

2

C) or to an inappropriate 3.3 V rails.

2.7.2 Low-power modes

The TV Microcontroller has two power-saving modes: Idle and Power-down, which are

controlled by the PCON SFR. AVIP blocks are put into a low-power standby mode by

disabling all PLLs. See Section 3.10.9.2

.

User manual Rev. 01 – 6 May 2005 20 of 795

Philips Semiconductors

UM10113

PNX2015 User Manual

3. AVIP1 and AVIP2

3.1 Introduction

Figure 10 shows a diagram of the AVIP block.

Each AVIP provides the following functionality:

• Detection of PAL, NTSC or SECAM, and various 1f

H

and 2f

H

component video input

sources.

• Full support for 1f

H

and 2f

H

video sources; progressive and interlaced.

• Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).

• ITU-656 output interface.

Fig 10.AVIP block diagram

DLINK

DCU

ITU-656

I2C

GTU

BCU

Sound Core

SDACS

(

AVIP1 onl

y)

VIDDEC

ITU-656

1fh/2fh

10-bit data

PI-Bus

X4 X6 X2

Video data CVBS, Y/C, YUV

54MHz clock 27/54 Msam

p

les/sec

Audio data SIF or L/R

I2C

Bus

INT

27MHz

clk

6x I2S

In

p

uts

6x I2S

Outputs

DLINK1 DLINK2 DLINK3

HSYNC

HSYNC/VSYNC

PNX3000

interface (2

stereo/4 mono)

Clock generation

and Distribution

Clock Distribution

Clocks to

AVIP2

Clocks from

AVIP1

AVIP2

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