List of Figures
TIM08 Reference Manual — Rev. 1.0
16 List of Figures MOTOROLA
Table Title Page
29 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .79
30 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . .80
31 Unbuffered PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .82
32 Timer Channel Status
and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . . .84
33 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
34 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .89
35 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . .90
36 Buffered PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
37 Timer Channel Status
and Control Registers (TSC0, TSC2) . . . . . . . . . . . . . . .94
38 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
39 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .99
40 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . .102
41 CPU Counter Overflow Interrupt Timing Example A . . . . .106
42 CPU Counter Overflow Interrupt Timing Example B . . . . .107
43 CPU Input Capture Interrupt Timing Example . . . . . . . . . .108
44 CPU Output Compare/PWM Interrupt Example. . . . . . . . .110
45 DMA Input Capture Service Request Timing Example . . .112
46 DMA Output Compare/PWM Service Request Example . .114
47 RC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
48 25% Duty Cycle PWM Signal. . . . . . . . . . . . . . . . . . . . . . .131
49 10 kHz, 50% Duty Cycle RC Transient Response . . . . . . .133
50 10-kHz, 50% Duty Cycle RC Response. . . . . . . . . . . . . . .134
51 Buffered Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
52 PD Loop Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
53 Servo Loop Motor Control Block Diagram . . . . . . . . . . . . .140
54 Waveform On Output Compare Pin (PTE5). . . . . . . . . . . .145
55 Internal Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
56 Timer Status and Control Register (TSC) . . . . . . . . . . . . .156
57 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . .158
58 Timer Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . .160
59 Timer Counter Modulo Registers (TMODH:TMODL) . . . . .161
60 Timer Channel Status
and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . .163
61 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
62 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . .169
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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