Acer B0W03AV Datasheet

Category
Processors
Type
Datasheet
Document Number: 326768-004
Mobile 3rd Generation Intel
®
Core™
Processor Family
Datasheet – Volume 1 of 2
September 2012
2 Datasheet, Volume 1
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Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel SpeedStep
®
Technology; See the Processor Spec Finder or contact your Intel representative for more information.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel
®
64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
No computer system can provide absolute security under all conditions. Intel
®
Trusted Execution Technology (Intel
®
TXT) requires
a computer system with Intel
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
Group and specific software for some uses. For more information, see http://www.intel.com/technology/security/.
Intel
®
Virtualization Technology requires a computer system with an enabled Intel
®
processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Intel
®
Active Management Technology requires the computer system to have an Intel® AMT-enabled chipset, network hardware
and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the
purchaser and may require scripting with the management console or further integration into existing security frameworks to
enable certain functionality. It may also require modifications of implementation of new business processes. With regard to
notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting
wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see http://www.intel.com/technology/
platform-technology/intel-amt/.
Intel
®
Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/
technology/turboboost.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See www.intel.com/products/processor_number for details.
Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced
for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or
marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user.
Intel, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All rights reserved.
Datasheet, Volume 1 3
Contents
1Introduction............................................................................................................11
1.1 Processor Feature Details ...................................................................................13
1.1.1 Supported Technologies ..........................................................................13
1.2 Interfaces ........................................................................................................13
1.2.1 System Memory Support.........................................................................13
1.2.2 PCI Express* .........................................................................................14
1.2.3 Direct Media Interface (DMI)....................................................................15
1.2.4 Platform Environment Control Interface (PECI)...........................................16
1.2.5 Processor Graphics.................................................................................16
1.2.6 Embedded DisplayPort* (eDP*)................................................................17
1.2.7 Intel
®
Flexible Display Interface (Intel
®
FDI).............................................17
1.3 Power Management Support ...............................................................................17
1.3.1 Processor Core.......................................................................................17
1.3.2 System.................................................................................................17
1.3.3 Memory Controller..................................................................................17
1.3.4 PCI Express* .........................................................................................17
1.3.5 Direct Media Interface (DMI)....................................................................17
1.3.6 Processor Graphics Controller (GT) ...........................................................18
1.3.7 Thermal Management Support .................................................................18
1.4 Processor Family SKU Definition..........................................................................18
1.5 Package...........................................................................................................19
1.6 Processor Compatibility......................................................................................19
1.7 Terminology .....................................................................................................20
1.8 Related Documents ...........................................................................................23
2Interfaces................................................................................................................25
2.1 System Memory Interface ..................................................................................25
2.1.1 System Memory Technology Supported.....................................................25
2.1.2 System Memory Timing Support...............................................................26
2.1.3 System Memory Organization Modes.........................................................27
2.1.3.1 Single-Channel Mode.................................................................27
2.1.3.2 Dual-Channel Mode – Intel
®
Flex Memory Technology Mode ........... 27
2.1.4 Rules for Populating Memory Slots............................................................28
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA)..........29
2.1.5.1 Just-in-Time Command Scheduling..............................................29
2.1.5.2 Command Overlap....................................................................29
2.1.5.3 Out-of-Order Scheduling............................................................29
2.1.6 Data Scrambling ....................................................................................29
2.1.7 DRAM Clock Generation...........................................................................29
2.1.8 DDR3 Reference Voltage Generation .........................................................30
2.2 PCI Express* Interface.......................................................................................30
2.2.1 PCI Express* Architecture .......................................................................30
2.2.1.1 Transaction Layer .....................................................................31
2.2.1.2 Data Link Layer ........................................................................31
2.2.1.3 Physical Layer ..........................................................................31
2.2.2 PCI Express* Configuration Mechanism .....................................................32
2.2.3 PCI Express* Graphics ............................................................................33
2.2.3.1 PCI Express* Lanes Connection ..................................................33
2.3 Direct Media Interface (DMI)...............................................................................34
2.3.1 DMI Error Flow.......................................................................................34
2.3.2 Processor / PCH Compatibility Assumptions................................................34
4 Datasheet, Volume 1
2.3.3 DMI Link Down.......................................................................................34
2.4 Processor Graphics Controller (GT).......................................................................35
2.4.1 3D and Video Engines for Graphics Processing ............................................35
2.4.1.1 3D Engine Execution Units..........................................................35
2.4.1.2 3D Pipeline...............................................................................36
2.4.1.3 Video Engine ............................................................................36
2.4.1.4 2D Engine ................................................................................37
2.4.2 Processor Graphics Display ......................................................................38
2.4.2.1 Display Planes ..........................................................................38
2.4.2.2 Display Pipes............................................................................39
2.4.2.3 Display Ports ............................................................................39
2.4.2.4 Embedded DisplayPort* (eDP*)...................................................39
2.4.3 Intel
®
Flexible Display Interface (Intel
®
FDI) .............................................39
2.4.4 Multi Graphics Controllers Multi-Monitor Support.........................................40
2.5 Platform Environment Control Interface (PECI) ......................................................40
2.6 Interface Clocking..............................................................................................40
2.6.1 Internal Clocking Requirements ................................................................40
3 Technologies............................................................................................................41
3.1 Intel
®
Virtualization Technology (Intel
®
VT)..........................................................41
3.1.1 Intel
®
Virtualization Technology (Intel
®
VT) for
IA-32, Intel
®
64 and Intel
®
Architecture
(Intel
®
VT-x) Objectives..........................................................................41
3.1.2 Intel
®
Virtualization Technology (Intel
®
VT) for
IA-32, Intel
®
64 and Intel
®
Architecture
(Intel
®
VT-x) Features ............................................................................42
3.1.3 Intel
®
Virtualization Technology (Intel
®
VT) for Directed
I/O (Intel
®
VT-d) Objectives ....................................................................42
3.1.4 Intel
®
Virtualization Technology (Intel
®
VT) for Directed
I/O (Intel
®
VT-d) Features.......................................................................43
3.1.5 Intel
®
Virtualization Technology (Intel
®
VT) for Directed
I/O (Intel
®
VT-d) Features Not Supported..................................................43
3.2 Intel
®
Trusted Execution Technology (Intel
®
TXT) .................................................44
3.3 Intel
®
Hyper-Threading Technology (Intel
®
HT Technology)....................................44
3.4 Intel
®
Turbo Boost Technology............................................................................45
3.4.1 Intel
®
Turbo Boost Technology Frequency...................................................45
3.4.2 Intel
®
Turbo Boost Technology Graphics Frequency.....................................46
3.5 Intel
®
Advanced Vector Extensions (Intel
®
AVX)....................................................46
3.6 Security and Cryptography Technologies...............................................................47
3.6.1 Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI) ........47
3.6.2 PCLMULQDQ Instruction ..........................................................................47
3.6.3 RDRAND Instruction................................................................................47
3.7 Intel
®
64 Architecture x2APIC.............................................................................48
3.8 Supervisor Mode Execution Protection (SMEP) .......................................................49
3.9 Power Aware Interrupt Routing (PAIR)..................................................................49
4 Power Management .................................................................................................51
4.1 Advanced Configuration and Power Interface
(ACPI) States Supported.....................................................................................52
4.1.1 System States........................................................................................52
4.1.2 Processor Core / Package Idle States.........................................................52
4.1.3 Integrated Memory Controller States.........................................................52
4.1.4 PCI Express* Link States .........................................................................53
4.1.5 Direct Media Interface (DMI) States ..........................................................53
4.1.6 Processor Graphics Controller States .........................................................53
4.1.7 Interface State Combinations ...................................................................53
4.2 Processor Core Power Management......................................................................54
Datasheet, Volume 1 5
4.2.1 Enhanced Intel
®
SpeedStep
®
Technology..................................................54
4.2.2 Low-Power Idle States ............................................................................55
4.2.3 Requesting Low-Power Idle States............................................................56
4.2.4 Core C-states ........................................................................................57
4.2.4.1 Core C0 State...........................................................................57
4.2.4.2 Core C1 / C1E State..................................................................57
4.2.4.3 Core C3 State...........................................................................57
4.2.4.4 Core C6 State...........................................................................57
4.2.4.5 Core C7 State...........................................................................58
4.2.4.6 C-State Auto-Demotion .............................................................58
4.2.5 Package C-States...................................................................................58
4.2.5.1 Package C0..............................................................................60
4.2.5.2 Package C1/C1E .......................................................................60
4.2.5.3 Package C3 State......................................................................60
4.2.5.4 Package C6 State......................................................................60
4.2.5.5 Package C7 State......................................................................61
4.2.5.6 Dynamic L3 Cache Sizing...........................................................61
4.3 Integrated Memory Controller (IMC) Power Management ........................................61
4.3.1 Disabling Unused System Memory Outputs ................................................61
4.3.2 DRAM Power Management and Initialization...............................................62
4.3.2.1 Initialization Role of CKE............................................................63
4.3.2.2 Conditional Self-Refresh ............................................................63
4.3.2.3 Dynamic Power Down Operation .................................................64
4.3.2.4 DRAM I/O Power Management....................................................64
4.3.3 DDR Electrical Power Gating (EPG) ...........................................................64
4.4 PCI Express* Power Management........................................................................65
4.5 DMI Power Management.....................................................................................65
4.6 Graphics Power Management ..............................................................................65
4.6.1 Intel
®
Rapid Memory Power Management (Intel
®
RMPM)
(also known as CxSR).............................................................................65
4.6.2 Intel
®
Graphics Performance Modulation Technology (Intel
®
GPMT).............. 65
4.6.3 Graphics Render C-State.........................................................................66
4.6.4 Intel
®
Smart 2D Display Technology (Intel
®
S2DDT) .................................. 66
4.6.5 Intel
®
Graphics Dynamic Frequency..........................................................66
4.6.6 Display Power Savings Technology 6.0 (DPST) ...........................................67
4.6.7 Automatic Display Brightness (ADB) .........................................................67
4.6.8 Intel
®
Seamless Display Refresh Rate Switching
Technology (Intel
®
SDRRS Technology) ....................................................67
4.7 Graphics Thermal Power Management..................................................................68
5 Thermal Management..............................................................................................69
5.1 Thermal Considerations......................................................................................69
5.2 Intel
®
Turbo Boost Technology Power Monitoring...................................................70
5.3 Intel
®
Turbo Boost Technology Power Control .......................................................70
5.3.1 Package Power Control............................................................................70
5.3.2 Power Plane Control................................................................................72
5.3.3 Turbo Time Parameter ............................................................................72
5.4 Configurable Thermal Design Power (cTDP) and
Low Power Mode (LPM) ......................................................................................72
5.4.1 Configurable TDP (cTDP).........................................................................72
5.4.2 Low Power Mode ....................................................................................73
5.5 Thermal and Power Specifications........................................................................74
5.6 Thermal Management Features ...........................................................................77
5.6.1 Adaptive Thermal Monitor........................................................................77
5.6.1.1 TCC Activation Offset ................................................................78
5.6.1.2 Frequency / Voltage Control.......................................................78
5.6.1.3 Clock Modulation ......................................................................80
6 Datasheet, Volume 1
5.6.2 Digital Thermal Sensor ............................................................................80
5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy) ................................81
5.6.2.2 Fan Speed Control with Digital Thermal Sensor .............................81
5.6.3 PROCHOT# Signal ..................................................................................81
5.6.3.1 Bi-Directional PROCHOT#...........................................................81
5.6.3.2 Voltage Regulator Protection versus PROCHOT#............................82
5.6.3.3 Thermal Solution Design and PROCHOT# Behavior ........................82
5.6.3.4 Low-Power States and PROCHOT# Behavior..................................82
5.6.3.5 THERMTRIP# Signal ..................................................................83
5.6.3.6 Critical Temperature Detection....................................................83
5.6.4 On-Demand Mode...................................................................................83
5.6.4.1 MSR Based On-Demand Mode.....................................................83
5.6.4.2 I/O Emulation-Based On-Demand Mode .......................................83
5.6.5 Memory Thermal Management..................................................................84
5.6.6 Platform Environment Control Interface (PECI) ...........................................84
6 Signal Description....................................................................................................85
6.1 System Memory Interface Signals........................................................................86
6.2 Memory Reference and Compensation Signals .......................................................88
6.3 Reset and Miscellaneous Signals ..........................................................................88
6.4 PCI Express*-based Interface Signals...................................................................89
6.5 Embedded DisplayPort* (eDP*) Signals ................................................................89
6.6 Intel
®
Flexible Display (Intel
®
FDI) Interface Signals..............................................89
6.7 Direct Media Interface (DMI) Signals....................................................................90
6.8 Phase Lock Loop (PLL) Signals.............................................................................90
6.9 Test Access Points (TAP) Signals..........................................................................90
6.10 Error and Thermal Protection Signals....................................................................91
6.11 Power Sequencing Signals...................................................................................92
6.12 Processor Power Signals .....................................................................................93
6.13 Sense Signals....................................................................................................93
6.14 Ground and Non-Critical to Function (NCTF) Signals ...............................................94
6.15 Processor Internal Pull-Up / Pull-Down Resistors ....................................................94
7 Electrical Specifications ...........................................................................................95
7.1 Power and Ground Pins.......................................................................................95
7.2 Decoupling Guidelines ........................................................................................95
7.2.1 Voltage Rail Decoupling...........................................................................95
7.2.2 PLL Power Supply ...................................................................................95
7.3 Voltage Identification (VID).................................................................................96
7.4 System Agent (SA) Vcc VID ................................................................................99
7.5 Reserved or Unused Signals................................................................................99
7.6 Signal Groups .................................................................................................100
7.7 Test Access Port (TAP) Connection.....................................................................102
7.8 Component Storage Condition Specifications (Prior to Board Attach).......................102
7.9 DC Specifications.............................................................................................103
7.9.1 Voltage and Current Specifications ..........................................................103
7.10 Platform Environmental Control Interface (PECI) DC Specifications.........................110
7.10.1 PECI Bus Architecture............................................................................110
7.10.2 PECI DC Characteristics.........................................................................111
7.10.3 Input Device Hysteresis.........................................................................111
8 Processor Pin, Signal, and Package Information ....................................................113
8.1 Processor Pin Assignments................................................................................113
8.2 Package Mechanical Information........................................................................160
9 DDR Data Swizzling................................................................................................169
Datasheet, Volume 1 7
Figures
1-1 Mobile Processor Platform........................................................................................12
1-2 Mobile Processor Compatibility Diagram ....................................................................19
2-1 Intel
®
Flex Memory Technology Operation.................................................................28
2-2 PCI Express* Layering Diagram................................................................................30
2-3 Packet Flow Through the Layers...............................................................................31
2-4 PCI Express* Related Register Structures in the Processor...........................................32
2-5 PCI Express* Typical Operation 16 Lanes Mapping......................................................33
2-6 Processor Graphics Controller Unit Block Diagram.......................................................35
2-7 Processor Display Block Diagram..............................................................................38
4-1 Processor Power States...........................................................................................51
4-2 Idle Power Management Breakdown of the Processor Cores .........................................55
4-3 Thread and Core C-State Entry and Exit ....................................................................55
4-4 Package C-State Entry and Exit................................................................................59
5-1 Package Power Control............................................................................................71
5-2 Frequency and Voltage Ordering ..............................................................................79
7-1 Example for PECI Host-Clients Connection ............................................................... 110
7-2 Input Device Hysteresis ........................................................................................ 111
8-1 rPGA988B (Socket-G2) Pin Map.............................................................................. 113
8-2 BGA1224 Ballmap (left side).................................................................................. 125
8-3 BGA1224 Ballmap (right side)................................................................................ 126
8-4 BGA1023 Ballmap (left side).................................................................................. 144
8-5 BGA1023 Ballmap (right side)................................................................................ 145
8-6 Processor rPGA988B 2C/GT1 (G24406) Mechanical Package (Sheet 1 of 2) .................. 160
8-7 Processor rPGA988B 2C/GT1 (G24406) Mechanical Package (Sheet 2 of 2) .................. 161
8-8 Processor rPGA988B 2C/GT2 (G23867) Mechanical Package (Sheet 1 of 2) .................. 162
8-9 Processor rPGA988B 2C/GT2 (G23867) Mechanical Package (Sheet 2 of 2) .................. 163
8-10 Processor rPGA988B 4C/GT2 (E95127) Mechanical Package (Sheet 1 of 2)................... 164
8-11 Processor rPGA988B 4C/GT2 (E95127) Mechanical Package (Sheet 2 of 2)................... 165
8-12 Processor BGA1023 2C/GT1 (G24405) Mechanical Package........................................ 166
8-13 Processor BGA1023 2C/GT2 (G23866) Mechanical Package........................................ 167
8-14 Processor BGA1224 4C/GT2 (G26204) Mechanical Package........................................ 168
Tables
1-1 Mobile 3rd Generation Intel
®
Core™ Processor Family SKUs.........................................18
1-2 Terminology..........................................................................................................20
1-3 Related Documents ................................................................................................23
2-1 Processor Mobile DIMM Support Summary by Product .................................................25
2-2 Supported DDR3 / DDR3L / DDR3L-RS SO-DIMM Module Configurations .......................26
2-3 Supported Maximum Memory Size Per DIMM .............................................................26
2-4 DDR3 / DDR3L / DDR3L-RS at 1.5 V System Memory Timing Support ...........................27
2-5 DDR3L / DDR3L-RS System Memory Timing Support...................................................27
2-6 Reference Clock.....................................................................................................40
4-1 System States.......................................................................................................52
4-2 Processor Core / Package State Support....................................................................52
4-3 Integrated Memory Controller States ........................................................................52
4-4 PCI Express* Link States.........................................................................................53
4-5 Direct Media Interface (DMI) States..........................................................................53
4-6 Processor Graphics Controller States.........................................................................53
4-7 G, S, and C State Combinations ...............................................................................53
4-8 D, S, and C State Combination.................................................................................54
4-9 Coordination of Thread Power States at the Core Level................................................56
4-10 P_LVLx to MWAIT Conversion ..................................................................................56
8 Datasheet, Volume 1
4-11 Coordination of Core Power States at the Package Level ..............................................59
4-12 Targeted Memory State Conditions............................................................................64
5-1 Intel
®
Turbo Boost Technology Package Power Control Settings....................................71
5-2 Configurable Thermal Design Power (cTDP) Modes ......................................................73
5-3 Thermal Design Power (TDP) Specifications................................................................75
5-4 Junction Temperature Specification...........................................................................75
5-5 Package Turbo Parameters.......................................................................................76
5-6 Idle Power Specifications .........................................................................................77
6-1 Signal Description Buffer Types ................................................................................85
6-2 Memory Channel A Signals.......................................................................................86
6-3 Memory Channel B Signals.......................................................................................87
6-4 Memory Reference and Compensation.......................................................................88
6-5 Reset and Miscellaneous Signals...............................................................................88
6-6 PCI Express* Graphics Interface Signals ....................................................................89
6-7 Embedded DisplayPort* Signals................................................................................89
6-8 Intel
®
Flexible Display (Intel
®
FDI) Interface .............................................................89
6-9 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface........................90
6-10 Phase Lock Loop (PLL) Signals..................................................................................90
6-11 Test Access Points (TAP) Signals...............................................................................90
6-12 Error and Thermal Protection Signals.........................................................................91
6-13 Power Sequencing Signals .......................................................................................92
6-14 Processor Power Signals ..........................................................................................93
6-15 Sense Signals ........................................................................................................93
6-16 Ground and Non-Critical to Function (NCTF) Signals ....................................................94
6-17 Processor Internal Pull-Up / Pull-Down Resistors.........................................................94
7-1 IMVP7 Voltage Identification Definition ......................................................................96
7-2 VCCSA_VID Configuration........................................................................................99
7-3 Signal Groups1.....................................................................................................100
7-4 Storage Condition Ratings......................................................................................102
7-5 Processor Core (V
CC
) Active and Idle Mode DC Voltage and Current Specifications.........103
7-6 Processor Uncore (V
CCIO
) Supply DC Voltage and Current Specifications.......................105
7-7 Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications .....................105
7-8 System Agent (V
CCSA
) Supply DC Voltage and Current Specifications...........................105
7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications.........................106
7-10 Processor Graphics (V
AXG
) Supply DC Voltage and Current Specifications .....................106
7-11 DDR3 / DDR3L / DDR3L-RS Signal Group DC Specifications........................................107
7-12 Control Sideband and TAP Signal Group DC Specifications..........................................108
7-13 PCI Express* DC Specifications...............................................................................109
7-14 Embedded DisplayPort* DC Specifications................................................................109
7-15 PECI DC Electrical Limits........................................................................................111
8-1 rPGA988B Processor Pin List by Pin Name ................................................................114
8-2 BGA1224 Processor Ball List by Ball Name ...............................................................127
8-3 BGA1023 Processor Ball List by Ball Name ...............................................................146
9-1 DDR Data Swizzling Table – Channel A ....................................................................170
9-2 DDR Data Swizzling Table for Package – Channel B...................................................171
Datasheet, Volume 1 9
Revision History
§ §
Revision
Number
Description Revision Date
001 Initial release April 2012
002
Added Mobile 3rd Generation Intel
®
Core™ i7-3520M, i5-3360M, i5-3320M,
i7-3667U, i5-3427U processors
Updated Table 7-10, Processor Graphics (V
AXG
) Supply DC Voltage and
Current Specifications
June 2012
003
Updated Section 1.5, Package
Removed DDR 1066 MHz support
Updated Table 2-5, DDR3L/DDR3L-RS System Memory Timing Support
Added support for DDR3L-RS
June 2012
004
Minor edits throughout for clarity
Added Mobile 3rd Generation Intel
®
Core™ i7-3940XM, i7-3840QM, i7-
3740QM processors
Removed references to the VCC_DIE_SENSE signal and changed affected
balls in Chapter 8 to “RSVD”.
September 2012
10 Datasheet, Volume 1
Datasheet, Volume 1 11
Introduction
1 Introduction
The Mobile 3rd Generation Intel
®
Core™ processor family is the next generation of 64-
bit, multi-core mobile processors built on 22-nanometer process technology. The
processor is designed for a two-chip platform. The two-chip platform consists of a
processor and a Platform Controller Hub (PCH) and enables higher performance, lower
cost, easier validation, and improved x-y footprint. The processor includes Integrated
Display Engine, Processor Graphics, and an Integrated Memory Controller. The
processor is designed for mobile platforms. The Mobile 3rd Generation Intel
®
Core™
processor family offers either 6 or 16 graphic execution units (EUs). The number of EU
engines supported may vary between processor SKUs. The processor is offered in a
rPGA988B, BGA1224, or BGA1023 package.
The Datasheet provides DC specifications, pinout and signal definitions, interface
functional descriptions, thermal specifications, and additional feature information
pertinent to the implementation and operation of the processor on its respective
platform.
Note: Throughout this document, the Mobile 3rd Generation Intel
®
Core™ processor family
may be referred to simply as “processor”.
Note: Throughout this document, the Mobile 3rd Generation Intel
®
Core™ processor family
refers to the Intel
®
Core™ processors listed in Table 1-1.
Note: Throughout this document, the Intel
®
6 / 7 Series Chipset Platform Controller Hub may
be referred to as “PCH”.
Note: Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Note: The term “MBL” refers to mobile platforms.
Introduction
12 Datasheet, Volume 1
Figure 1-1. Mobile Processor Platform
I
n
t
e
l
®
F
l
e
x
i
b
l
e
D
i
s
p
l
a
y
I
n
t
e
r
f
a
c
e
DMI2 x4
Discrete
Graphics (PEG)
Analog CRT
Gigabit
Network Connection
USB 2.0 / USB 3.0
1
Intel
®
HD Audio
FWH
Super I/O
Serial ATA
DDR3 / DDR3L / DDR3L-RS
PCI Express* 3.0
1 x16 or 2x8
8 PCI Express* 2.0
x1 Ports
(5 GT/s)
SPI
Digital Display x 3
PCI Express*
SPI Flash x 2
LPC
SMBUS 2.0
GPIO
LVDS Flat Panel
WiFi / WiMax
Controller Link 1
Embedded
Display Port
Intel
®
Processor
PECI
Intel
®
Management
Engine
Intel
®
6/7 Series
Chipset Families
Note:
1. USB 3.0 is supported on the Intel
®
7 Series Chipset family only.
Datasheet, Volume 1 13
Introduction
1.1 Processor Feature Details
Four or two execution cores
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256-KB shared instruction / data second-level cache (L2) for each core
Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores
1.1.1 Supported Technologies
•Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O (Intel
®
VT-d)
•Intel
®
Virtualization Technology (Intel
®
VT) for IA-32, Intel
®
64 and Intel
®
Architecture (Intel
®
VT-x)
Intel
®
Active Management Technology (Intel
®
AMT) 8.0
•Intel
®
Trusted Execution Technology (Intel
®
TXT)
•Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
•Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
•Intel
®
Hyper-Threading Technology (Intel
®
HT Technology)
•Intel
®
64 Architecture
Execute Disable Bit
•Intel
®
Turbo Boost Technology
•Intel
®
Advanced Vector Extensions (Intel
®
AVX)
•Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI)
PCLMULQDQ Instruction
RDRAND instruction for random number generation
SMEP – Supervisor Mode Execution Protection
PAIR – Power Aware Interrupt Routing
1.2 Interfaces
1.2.1 System Memory Support
Two channels of DDR3 / DDR3L / DDR3L-RS memory with Unbuffered Small Outline
Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per
channel
Note: 2 DIMMs per channel supported only in Quad-Core rPGA package only
Single-channel and dual-channel memory organization modes
Data burst length of eight for all memory organization modes
System Memory Interface I/O Voltage of 1.35 V and 1.5 V
DDR3, DDR3L, and DDR3L-RS DIMMs / DRAMs running at 1.5 V
DDR3L and DDR3L-RS DIMMs / DRAMS running at 1.35 V
Support memory configurations that mix DDR3 DIMMs / DRAMs with DDR3L /
DDR3L-RS DIMMs / DRAMs running at 1.5 V
64-bit wide channels
Non-ECC, Unbuffered DDR3 / DDR3L / DDR3L-RS SO-DIMMs only
Theoretical maximum memory bandwidth of:
21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
Introduction
14 Datasheet, Volume 1
Processor on-die Reference Voltage (VREF) generation for both DDR3 Read
(RDVREF) and Write (VREFDQ)
1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported
Using 4Gb DRAM device technologies, the largest memory capacity possible is
32
GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory
configuration
Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
Command launch modes of 1N/2N
On-Die Termination (ODT)
Asynchronous ODT
•Intel
®
Fast Memory Access (Intel
®
FMA):
Just-in-Time Command Scheduling
—Command Overlap
Out-of-Order Scheduling
1.2.2 PCI Express*
The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI
Express Base Specification, Revision 3.0, including support for 8.0 GT/s transfer
speeds.
PCI Express* supported configurations in mobile products
The port may negotiate down to narrower widths
Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode
2.5 GT/s, 5.0 GT/s and 8.0 GT/s PCI Express* frequencies are supported
Gen1 Raw bit-rate on the data pins Gen 2 Raw bit-rate on the data pins of 5.0 GT/s,
resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used
to transmit data across this interface. This also does not account for packet
overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per
pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 16 GB/s in each direction
simultaneously, for an aggregate of 32 GB/s when x16 Gen 3
Hierarchical PCI-compliant configuration mechanism for downstream devices
Traditional PCI style traffic (asynchronous snooped, PCI ordering)
Configuration Organization Mobile
1
1x8
Graphics, I/O
2x4
2 2x8 Graphics, I/O
3 1x16 Graphics, I/O
Datasheet, Volume 1 15
Introduction
PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Automatic discovery, negotiation, and training of link out of reset
Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
DMI -> PCI Express* Port 0
DMI -> PCI Express* Port 1
PCI Express* Port 0 -> DMI
PCI Express* Port 1 -> DMI
64-bit downstream address format; however, the processor never generates an
address above 64 GB (Bits 63:36 will always be zeros)
64-bit upstream address format; however, the processor responds to upstream
read transactions to addresses above 64 GB (addresses where any of Bits 63:36
are nonzero) with an Unsupported Request response. Upstream write transactions
to addresses above 64
GB will be dropped.
Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
PCI Express* reference clock is 100-MHz differential clock
Power Management Event (PME) functions
Dynamic width capability
Message Signaled Interrupt (MSI and MSI-X) messages
Polarity inversion
Static lane numbering reversal
Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification
Supports Half Swing “low-power / low-voltage” mode
Note: The processor does not support PCI Express* Hot-Plug.
1.2.3 Direct Media Interface (DMI)
DMI 2.0 support
Four lanes in each direction
5 GT/s point-to-point DMI interface to PCH is supported
Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
Shares 100-MHz PCI Express* reference clock
Introduction
16 Datasheet, Volume 1
64-bit downstream address format; however, the processor never generates an
address above 64 GB (Bits 63:36 will always be zeros)
64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
Supports the following traffic types to or from the PCH:
—DMI -> DRAM
DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
Processor core -> DMI
APIC and MSI interrupt messaging support:
Message Signaled Interrupt (MSI and MSI-X) messages
Downstream SMI, SCI and SERR error indication
Legacy support for ISA regime protocol (PHOLD / PHOLDA) required for parallel
port DMA, floppy drive, and LPC bus masters
DC coupling – no capacitors between the processor and the PCH
Polarity inversion
PCH end-to-end lane reversal across the link
Supports Half Swing “low-power / low-voltage”
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processor supports the PECI 3.0
Specification.
1.2.5 Processor Graphics
The Processor Graphics contains a refresh of the seventh generation graphics core
enabling substantial gains in performance and lower power consumption. Up to
16
EU support.
Next Generation Intel Clear Video Technology HD Support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience
Encode / transcode HD content
Playback of high definition content including Blu-ray Disc*
Superior image quality with sharper, more colorful images
Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
DirectX* Video Acceleration (DXVA) support for accelerating video processing
Full AVC/VC1/MPEG2 HW Decode
Advanced Scheduler 2.0, 1.0, XPDM support
Windows* 7, Windows* XP, OSX, Linux OS Support
DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support
OpenGL* 3.0 support
Datasheet, Volume 1 17
Introduction
1.2.6 Embedded DisplayPort* (eDP*)
Stand alone dedicated port (unlike two generations ago that shared pins with PCIe
interface)
1.2.7 Intel
®
Flexible Display Interface (Intel
®
FDI)
For SKUs with graphics, carries display traffic from the Processor Graphics in the
processor to the legacy display connectors in the PCH
Based on DisplayPort standard
The two Intel FDI links are capable of being configured to support three
independent channels, one for each display pipeline
There are two Intel FDI channels, each one consists of four unidirectional
downstream differential transmitter pairs:
Scalable down to 3X, 2X, or 1X based on actual display bandwidth
requirements
Fixed frequency 2.7 GT/s data rate
Two sideband signals for display synchronization:
FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
One Interrupt signal used for various interrupts from the PCH:
FDI_INT signal shared by both Intel FDI Links
PCH supports end-to-end lane reversal across both links
Common 100-MHz reference clock
1.3 Power Management Support
1.3.1 Processor Core
Full support of ACPI C-states as implemented by the following processor C-states:
C0, C1, C1E, C3, C6, C7
Enhanced Intel SpeedStep Technology
1.3.2 System
S0, S3, S4, S5
1.3.3 Memory Controller
Conditional self-refresh (Intel
®
Rapid Memory Power Management (Intel
®
RMPM))
Dynamic power down
1.3.4 PCI Express*
L0s and L1 ASPM power management capability
1.3.5 Direct Media Interface (DMI)
L0s and L1 ASPM power management capability
Introduction
18 Datasheet, Volume 1
1.3.6 Processor Graphics Controller (GT)
•Intel
®
Rapid Memory Power Management (Intel
®
RMPM) – CxSR
•Intel
®
Graphics Performance Modulation Technology (Intel
®
GPMT)
•Intel
®
Smart 2D Display Technology (Intel
®
S2DDT)
Graphics Render C-State (RC6)
Intel Seamless Display Refresh Rate Switching with eDP port
1.3.7 Thermal Management Support
Digital Thermal Sensor
Intel Adaptive Thermal Monitor
THERMTRIP# and PROCHOT# support
On-Demand Mode
Open and Closed Loop Throttling
Memory Thermal Throttling
External Thermal Sensor (TS-on-DIMM and TS-on-Board)
Render Thermal Throttling
Fan speed control with DTS
1.4 Processor Family SKU Definition
Table 1-1. Mobile 3rd Generation Intel
®
Core™ Processor Family SKUs
Processor
Number
TDP
(W)
IA LFM /
LPM
Frequency
IA Frequency Range GT Frequency Range
T
jMAX
(°C)
i7-3940XM
55
(Down 45, Up 65)
1200 MHz 3.0 GHz up to 3.9 GHz 650 MHz up to 1.35 GHz 105
i7-3920XM
55
(Down:45;Up:65)
1900 MHz
(LPM
enabled)
2.9 GHz up to 3.8 GHz 650 MHz up to 1300 MHz 105
i7-3840QM 45 1200 MHz 2.8 GHz up to 3.8 GHz 650 MHZ up to 1.3 GHz 105
i7-3820QM 45 1200 MHz 2.7 GHz up to 3.7 GHz 650 MHz up to 1250 MHz 105
i7-3740QM 45 1200 MHz 2.7 GHz up to 3.7 GHz 650 MHz up to 1.3 GHz 105
i7-3720QM 45 1200 MHz 2.6 GHz up to 3.6 GHz 650 MHz up to 1250 MHz 105
i7-3520M 35 1200 MHz 2.9 GHz up to 3.6 GHz 650 MHz up to 1250 MHz 105
i5-3360M 35 1200 MHz 2.8 GHz up to 3.5 GHz 650 MHz up to 1200 MHz 105
i5-3320M 35 1200 MHz 2.6 GHz up to 3.3 GHz 650 MHz up to 1200 MHz 105
i7-3667U
17
(Down:14;Up:25)
800 MHz
(LPM
enabled)
2 GHz up to 3.2 GHz 350 MHz up to 1150 MHz 105
i5-3427U
17
(Down:14;Up:25)
800 MHz
(LPM
enabled)
1.8 GHz up to 2.8 GHz 350 MHz up to 1150 MHz 105
Datasheet, Volume 1 19
Introduction
1.5 Package
The processor is available on two packages:
A 37.5 x 37.5 mm rPGA package (rPGA988B)
A 31 x 24 mm BGA package (BGA1023 for dual-core processors or BGA1224 for
quad-core processors)
1.6 Processor Compatibility
The Mobile 3rd Generation Intel
®
Core™ processor family has specific platform
requirements that differentiate it from a 2nd Generation Intel
®
Core™ processor family
mobile processor. Platforms intending to support both processor families need to
address the platform compatibility requirements detailed in Figure 1-2.
Notes:
1. 2G_Core = 2nd Generation Intel
®
Core™ processor family mobile
2. 3G_Core = Mobile 3rd Generation Intel
®
Core™ processor family
Figure 1-2. Mobile Processor Compatibility Diagram
2 x 330 µF
2 x 330 µF +
1 placeholder
VCCIO
VR
VDDQ
VR
VCore
VR
VCCSA
VR
VAXG
VR
DDR3
DDR3/3L
2G_Core: 1.5 V
3G_Core: 1.5 V or
1.35 V
2G_Core: 1.05 V
3G_Core: 1.05 V
VCCIO_SEL#
2G_Core: ‘1’
3G_Core: ‘0’
Need to be disconnected
To use same Voltage!
Mobile
Processor
PCH
VCCSA_VID [1:0]
PEG AC Decoupling
PEG Gen 1,2 – 100 nF
PEG Gen 1,2,3 – 220 nF
*VAXG: 2 ph required for
some SKUs
SVID
PROC_SELECT#
2G_Core: ‘1’
3G_Core: ‘0’
Controls DMI
and FDI
termination
DF_TVS
(* 1.35 V for
BGA DC only)
Introduction
20 Datasheet, Volume 1
1.7 Terminology
Table 1-2. Terminology (Sheet 1 of 3)
Term Description
ACPI Advanced Configuration and Power Interface
ADB Automatic Display Brightness
APD Active Power Down
ASPM Active State Power Management
BGA Ball Grid Array
BLT Block Level Transfer
CLTT Closed Loop Thermal Throttling
CRT Cathode Ray Tube
cTDP Configurable Thermal Design Power
DDDR3L-RS DDR3L Reduced Standby Power
DDR3 Third-generation Double Data Rate SDRAM memory technology
DDR3L DDR3 Low Voltage
DMA Direct Memory Access
DMI Direct Media Interface
DP DisplayPort*
DPST Display Power Savings Technology
DTS Digital Thermal Sensor
EC Embedded Controller
ECC Error Correction Code
eDP* Embedded DisplayPort*
Enhanced Intel
®
SpeedStep
®
Technology
Technology that provides power management capabilities to laptops.
EPG Electrical Power Gating
EU Execution Unit
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-executable,
when combined with a supporting operating system. If code attempts to run in non-
executable memory the processor raises an error to the operating system. This feature
can prevent some classes of viruses or worms that exploit buffer overrun
vulnerabilities and can thus help improve the overall security of the system. See the
Intel
®
64 and IA-32 Architectures Software Developer's Manuals for more detailed
information.
HDMI* High Definition Multimedia Interface
HFM High Frequency Mode
IMC Integrated Memory Controller
Intel
®
64 Technology 64-bit memory extensions to the IA-32 architecture
Intel
®
DPST Intel
®
Display Power Saving Technology
Intel
®
FDI Intel
®
Flexible Display Interface
Intel
®
TXT Intel
®
Trusted Execution Technology
Intel
®
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual Machine Monitor
software enables multiple, robust independent software environments inside a single
platform.
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Acer B0W03AV Datasheet

Category
Processors
Type
Datasheet

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