Contents
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
8 Document Number: 327405-001
8-4 Memory Reference and Compensation ...................................................................74
8-5 Reset and Miscellaneous Signals ...........................................................................74
8-6 PCI Express* Interface Signals .............................................................................75
8-7 DMI - Processor to PCH Serial Interface.................................................................75
8-8 PLL Signals........................................................................................................76
8-9 TAP Signals........................................................................................................76
8-10 Error and Thermal Protection................................................................................77
8-11 Power Sequencing ..............................................................................................78
8-12 Processor Power Signals ......................................................................................78
8-13 Sense Pins.........................................................................................................79
8-14 Future Compatibility............................................................................................79
8-15 Processor Internal Pull Up/Pull Down.....................................................................79
9-1 IMVP7 Voltage Identification Definition ..................................................................82
9-2 VCCSA_VID Configuration....................................................................................89
9-3 Signal Groups ....................................................................................................90
9-4 Storage Condition Ratings....................................................................................93
9-5 Processor Core (VCC) DC Voltage and Current Specifications ....................................94
9-6 Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications ...................96
9-7 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications ..................96
9-8 System Agent (VCCSA) Supply DC Voltage and Current Specifications .......................96
9-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications.......................97
9-10 DDR3 Signal Group DC Specifications ....................................................................97
9-11 Control Sideband and TAP Signal Group DC Specifications........................................98
9-12 PCI Express* DC Specifications.............................................................................99
9-13 PECI DC Electrical Limits....................................................................................100
9-14 Differential Clocks (SSC on) ...............................................................................102
9-15 Differential Clocks (SSC off)...............................................................................102
9-16 Processor Clock Jitter Specifications (cycle-cycle)..................................................102
9-17 System Reference Clock DC and AC Specifications.................................................102
9-18 DDR3 Electrical Characteristics and AC Timings at 1066 MT/s,
VDDQ = 1.5 V ±0.075 V....................................................................................104
9-19 DDR3 Electrical Characteristics and AC Timings at 1333 MT/s,
VDDQ = 1.5 V ±0.075 V....................................................................................105
9-20 DDR3 Electrical Characteristics and AC Timings at 1600 MT/s,
VDDQ = 1.5 V ±0.075 V....................................................................................106
9-21 PCI Express* AC Specification ............................................................................107
9-22 Miscellaneous AC Specifications..........................................................................108
9-23 TAP Signal Group AC Specifications.....................................................................108
9-24 SVID Signal Group AC Specifications ...................................................................109
9-25 VCC Overshoot Specifications.............................................................................115
9-26 Processor Overshoot/Undershoot Specifications ....................................................116
10-1 Alphabetical Ball Listing.....................................................................................120
10-2 Alphabetical Signal Listing..................................................................................131
11-1 Register Terminology ........................................................................................151
11-2 Register Terminology Attribute Modifier ...............................................................152
11-3 Error Status Register.........................................................................................152
11-4 Error Command Registers..................................................................................154
11-5 SMI Command Registers....................................................................................154
11-6 SCI Command Registers....................................................................................155
11-7 Channel 0 ECC Error Log 0.................................................................................156
11-8 Channel 0 ECC Error Log 1.................................................................................157
11-9 Channel 1 ECC Error Log 0.................................................................................157
11-10 Channel 1 ECC Error Log 1.................................................................................158
11-11 Address Decode Channel 0.................................................................................159
11-12 Address Decode Channel 1.................................................................................160