Allegro APEK49107 User guide

Brand: Allegro

Model: APEK49107

Type: User guide

Allegro APEK49107 is a demonstration board designed for Allegro AMT49107 gate driver ICs, enabling users to evaluate the performance and functionality of these devices in various applications. The board features flexible I/O voltage configuration, allowing operation with either 3.3 V or 5 V logic systems. It includes an onboard linear regulator, USB interface, and various jumpers and switches for customization. The APEK49107 provides a convenient platform for experimenting with AMT49107 gate drivers and exploring their capabilities in real-world scenarios.

APEK49107-UM

MCO-0001278

This guide applies to the Allegro APEK49107 demonstration

board, which is designed for Allegro AMT49107 devices. This

guide describes how to change the input/output (I/O) voltage

logic level of the AMT49107 device fitted to the APEK49107.

INTRODUCTION

APEK49107 (identification number EDC174 on solder-side silk

screen) is a demonstration board that carries a soldered-down

AMT49107KEVSR-3-T gate driver IC. This part variant is

Logic I/O Voltage Configuration Guide for Demonstration Board for AMT49107

ABSTRACT

APEK49107

June 2, 2022

Figure 1: APEK49107 Demonstration Board Photograph

configured by default for operation in conjunction with 3.3 V

CMOS logic systems, as are the related features on the board.

To operate the board in conjunction with 5 V CMOS logic

systems, both the device and board should be reconfigured. A

procedure to do this is described in this document along with

another that describes how to reverse the change.

Note that orders can be placed for sample and production

quantities of AMT49107 parts configured by default for 3.3 V

or 5 V logic operation (part numbers AMT49107KEVSR-3-T

and AMT49107KEVSR-5-T, respectively). Further informa-

tion on this can be found in the AMT49107 product datasheet.

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

OVERVIEW

The APEK49107 demonstration board—shown in the photograph

in Figure 1 and in the schematics in Appendix 1—includes:

• AMT49107KEVSR-3-T gate driver IC (U1), default logic

input/output levels configured for 3.3 V operation.

• FT232RL USB UART IC (U3):

□A standard USB-A to USB-Micro-B cable plugged into

connector X8 is used to connect the USB UART IC to a PC

running the Allegro AMT49107 graphical user interface

(GUI).

• DC power connector (X2):

□DC power must comply with the non-volatile memory

(NVM) programming voltage limit and the VBB functional

operating range for the device, as specified in the product

datasheet in effect—between 24 V(minimum) and

50 V(maximum), current limit ≥ 50 mA.

□DC power is connected to the board via connector X2.

□The VBAT pin (X2.1) is positive with respect to the GND

(X2.2) pin.

• On-board linear regulator (U2):

□The regulator provides a DC bias voltage to allow the

AMT49107 discrete control input steady states to be

optionally set by way of DIP switches S1 and S2.

Logic I/O Level Control

Table 1: Equipment Required for Demonstration Board Logic I/O Voltage Change

Item Description Comment

1 AMT49107 Demonstration Board Silk Screen Ident: EDC174

2 USB-A to USB-Micro-B Cable –

3 AMT49107 Graphical User Interface (GUI)

Available at the Allegro software portal at

registration.allegromicro.com/login

4 Bench Power Supply (DC) Rated output voltage ≥ 24 V; Rated output current ≥ 50 mA

5 Oscilloscope or Voltmeter –

6 PC Microsoft Windows 7 or later, USB port available

Demonstration Board

Logic I/O level control must be set for both the AMT49107 gate

driver IC and the FT232RL USB UART IC. However, damage

will not result if an incompatibility exists between the I/O voltage

settings (i.e., if one device is set for 3V3 operation and the other

is set for 5 V operation).

Controls are as follows:

• AMT49107 gate driver IC (U1)

Logic I/O voltage supply and associated logic thresholds are

set by the value of the VIO Voltage Monitor (VLM) bit in the

Config 6 register of the device:

□VLM = 0 sets the device to operate with 3.3 V logic.

□VLM = 1 sets the device to operate with 5 V logic.

To set the VLM bit, the desired value must be written to the

Config 6 register over the serial interface. To retain a new

VLM bit value between power-up events, the new value

must be saved to the internal device non-volatile storage

(EEPROM):

• FT232RL USB UART IC

The I/O voltage of the FT232RL USB UART IC connections

to the AMT49107 is set by the position of jumper J16 on the

demonstration board:

□J16 in the "5V" position sets the I/O voltage to 5 V.

□J16 in the "3V3" position sets the I/O voltage to 3.3 V.

EQUIPMENT

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

This procedure applies to an APEK49107 board that is config-

ured for operation in conjunction with 3.3 V logic systems (i.e.,

the default setting at the point of supply with VLM = 0) and is

to be reconfigured for operation in conjunction with 5 V logic

systems (i.e., VLM = 1).

1. Use the reference designations marked on the PCB compo-

nent-side silk screen to conrm the demonstration board is

congured as follows:

□J1, J2, J3, J8, and J9 are fitted.

□J4 is fitted to “VL-U2”.

□J16 is fitted to “3V3”.

□J17, J18, J19, and J20 are fitted to “X8”.

□S1/1 through S1/3 are set to “OFF”.

□S2/1 through S2/6 are set to “OFF”.

All other jumper and switch states are not relevant to this

procedure. However, additional notes about switch states,

resistors, and voltages are provided in the "Additional Notes

and Considerations" section.

2. Connect X8 to a PC USB port with a standard USB-A to

USB-Micro-B cable.

3. Connect the DC power supply to X2 (X2/1[VBAT] positive

with respect to X2/2[GND]).

4. Adjust the DC power supply that is to be connected such

that the voltage at the VBB terminal of U1 will comply with

the non-volatile memory (NVM) programming voltage limit

and the VBB functional operating range for the device, as

specified in the product datasheet in effect—between 24 V

(minimum) and 50 V (maximum), current limit ≥ 50 mA.

5. Turn on the power supply.

6. Run the AMT49107 GUI on the PC.

7. On the GUI, conrm the SPI Status at the top right of the

main GUI is set to “OK”.

Change Logic I/O Level From 3.3 V to 5 V

HOW TO CHANGE LOGIC

I/O VOLTAGE CONFIGURATION

This section provides procedures needed to change the I/O volt-

age configuration of the APEK49107 and fitted AMT49107 gate

driver IC. The equipment required to change the demonstration

board logic I/O voltage is listed in Table 1. Use one of the two

following procedures, as relevant to your system needs:

• "Change Logic I/O Level From 3.3 V to 5 V"

• "Change Logic I/O Level From 5 V to 3.3 V"

8. Set S1/1, S1/2, S1/3, and S2/1 to “ON”.

9. On the GUI, click on the <Watchdog: Disable> button.

10. Conrm the voltage on the SAL monitor pin is 3.3 V ± 0.5 V.

(i.e., logic I/O is "3V3").

11. On the GUI:

A. Click on the <BRIDGE AND SYSTEM> button.

B. On the drop-down list, set the VIO Voltage Monitor

(VLM) to “5V”.

C. Close the <BRIDGE AND SYSTEM> window.

D. Click on the <NVM Write: SAVE> button.

12. Set S1/1, S1/2, S1/3, and S2/1 to “OFF”.

13. Turn o the power supply.

14. Shut down the GUI.

15. Wait for at least 10 seconds.

16. Move J16 from “3V3” to “5V”.

17. Turn on the power supply.

18. Run the AMT49107 GUI on the PC.

19. On the GUI, conrm the SPI Status at the top right of the

main GUI is set to “OK".

20. Set S1/1, S1/2, S1/3, and S2/1 to “ON”.

21. On the GUI, click on the <Watchdog: Disable> button.

22. Measure the voltage on the SAL monitor pin and conrm it is

5.0 V ± 0.5 V. (i.e., logic I/O is "5V").

23. Set S1/1, S1/2, S1/3, and S2/1 to “OFF”.

24. Turn o the power supply.

25. Shut down the GUI.

If the SAL voltage measured at Step 22 is 5.0 V ± 0.5 V, the board

is now configured for 5 V logic I/O operation on every power up

without further intervention. The demonstration board may be

used as required.

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Change Logic I/O Level From 5 V to 3.3 V

This procedure applies to an APEK49107 board that is config-

ured for operation in conjunction with 5 V logic systems (i.e.,

VLM = 1) and is to be reconfigured for operation in conjunction

with 3.3 V logic systems (i.e., VLM = 0).

1. Use the reference designations marked on the PCB compo-

nent-side silk screen to conrm the demonstration board is

congured as follows:

□J1, J2, J3, J8, and J9 are fitted.

□J4 is fitted to “VL-U2”.

□J16 is fitted to “5V”.

□J17, J18, J19, are J20 are fitted to “X8”.

□S1/1 through S1/3 are set to “OFF”.

□ S2/1 through S2/6 are set to “OFF”.

All other jumper and switch states are not relevant to this

procedure. However, additional notes about switch states,

resistors, and voltages are provided in the "Additional Notes

and Considerations" section.

2. Connect X8 to a PC USB port with standard USB-A to USB-

Micro-B cable.

3. Connect a DC power supply to X2 (X2/1[VBAT] positive

with respect to X2/2[GND]).

4. Adjust the DC power supply that is to be connected such

that the voltage at the VBB terminal of U1 will comply

with the non-volatile memory (NVM) programming voltage

limit and the VBB functional operating range for the device,

as specified in the product datasheet in effect—between

24 V(minimum) and 50 V(maximum), current limit ≥ 50 mA.

5. Turn on the power supply.

6. Run the AMT49107 GUI on the PC.

7. On the GUI, conrm the SPI Status at the top right of the

main GUI is set to “OK”.

8. Set S1/1, S1/2, S1/3, and S2/1 to “ON”.

9. On the GUI, click on the <Watchdog: Disable> button.

10. Conrm the voltage on the SAL monitor pin is 5.0 V ± 0.5 V.

(i.e., logic I/O is "5V").

11. On the GUI:

A. Click on the <BRIDGE AND SYSTEM> button.

B. On the drop-down list, set the VIO Voltage Monitor

(VLM) to “5 V”; then re-set VLM to “3.3 V”.

C. Close the <BRIDGE AND SYSTEM> window.

D. Click on the <NVM Write: SAVE> button.

12. Set S1/1, S1/2, S1/3, and S2/1 to “OFF”.

13. Turn o the power supply.

14. Shut down the GUI.

15. Wait for at least 10 seconds.

16. Move J16 from “5V” to “3V3”.

17. Turn on the power supply.

18. Run the AMT49107 GUI on the PC.

19. On the GUI, conrm the SPI Status at the top right of the

main GUI is set to “OK”.

20. Set S1/1, S1/2, S1/3, and S2/1 to “ON”.

21. On the GUI, click on the <Watchdog: Disable> button.

22. Measure the voltage on the SAL monitor pin and conrm it is

3.3 V ± 0.5 V (i.e., logic I/O is "3V3").

23. Set S1/1, S1/2, S1/3, and S2/1 to “OFF”.

24. Turn o the power supply.

25. Shut down the GUI.

If the SAL voltage measured at Step 22 is 3.3 V ± 0.5 V, the board

is now configured for 3.3 V logic I/O operation on every power

up without further intervention. The demonstration board may be

used as required.

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

On-Board Linear Regulator

Linear regulator (U2) is a fixed-value, 5 V (nominal) output

device. If any of the switches on S1 or S2 are closed, a 5 V

(nominal) logic high is applied to the corresponding AMT49107

discrete control input:

• In the 5 V logic I/O configuration (VLM = 1), the applied

logic high voltage is directly compatible with the discrete

logic input high threshold of the AMT49107.

• In the 3.3 V logic I/O configuration (VLM = 0), the applied

logic high voltage is compatible with the discrete logic

input high threshold of the AMT49107, though the applied

voltage exceeds the set logic I/O voltage for the part. This is

acceptable because all logic inputs are 5 V logic level tolerant,

regardless of the AMT49107 logic I/O voltage setting (5 V or

3.3 V).

ADDITIONAL NOTES AND CONSIDERATIONS

If setting the AMT49107 for 3.3 V logic I/O operation and then

connecting an external logic driver to any of the RESETn, POK,

ENABLE, Hx, or Lx pins on connector X5, ensure that the 5 V

generated by LDO U2 does not propagate to the externally con-

nected logic driver:

• Set all switches on S1 and S2 corresponding to the driven pins

to the "OFF" position; or

• Switch jumper J4 from the U2 position to the X3 position, and

connect a suitable external 3.3 V DC supply to connector X3.

Resistors R27–35 and R43 limit any current flow from U2 or an

external supply connected to X3 back into logic drivers con-

nected to the RESETn, POK, ENABLE, Hx, or Lx pins on con-

nector X5.

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

APPENDIX 1: AMT49107 DEMONSTRATION BOARD SCHEMATICS

DN F

R10

DN F

R11

DN F

R12

X2.1

X2.2

VBAT

GND

STRn

SCK

SDI

DIAG

- +

E-202

CRD1

LED1

VB AT

1000u

63V

+C10

1000u

63V

+C11

100n

63V

C12

100n

63V

C13

X3.1

X3.2

X5.25

X5.2

X5.3

X5.4

X5.6

X5.7

X5.18

X5.20

X5.24

X5.14

DIAG

SDI

SCK

STRn

SCL

100n

63V

C14

10u

25V

+C15

87654321

BC807

27kR44

27k

R45

1k6

R46

LED2

DIAG

J10 J6

100n

63V

C16

VCP

SDO

X5.16

SDO

ENABLE

X5.8

ENABLE

X5.1

X5.5

RESETn

VLH

GND

SDI

SDO

SCK

SDO_ext

SDI_ext

SCK_ext

STRn_ext

"DNF"

font = Text to be visible on PCB silkscreen.

(italics) = "Do No Fit" (component not fitted).Note:

Bold

Note:

X5.26

GND

Note: "TBC" = component value "To Be Confirmed".

VLH

X5.22

VLH

VBB



X5.23

GND

IRFR2405 M1 M3 M5

M2 M4 M6

33R

X1.2

X1.1

X4.2

X4.1

X6.2

X6.1

100kR13

100k

R15

100k

R17

100k

R14

100k

R16

100k

R18

10u

25V

220n

25V

220n

25V

220n

25V

R34

R35

R36

R37

R38

R29

R30

R31

R32

R33

R39

R40

R43

X5.13

GND

1N4148W

DIAG

SDO

SDI

SCK

STRn

VCP 12

ENABLE

RESETn

CP5 10

CP4 4

CP3 5

VBB 9

CP2 6

CP1 7

VREG3

VBRG8

GND

SA 48

GHA 1

LSSA 45

SB 43

GHB 44

CA 47

GLA 46

CB 42

GLB 41

LSSB 40

SC 38

CC 37

GHC 39

GLC 36

33 NC

LSSC 35

SCL

31 NC

POK

SAL

SBL

CP6 11

TAB

AMT49107EV

SAN

SAP

DN F

X5.11

X5.12

R53

R54

R55

SAL

SBL

1234

RST n

POK

X5.9

X5.10 1kR28

R27

POK

RESETn

GND

INOUT

LM2936HV-5.0

10u

25V

+C5

100n

50V

C4 J2

VBRG

25V

2.2u

C19

25V

2.2u

C20

25V

2.2u

C21

25V

2.2u

C22

SAL

SCL

SBL

GND1 GND2 GND3 GND4

Note: "TC" = "Track Cut" (option to cut shorting track at this point).

TC3

TC2

TC1

SBP

SBN SCN

SCP

STRn

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

TXD 1

DTR# 2

RTS# 3

VCCIO

RXD 5

RI# 6

GND1

NC1

8DSR# 9

DCD# 10

CTS# 11

CBUS4 12

CBUS2 13

CBUS3 14

USBDP

15 USBDM

3V3OUT

GND2

RESET#

VCC

GND3

CBUS1 22

CBUS0 23

NC2

AGND

TEST

OSCI

OSCO

FT232RL

SCK

SDI

SDO

STRn

Port Protect

VCC1

GND1

4GND2 5

B2 6

B1 7

VCC2 8

USB6B1

GND

100n

10V

C23

GND

3V3

J16

USB-Micro-B

SHD 6

GND 5

ID (NC) 4

D+ 3

D- 2

+V 1

47p

10V

C24

47p

10V

C25

GND GND

4.7u

16V

C26

100n

16V

C27

10n

16V

C28

GND GND GND



J17



J18



J19



J20

STRn_ext

(On-Board FT232RL)

3V3

SDO_ext

SDI_ext

SCK_ext

GND

SPI over USB:-

If desired, an SPI cable (3V3or5V) can be used instead of the

Micro-B-USB connector X8 and on-board FT232RL device (U3).

Move links on J17-J20, then connect the cable 6 pin socket to X5

header pins 16, 18, 20,22, 24, and 25 as shown.

X5 pinout:- (IDC26) (top view)

25 GND

STRn

VLH

SCK

SDI

SDO

ENDIAG

GND

RSTn

SAL

POK

GND

SBL

SCL

SPI Cable

Black

Brown

Red

Orange

Yellow

Green

(External Header)X5

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit

improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor

for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

Revision History

Number Date Description

– June 2, 2022 Initial release

Allegro APEK49107 User guide

Allegro APEK49107 User guide

Allegro APEK49107 User guide

Related papers

Other documents