Motorola ColdFire MCF5281 User manual

MCF5282UM/D

Rev. 2

1/2004

MCF5282 ColdFire

®

Microcontroller User’s Manual

Devices Supported:

MCF5281

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Overview

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Cache

Static RAM (SRAM)

ColdFire Flash Module (CFM)

Power Management

System Control Module (SCM)

Clock Module

Interrupt Controller Modules

Edge Port Module (EPORT)

Chip Select Module

External Interface Module (EIM)

Synchronous DRAM Controller Module

DMA Controller Module

Fast Ethernet Controller (FEC)

Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules

General Purpose Timer (GPT) Modules

FlexCAN Module

General Purpose I/O Module

I

2

C Module

3

4

5

7

8

9

10

11

12

13

15

16

17

18

19

24

6

20

25

26

21

23

22

DMA Timers

Queued Serial Peripheral Interface Module (QSPI)

UART Modules

1

2

27

28

29

30

31

32

33

A

Chip Configuration Module (CCM)

Queued Analog-to-Digital Converter (QADC)

Reset Controller Module

Debug Support

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

IND

Index

Signal Descriptions

14

Overview

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Cache

Static RAM (SRAM)

ColdFire Flash Module (CFM)

Power Management

System Control Module (SCM)

Clock Module

Interrupt Controller Modules

Edge Port Module (EPORT)

Chip Select Module

External Interface Module (EIM)

Signal Descriptions

Synchronous DRAM Controller Module

DMA Controller Module

Fast Ethernet Controller (FEC)

Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules

General Purpose Timer (GPT) Modules

FlexCAN Module

General Purpose I/O Module

I

2

C Module

3

4

5

7

8

9

10

11

12

13

14

15

16

17

18

19

24

6

20

25

26

21

23

22

DMA Timers

Queued Serial Peripheral Interface Module (QSPI)

UART Modules

1

2

27

28

29

30

31

32

33

A

Chip Configuration Module (CCM)

Queued Analog-to-Digital Converter (QADC)

Reset Controller Module

Debug Support

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

IND

Index

CONTENTS

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MOTOROLA Contents v

Chapter 1

Overview

1.1 MCF5282 Key Features...................................................................................... 1-1

1.1.1 Version 2 ColdFire Core................................................................................. 1-8

1.1.2 System Control Module................................................................................ 1-10

1.1.3 External Interface Module (EIM) ................................................................. 1-10

1.1.4 Chip Select.................................................................................................... 1-11

1.1.5 Power Management ...................................................................................... 1-11

1.1.6 General Input/Output Ports........................................................................... 1-11

1.1.7 Interrupt Controllers (INTC0/INTC1).......................................................... 1-11

1.1.8 SDRAM Controller....................................................................................... 1-11

1.1.9 Test Access Port............................................................................................ 1-12

1.1.10 UART Modules............................................................................................. 1-12

1.1.11 DMA Timers (DTIM0-DTIM3) ................................................................... 1-13

1.1.12 General-Purpose Timers (GPTA/GPTB)...................................................... 1-13

1.1.13 Periodic Interrupt Timers (PIT0-PIT3)......................................................... 1-13

1.1.14 Software Watchdog Timer............................................................................ 1-14

1.1.15 Phase Locked Loop (PLL)............................................................................ 1-14

1.1.16 DMA Controller............................................................................................ 1-14

1.1.17 Reset.............................................................................................................. 1-14

1.2 MCF5282-Specific Features ............................................................................. 1-15

1.2.1 Fast Ethernet Controller (FEC)..................................................................... 1-15

1.2.2 FlexCAN....................................................................................................... 1-15

1.2.3 I

2

C Bus.......................................................................................................... 1-15

1.2.4 Queued Serial Peripheral Interface (QSPI)................................................... 1-15

1.2.5 Queued Analog-to-Digital Converter (QADC) ............................................ 1-15

Chapter 2

ColdFire Core

2.1 Processor Pipelines ............................................................................................. 2-1

2.2 Processor Register Description........................................................................... 2-2

2.2.1 User Programming Model .............................................................................. 2-2

2.2.2 EMAC Programming Model ......................................................................... 2-5

2.2.3 Supervisor Programming Model..................................................................... 2-5

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2.3 Programming Model ........................................................................................... 2-8

2.4 Additions to the Instruction Set Architecture ..................................................... 2-9

2.5 Exception Processing Overview ....................................................................... 2-10

2.6 Exception Stack Frame Definition.................................................................... 2-12

2.7 Processor Exceptions ........................................................................................ 2-13

2.7.1 Access Error Exception ................................................................................ 2-13

2.7.2 Address Error Exception............................................................................... 2-14

2.7.3 Illegal Instruction Exception......................................................................... 2-14

2.7.4 Divide-By-Zero............................................................................................. 2-14

2.7.5 Privilege Violation........................................................................................ 2-14

2.7.6 Trace Exception ............................................................................................ 2-14

2.7.7 Unimplemented Line-A Opcode................................................................... 2-15

2.7.8 Unimplemented Line-F Opcode ................................................................... 2-15

2.7.9 Debug Interrupt............................................................................................. 2-15

2.7.10 RTE and Format Error Exception................................................................. 2-16

2.7.11 TRAP Instruction Exception......................................................................... 2-16

2.7.12 Interrupt Exception ....................................................................................... 2-16

2.7.13 Fault-on-Fault Halt ....................................................................................... 2-16

2.7.14 Reset Exception ............................................................................................ 2-16

2.8 Instruction Execution Timing ........................................................................... 2-21

2.8.1 Timing Assumptions..................................................................................... 2-21

2.8.2 MOVE Instruction Execution Times ............................................................ 2-22

2.9 Standard One Operand Instruction Execution Times ....................................... 2-24

2.10 Standard Two Operand Instruction Execution Times....................................... 2-24

2.11 Miscellaneous Instruction Execution Times..................................................... 2-26

2.12 EMAC Instruction Execution Times ................................................................ 2-27

2.13 Branch Instruction Execution Times ................................................................ 2-28

2.14 ColdFire Instruction Set Architecture Enhancements ...................................... 2-28

Chapter 3

Enhanced Multiply-Accumulate Unit (EMAC)

3.1 Multiply-Accumulate Unit.................................................................................. 3-1

3.2 Introduction to the MAC..................................................................................... 3-2

3.3 General Operation............................................................................................... 3-3

3.4 Memory Map/Register Set.................................................................................. 3-6

3.4.1 MAC Status Register (MACSR) .................................................................... 3-6

3.4.2 Mask Register (MASK)................................................................................ 3-11

3.5 EMAC Instruction Set Summary...................................................................... 3-12

3.5.1 EMAC Instruction Execution Times ............................................................ 3-12

3.5.2 Data Representation...................................................................................... 3-13

3.5.3 MAC Opcodes .............................................................................................. 3-14

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Chapter 4

Cache

4.1 Cache Features.................................................................................................... 4-1

4.2 Cache Physical Organization .............................................................................. 4-1

4.3 Cache Operation ................................................................................................. 4-3

4.3.1 Interaction with Other Modules...................................................................... 4-3

4.3.2 Memory Reference Attributes ........................................................................ 4-4

4.3.3 Cache Coherency and Invalidation................................................................. 4-4

4.3.4 Reset................................................................................................................ 4-5

4.3.5 Cache Miss Fetch Algorithm/Line Fills ......................................................... 4-5

4.4 Cache Programming Model ................................................................................ 4-7

4.4.1 Cache Registers Memory Map ....................................................................... 4-7

4.4.2 Cache Registers............................................................................................... 4-7

Chapter 5

Static RAM (SRAM)

5.1 SRAM Features................................................................................................... 5-1

5.2 SRAM Operation ................................................................................................ 5-1

5.3 SRAM Programming Model............................................................................... 5-1

5.3.1 SRAM Base Address Register (RAMBAR)................................................... 5-2

5.3.2 SRAM Initialization........................................................................................ 5-3

5.3.3 SRAM Initialization Code .............................................................................. 5-4

5.3.4 Power Management ........................................................................................ 5-4

Chapter 6

ColdFire Flash Module (CFM)

6.1 Features............................................................................................................... 6-1

6.2 Block Diagram.................................................................................................... 6-2

6.3 Memory Map ...................................................................................................... 6-4

6.3.1 CFM Configuration Field ............................................................................... 6-5

6.3.2 Flash Base Address Register (FLASHBAR).................................................. 6-5

6.3.3 CFM Registers ................................................................................................ 6-8

6.3.4 Register Descriptions...................................................................................... 6-9

6.4 CFM Operation ................................................................................................. 6-17

6.4.1 Read Operations............................................................................................ 6-17

6.4.2 Write Operations........................................................................................... 6-17

6.4.3 Program and Erase Operations ..................................................................... 6-17

6.4.4 Stop Mode..................................................................................................... 6-22

6.4.5 Master Mode................................................................................................. 6-23

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6.5 Flash Security Operation .................................................................................. 6-23

6.5.1 Back Door Access......................................................................................... 6-24

6.5.2 Erase Verify Check....................................................................................... 6-24

6.6 Reset.................................................................................................................. 6-24

6.7 Interrupts........................................................................................................... 6-25

Chapter 7

Power Management

7.1 Features............................................................................................................... 7-1

7.2 Memory Map and Registers................................................................................ 7-1

7.2.1 Programming Model....................................................................................... 7-1

7.2.2 Memory Map .................................................................................................. 7-2

7.2.3 Register Descriptions...................................................................................... 7-2

7.3 Functional Description........................................................................................ 7-5

7.3.1 Low-Power Modes.......................................................................................... 7-5

7.3.2 Peripheral Behavior in Low-Power Modes .................................................... 7-7

7.3.3 Summary of Peripheral State During Low-Power Modes............................ 7-16

Chapter 8

System Control Module (SCM)

8.1 Overview............................................................................................................. 8-1

8.2 Features............................................................................................................... 8-1

8.3 Memory Map and Register Definition................................................................ 8-2

8.4 Register Descriptions.......................................................................................... 8-3

8.4.1 Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3

8.4.2 Memory Base Address Register (RAMBAR) ................................................ 8-4

8.4.3 Core Reset Status Register (CRSR)................................................................ 8-6

8.4.4 Core Watchdog Control Register (CWCR) .................................................... 8-6

8.4.5 Core Watchdog Service Register (CWSR)..................................................... 8-9

8.5 Internal Bus Arbitration ...................................................................................... 8-9

8.5.1 Overview....................................................................................................... 8-11

8.5.2 Arbitration Algorithms ................................................................................. 8-11

8.5.3 Bus Master Park Register (MPARK)............................................................ 8-12

8.6 System Access Control Unit (SACU)............................................................... 8-14

8.6.1 Overview....................................................................................................... 8-14

8.6.2 Features......................................................................................................... 8-14

8.6.3 Memory Map/Register Definition ................................................................ 8-15

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Chapter 9

Clock Module

9.1 Features............................................................................................................... 9-1

9.2 Modes of Operation ............................................................................................ 9-1

9.2.1 Normal PLL Mode.......................................................................................... 9-1

9.2.2 1:1 PLL Mode................................................................................................. 9-2

9.2.3 External Clock Mode...................................................................................... 9-2

9.3 Low-power Mode Operation .............................................................................. 9-2

9.4 Block Diagram.................................................................................................... 9-3

9.5 Signal Descriptions ............................................................................................. 9-4

9.5.1 EXTAL ........................................................................................................... 9-4

9.5.2 XTAL.............................................................................................................. 9-5

9.5.3 CLKOUT ........................................................................................................ 9-5

9.5.4 CLKMOD[1:0] ............................................................................................... 9-5

9.5.5 RSTOUT......................................................................................................... 9-5

9.6 Memory Map and Registers................................................................................ 9-5

9.6.1 Module Memory Map..................................................................................... 9-5

9.6.2 Register Descriptions...................................................................................... 9-6

9.7 Functional Description...................................................................................... 9-10

9.7.1 System Clock Modes .................................................................................... 9-10

9.7.2 Clock Operation During Reset...................................................................... 9-11

9.7.3 System Clock Generation ............................................................................. 9-11

9.7.4 PLL Operation .............................................................................................. 9-12

Chapter 10

Interrupt Controller Modules

10.1 68K/ColdFire Interrupt Architecture Overview ............................................... 10-1

10.1.1 Interrupt Controller Theory of Operation ..................................................... 10-3

10.2 Memory Map .................................................................................................... 10-5

10.3 Register Descriptions........................................................................................ 10-6

10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)............................................... 10-6

10.3.2 Interrupt Mask Register (IMRHn, IMRLn) .................................................. 10-8

10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)................................... 10-9

10.3.4 Interrupt Request Level Register (IRLRn) ................................................. 10-10

10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) ............ 10-11

10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).................................. 10-11

10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15

10.4 Prioritization Between Interrupt Controllers .................................................. 10-16

10.5 Low-Power Wakeup Operation ...................................................................... 10-17

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Chapter 11

Edge Port Module (EPORT)

11.1 Introduction....................................................................................................... 11-1

11.2 Low-Power Mode Operation ............................................................................ 11-1

11.3 Interrupt/General-Purpose I/O Pin Descriptions............................................... 11-2

11.4 Memory Map and Registers.............................................................................. 11-3

11.4.1 Memory Map ................................................................................................ 11-3

11.4.2 Registers........................................................................................................ 11-3

Chapter 12

Chip Select Module

12.1 Overview........................................................................................................... 12-1

12.2 Chip Select Module Signals.............................................................................. 12-1

12.3 Chip Select Operation....................................................................................... 12-3

12.3.1 General Chip Select Operation ..................................................................... 12-3

12.4 Chip Select Registers ........................................................................................ 12-5

12.4.1 Chip Select Module Registers....................................................................... 12-6

Chapter 13

External Interface Module (EIM)

13.1 Features............................................................................................................. 13-1

13.2 Bus and Control Signals ................................................................................... 13-1

13.3 Bus Characteristics ........................................................................................... 13-2

13.4 Data Transfer Operation ................................................................................... 13-2

13.4.1 Bus Cycle Execution..................................................................................... 13-3

13.4.2 Data Transfer Cycle States ........................................................................... 13-5

13.4.3 Read Cycle.................................................................................................... 13-6

13.4.4 Write Cycle................................................................................................... 13-8

13.4.5 Fast Termination Cycles ............................................................................... 13-9

13.4.6 Back-to-Back Bus Cycles ........................................................................... 13-10

13.4.7 Burst Cycles................................................................................................ 13-10

13.5 Misaligned Operands ...................................................................................... 13-14

Chapter 14

Signal Descriptions

14.1 Overview........................................................................................................... 14-1

14.1.1 Single-Chip Mode....................................................................................... 14-17

14.1.2 External Boot Mode.................................................................................... 14-17

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14.2 MCF5282 External Signals............................................................................. 14-18

14.2.1 External Interface Module (EIM) Signals .................................................. 14-18

14.2.2 SDRAM Controller Signals........................................................................ 14-21

14.2.3 Clock and Reset Signals ............................................................................. 14-22

14.2.4 Chip Configuration Signals ........................................................................ 14-22

14.2.5 External Interrupt Signals ........................................................................... 14-23

14.2.6 Ethernet Module Signals............................................................................. 14-23

14.2.7 Queued Serial Peripheral Interface (QSPI) Signals.................................... 14-25

14.2.8 FlexCAN Signals ........................................................................................ 14-26

14.2.9 I

2

C Signals .................................................................................................. 14-26

14.2.10 UART Module Signals ............................................................................... 14-26

14.2.11 General Purpose Timer Signals .................................................................. 14-27

14.2.12 DMA Timer Signals.................................................................................... 14-28

14.2.13 Analog-to-Digital Converter Signals.......................................................... 14-29

14.2.14 Debug Support Signals ............................................................................... 14-30

14.2.15 Test Signals................................................................................................. 14-32

14.2.16 Power and Reference Signals ..................................................................... 14-33

Chapter 15

Synchronous DRAM Controller Module

15.1 Overview........................................................................................................... 15-1

15.1.1 Definitions .................................................................................................... 15-1

15.1.2 Block Diagram and Major Components ....................................................... 15-2

15.2 SDRAM Controller Operation.......................................................................... 15-3

15.2.1 DRAM Controller Signals ............................................................................ 15-4

15.2.2 Memory Map for SDRAMC Registers......................................................... 15-4

15.2.3 General Synchronous Operation Guidelines................................................. 15-9

15.2.4 Initialization Sequence................................................................................ 15-17

15.3 SDRAM Example ........................................................................................... 15-19

15.3.1 SDRAM Interface Configuration................................................................ 15-20

15.3.2 DCR Initialization....................................................................................... 15-20

15.3.3 DACR Initialization.................................................................................... 15-21

15.3.4 DMR Initialization...................................................................................... 15-22

15.3.5 Mode Register Initialization ....................................................................... 15-23

15.3.6 Initialization Code....................................................................................... 15-24

Chapter 16

DMA Controller Module

16.1 Overview........................................................................................................... 16-1

16.1.1 DMA Module Features ................................................................................. 16-2

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16.2 DMA Request Control (DMAREQC) .............................................................. 16-3

16.3 DMA Transfer Overview.................................................................................. 16-4

16.4 DMA Controller Module Programming Model................................................ 16-5

16.4.1 Source Address Registers (SAR0–SAR3) .................................................... 16-6

16.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 16-6

16.4.3 Byte Count Registers (BCR0–BCR3) .......................................................... 16-7

16.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 16-8

16.4.5 DMA Status Registers (DSR0–DSR3) ....................................................... 16-10

16.5 DMA Controller Module Functional Description .......................................... 16-11

16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)........................... 16-11

16.5.2 Data Transfer Modes .................................................................................. 16-12

16.5.3 Channel Initialization and Startup .............................................................. 16-13

16.5.4 Data Transfer .............................................................................................. 16-14

16.5.5 Termination................................................................................................. 16-15

Chapter 17

Fast Ethernet Controller (FEC)

17.1 Overview........................................................................................................... 17-1

17.1.1 Features......................................................................................................... 17-1

17.2 Modes of Operation .......................................................................................... 17-2

17.2.1 Full and Half Duplex Operation ................................................................... 17-2

17.2.2 Interface Options........................................................................................... 17-2

17.2.3 Address Recognition Options ....................................................................... 17-3

17.2.4 Internal Loopback......................................................................................... 17-3

17.3 FEC Top-Level Functional Diagram ................................................................ 17-4

17.4 Functional Description...................................................................................... 17-5

17.4.1 Initialization Sequence.................................................................................. 17-6

17.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN]).......................... 17-6

17.4.3 Microcontroller Initialization........................................................................ 17-7

17.4.4 User Initialization (After Asserting ECR[ETHER_EN]) ............................. 17-7

17.4.5 Network Interface Options............................................................................ 17-8

17.4.6 FEC Frame Transmission ............................................................................. 17-9

17.4.7 FEC Frame Reception................................................................................. 17-10

17.4.8 Ethernet Address Recognition .................................................................... 17-11

17.4.9 Hash Algorithm........................................................................................... 17-13

17.4.10 Full Duplex Flow Control........................................................................... 17-16

17.4.11 Inter-Packet Gap (IPG) Time...................................................................... 17-17

17.4.12 Collision Handling...................................................................................... 17-17

17.4.13 Internal and External Loopback.................................................................. 17-17

17.4.14 Ethernet Error-Handling Procedure............................................................ 17-18

17.5 Programming Model ....................................................................................... 17-20

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17.5.1 Top Level Module Memory Map ............................................................... 17-20

17.5.2 Detailed Memory Map (Control/Status Registers) ..................................... 17-20

17.5.3 MIB Block Counters Memory Map............................................................ 17-21

17.5.4 Registers...................................................................................................... 17-23

17.6 Buffer Descriptors........................................................................................... 17-45

17.6.1 Driver/DMA Operation with Buffer Descriptors........................................ 17-45

17.6.2 Ethernet Receive Buffer Descriptor (RxBD).............................................. 17-47

17.6.3 Ethernet Transmit Buffer Descriptor (TxBD) ............................................ 17-49

Chapter 18

Watchdog Timer Module

18.1 Introduction....................................................................................................... 18-1

18.2 Low-Power Mode Operation ............................................................................ 18-1

18.3 Block Diagram.................................................................................................. 18-2

18.4 Signals............................................................................................................... 18-2

18.5 Memory Map and Registers.............................................................................. 18-2

18.5.1 Memory Map ................................................................................................ 18-2

18.5.2 Registers........................................................................................................ 18-3

Chapter 19

Programmable Interrupt Timer Modules (PIT0–PIT3)

19.1 Overview........................................................................................................... 19-1

19.2 Block Diagram.................................................................................................. 19-1

19.3 Low-Power Mode Operation ............................................................................ 19-2

19.4 Signals............................................................................................................... 19-2

19.5 Memory Map and Registers.............................................................................. 19-3

19.5.1 Memory Map ................................................................................................ 19-3

19.5.2 Registers........................................................................................................ 19-3

19.6 Functional Description...................................................................................... 19-6

19.6.1 Set-and-Forget Timer Operation................................................................... 19-6

19.6.2 Free-Running Timer Operation .................................................................... 19-7

19.6.3 Timeout Specifications ................................................................................. 19-7

19.7 Interrupt Operation ........................................................................................... 19-8

Chapter 20

General Purpose Timer Modules

(GPTA and GPTB)

20.1 Features............................................................................................................. 20-1

20.2 Block Diagram.................................................................................................. 20-2

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20.3 Low-Power Mode Operation ............................................................................ 20-3

20.4 Signal Description............................................................................................. 20-3

20.4.1 GPTn[2:0] ..................................................................................................... 20-3

20.4.2 GPTn3........................................................................................................... 20-4

20.4.3 SYNCn.......................................................................................................... 20-4

20.5 Memory Map and Registers.............................................................................. 20-4

20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ................. 20-5

20.5.2 GPT Compare Force Register (GPCFORC)................................................. 20-6

20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).................................. 20-6

20.5.4 GPT Output Compare 3 Data Register (GPTOC3D).................................... 20-7

20.5.5 GPT Counter Register (GPTCNT) ............................................................... 20-7

20.5.6 GPT System Control Register 1 (GPTSCR1)............................................... 20-8

20.5.7 GPT Toggle-On-Overflow Register (GPTTOV).......................................... 20-9

20.5.8 GPT Control Register 1 (GPTCTL1)............................................................ 20-9

20.5.9 GPT Control Register 2 (GPTCTL2).......................................................... 20-10

20.5.10 GPT Interrupt Enable Register (GPTIE) .................................................... 20-10

20.5.11 GPT System Control Register 2 (GPTSCR2)............................................. 20-11

20.5.12 GPT Flag Register 1 (GPTFLG1)............................................................... 20-12

20.5.13 GPT Flag Register 2 (GPTFLG2)............................................................... 20-12

20.5.14 GPT Channel Registers (GPTCn)............................................................... 20-13

20.5.15 Pulse Accumulator Control Register (GPTPACTL) .................................. 20-13

20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)........................................ 20-14

20.5.17 Pulse Accumulator Counter Register (GPTPACNT) ................................. 20-15

20.5.18 GPT Port Data Register (GPTPORT)......................................................... 20-16

20.5.19 GPT Port Data Direction Register (GPTDDR)........................................... 20-16

20.6 Functional Description.................................................................................... 20-17

20.6.1 Prescaler...................................................................................................... 20-17

20.6.2 Input Capture .............................................................................................. 20-17

20.6.3 Output Compare.......................................................................................... 20-17

20.6.4 Pulse Accumulator...................................................................................... 20-18

20.6.5 Event Counter Mode................................................................................... 20-18

20.6.6 Gated Time Accumulation Mode ............................................................... 20-19

20.6.7 General-Purpose I/O Ports.......................................................................... 20-19

20.7 Reset................................................................................................................ 20-21

20.8 Interrupts......................................................................................................... 20-21

20.8.1 GPT Channel Interrupts (CnF) ................................................................... 20-22

20.8.2 Pulse Accumulator Overflow (PAOVF)..................................................... 20-22

20.8.3 Pulse Accumulator Input (PAIF) ................................................................ 20-22

20.8.4 Timer Overflow (TOF) ............................................................................... 20-22

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Chapter 21

DMA Timers (DTIM0–DTIM3)

21.1 Overview........................................................................................................... 21-1

21.1.1 Key Features ................................................................................................. 21-2

21.2 DMA Timer Programming Model.................................................................... 21-2

21.2.1 Prescaler........................................................................................................ 21-2

21.2.2 Capture Mode ............................................................................................... 21-3

21.2.3 Reference Compare....................................................................................... 21-3

21.2.4 Output Mode................................................................................................. 21-3

21.2.5 Memory Map ................................................................................................ 21-3

21.2.6 DMA Timer Mode Registers (DTMRn)....................................................... 21-4

21.2.7 DMA Timer Extended Mode Registers (DTXMRn).................................... 21-5

21.2.8 DMA Timer Event Registers (DTERn)........................................................ 21-6

21.2.9 DMA Timer Reference Registers (DTRRn)................................................. 21-7

21.2.10 DMA Timer Capture Registers (DTCRn) .................................................... 21-7

21.2.11 DMA Timer Counters (DTCNn) .................................................................. 21-8

21.3 Using the DMA Timer Modules....................................................................... 21-8

21.3.1 Code Example............................................................................................... 21-9

21.3.2 Calculating Time-Out Values ..................................................................... 21-10

Chapter 22

Queued Serial Peripheral Interface

(QSPI) Module

22.1 Overview........................................................................................................... 22-1

22.2 Features............................................................................................................. 22-1

22.3 Module Description .......................................................................................... 22-1

22.3.1 Interface and Signals..................................................................................... 22-2

22.3.2 Internal Bus Interface.................................................................................... 22-3

22.4 Operation .......................................................................................................... 22-3

22.4.1 QSPI RAM.................................................................................................... 22-4

22.4.2 Baud Rate Selection...................................................................................... 22-6

22.4.3 Transfer Delays............................................................................................. 22-7

22.4.4 Transfer Length............................................................................................. 22-8

22.4.5 Data Transfer ................................................................................................ 22-8

22.5 Programming Model ......................................................................................... 22-9

22.5.1 QSPI Mode Register (QMR) ...................................................................... 22-10

22.5.2 QSPI Delay Register (QDLYR) ................................................................. 22-11

22.5.3 QSPI Wrap Register (QWR)....................................................................... 22-12

22.5.4 QSPI Interrupt Register (QIR).................................................................... 22-13

22.5.5 QSPI Address Register (QAR) ................................................................... 22-14

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22.5.6 QSPI Data Register (QDR)......................................................................... 22-14

22.5.7 Command RAM Registers (QCR0–QCR15).............................................. 22-15

22.5.8 Programming Example ............................................................................... 22-16

Chapter 23

UART Modules

23.1 Overview........................................................................................................... 23-1

23.2 Serial Module Overview................................................................................... 23-2

23.3 Register Descriptions........................................................................................ 23-3

23.3.1 UART Mode Registers 1 (UMR1n).............................................................. 23-4

23.3.2 UART Mode Register 2 (UMR2n) ............................................................... 23-6

23.3.3 UART Status Registers (USRn) ................................................................... 23-7

23.3.4 UART Clock Select Registers (UCSRn) ...................................................... 23-8

23.3.5 UART Command Registers (UCRn) ............................................................ 23-9

23.3.6 UART Receive Buffers (URBn)................................................................. 23-11

23.3.7 UART Transmit Buffers (UTBn) ............................................................... 23-11

23.3.8 UART Input Port Change Registers (UIPCRn).......................................... 23-12

23.3.9 UART Auxiliary Control Register (UACRn)............................................. 23-13

23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 23-13

23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) ......................... 23-14

23.3.12 UART Input Port Register (UIPn).............................................................. 23-15

23.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 23-15

23.4 UART Module Signal Definitions.................................................................. 23-17

23.5 Operation ........................................................................................................ 23-18

23.5.1 Transmitter/Receiver Clock Source............................................................ 23-18

23.5.2 Transmitter and Receiver Operating Modes............................................... 23-20

23.5.3 Looping Modes........................................................................................... 23-25

23.5.4 Multidrop Mode.......................................................................................... 23-26

23.5.5 Bus Operation ............................................................................................. 23-28

23.5.6 Programming .............................................................................................. 23-28

Chapter 24

I

2

C Interface

24.1 Overview........................................................................................................... 24-1

24.2 Interface Features.............................................................................................. 24-1

24.3 I

2

C System Configuration................................................................................. 24-3

24.4 I

2

C Protocol ...................................................................................................... 24-3

24.4.1 Arbitration Procedure ................................................................................... 24-4

24.4.2 Clock Synchronization.................................................................................. 24-5

24.4.3 Handshaking ................................................................................................. 24-5

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24.4.4 Clock Stretching ........................................................................................... 24-5

24.5 Programming Model ......................................................................................... 24-6

24.5.1 I

2

C Address Register (I2ADR)..................................................................... 24-6

24.5.2 I

2

C Frequency Divider Register (I2FDR)..................................................... 24-7

24.5.3 I

2

C Control Register (I2CR)......................................................................... 24-8

24.5.4 I

2

C Status Register (I2SR)............................................................................ 24-9

24.5.5 I

2

C Data I/O Register (I2DR) ..................................................................... 24-10

24.6 I

2

C Programming Examples ........................................................................... 24-10

24.6.1 Initialization Sequence................................................................................ 24-10

24.6.2 Generation of START................................................................................. 24-11

24.6.3 Post-Transfer Software Response............................................................... 24-11

24.6.4 Generation of STOP.................................................................................... 24-12

24.6.5 Generation of Repeated START................................................................. 24-13

24.6.6 Slave Mode ................................................................................................. 24-13

24.6.7 Arbitration Lost........................................................................................... 24-14

Chapter 25

FlexCAN

25.1 Features............................................................................................................. 25-1

25.1.1 FlexCAN Memory Map................................................................................ 25-3

25.1.2 External Signals ............................................................................................ 25-3

25.2 The CAN System .............................................................................................. 25-4

25.3 Message Buffers ............................................................................................... 25-4

25.3.1 Message Buffer Structure ............................................................................. 25-4

25.3.2 Message Buffer Memory Map...................................................................... 25-7

25.4 Functional Overview......................................................................................... 25-8

25.4.1 Transmit Process........................................................................................... 25-9

25.4.2 Receive Process ............................................................................................ 25-9

25.4.3 Message Buffer Handling ........................................................................... 25-10

25.4.4 Remote Frames ........................................................................................... 25-12

25.4.5 Overload Frames......................................................................................... 25-13

25.4.6 Time Stamp................................................................................................. 25-13

25.4.7 Listen-Only Mode....................................................................................... 25-13

25.4.8 Bit Timing................................................................................................... 25-14

25.4.9 FlexCAN Error Counters............................................................................ 25-15

25.4.10 FlexCAN Initialization Sequence ............................................................... 25-16

25.4.11 Special Operating Modes............................................................................ 25-17

25.4.12 Interrupts..................................................................................................... 25-19

25.5 Programmer’s Model ...................................................................................... 25-20

25.5.1 CAN Module Configuration Register (CANMCR).................................... 25-20

25.5.2 FlexCAN Control Register 0 (CANCTRL0).............................................. 25-22

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25.5.3 FlexCAN Control Register 1 (CANCTRL1).............................................. 25-23

25.5.4 Prescaler Divide Register (PRESDIV) ....................................................... 25-24

25.5.5 FlexCAN Control Register 2 (CANCTRL2).............................................. 25-25

25.5.6 Free Running Timer (TIMER).................................................................... 25-26

25.5.7 Rx Mask Registers...................................................................................... 25-26

25.5.8 FlexCAN Error and Status Register (ESTAT) ........................................... 25-28

25.5.9 Interrupt Mask Register (IMASK).............................................................. 25-30

25.5.10 Interrupt Flag Register (IFLAG)................................................................. 25-31

25.5.11 FlexCAN Receive Error Counter (RXECTR) ............................................ 25-32

25.5.12 FlexCAN Transmit Error Counter (TXECTR)........................................... 25-32

Chapter 26

General Purpose I/O Module

26.1 Introduction....................................................................................................... 26-1

26.1.1 Overview....................................................................................................... 26-3

26.1.2 Features......................................................................................................... 26-3

26.1.3 Modes of Operation ...................................................................................... 26-3

26.2 External Signal Description .............................................................................. 26-4

26.3 Memory Map/Register Definition .................................................................... 26-6

26.3.1 Register Overview ........................................................................................ 26-6

26.3.2 Register Descriptions.................................................................................... 26-8

26.4 Functional Description.................................................................................... 26-25

26.4.1 Overview..................................................................................................... 26-25

26.4.2 Port Digital I/O Timing .............................................................................. 26-25

26.5 Initialization/Application Information............................................................ 26-26

Chapter 27

Queued Analog-to-Digital Converter (QADC)

27.1 Features............................................................................................................. 27-1

27.2 Block Diagram.................................................................................................. 27-2

27.3 Modes of Operation .......................................................................................... 27-3

27.3.1 Debug Mode ................................................................................................. 27-3

27.3.2 Stop Mode..................................................................................................... 27-3

27.4 Signals............................................................................................................... 27-4

27.4.1 Port QA Signal Functions............................................................................. 27-4

27.4.2 Port QB Signal Functions ............................................................................. 27-5

27.4.3 External Trigger Input Signals...................................................................... 27-6

27.4.4 Multiplexed Address Output Signals............................................................ 27-6

27.4.5 Multiplexed Analog Input Signals................................................................ 27-6

27.4.6 Voltage Reference Signals............................................................................ 27-7

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27.4.7 Dedicated Analog Supply Signals ................................................................ 27-7

27.4.8 Dedicated Digital I/O Port Supply Signal..................................................... 27-7

27.5 Memory Map .................................................................................................... 27-7

27.6 Register Descriptions........................................................................................ 27-8

27.6.1 QADC Module Configuration Register (QADCMCR)................................ 27-8

27.6.2 QADC Test Register (QADCTEST) ............................................................ 27-9

27.6.3 Port Data Registers (PORTQA and PORTQB) ............................................ 27-9

27.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)........... 27-10

27.6.5 Control Registers ........................................................................................ 27-11

27.6.6 Status Registers........................................................................................... 27-19

27.6.7 Conversion Command Word Table (CCW) ............................................... 27-26

27.6.8 Result Registers .......................................................................................... 27-29

27.7 Functional Description.................................................................................... 27-31

27.7.1 Result Coherency........................................................................................ 27-31

27.7.2 External Multiplexing ................................................................................. 27-31

27.7.3 Analog Subsystem ...................................................................................... 27-34

27.8 Digital Control Subsystem.............................................................................. 27-37

27.8.1 Queue Priority Timing Examples ............................................................... 27-38

27.8.2 Boundary Conditions .................................................................................. 27-49

27.8.3 Scan Modes................................................................................................. 27-50

27.8.4 Disabled Mode............................................................................................ 27-50

27.8.5 Reserved Mode ........................................................................................... 27-50

27.8.6 Single-Scan Modes ..................................................................................... 27-50

27.8.7 Continuous-Scan Modes............................................................................. 27-54

27.8.8 QADC Clock (QCLK) Generation ............................................................. 27-57

27.8.9 Periodic/Interval Timer............................................................................... 27-58

27.8.10 Conversion Command Word Table ............................................................ 27-59

27.8.11 Result Word Table...................................................................................... 27-62

27.9 Signal Connection Considerations.................................................................. 27-62

27.9.1 Analog Reference Signals........................................................................... 27-63

27.9.2 Analog Power Signals................................................................................. 27-63

27.9.3 Conversion Timing Schemes...................................................................... 27-64

27.9.4 Analog Supply Filtering and Grounding .................................................... 27-67

27.9.5 Accommodating Positive/Negative Stress Conditions ............................... 27-69

27.9.6 Analog Input Considerations ...................................................................... 27-71

27.9.7 Analog Input Pins ....................................................................................... 27-73

27.10 Interrupts......................................................................................................... 27-75

27.10.1 Interrupt Operation ..................................................................................... 27-75

27.10.2 Interrupt Sources......................................................................................... 27-76

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Chapter 28

Reset Controller Module

28.1 Features............................................................................................................. 28-1

28.2 Block Diagram.................................................................................................. 28-2

28.3 Signals............................................................................................................... 28-2

28.3.1 RSTI............................................................................................................. 28-2

28.3.2 RSTO

........................................................................................................... 28-2

28.4 Memory Map and Registers.............................................................................. 28-3

28.4.1 Reset Control Register (RCR) ...................................................................... 28-3

28.4.2 Reset Status Register (RSR) ......................................................................... 28-4

28.5 Functional Description...................................................................................... 28-6

28.5.1 Reset Sources................................................................................................ 28-6

28.5.2 Reset Control Flow ....................................................................................... 28-8

28.5.3 Concurrent Resets....................................................................................... 28-10

Chapter 29

Debug Support

29.1 Overview........................................................................................................... 29-1

29.2 Signal Description............................................................................................. 29-2

29.3 Real-Time Trace Support.................................................................................. 29-3

29.3.1 Begin Execution of Taken Branch (PST = 0x5)........................................... 29-4

29.4 Programming Model ......................................................................................... 29-5

29.4.1 Revision A Shared Debug Resources ........................................................... 29-7

29.4.2 Address Attribute Trigger Register (AATR)................................................ 29-8

29.4.3 Address Breakpoint Registers (ABLR, ABHR) ........................................... 29-9

29.4.4 Configuration/Status Register (CSR) ......................................................... 29-10

29.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)....................................... 29-12

29.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR).................... 29-13

29.4.7 Trigger Definition Register (TDR)............................................................. 29-14

29.5 Background Debug Mode (BDM) .................................................................. 29-16

29.5.1 CPU Halt..................................................................................................... 29-16

29.5.2 BDM Serial Interface.................................................................................. 29-18

29.5.3 BDM Command Set ................................................................................... 29-20

29.6 Real-Time Debug Support .............................................................................. 29-37

29.6.1 Theory of Operation.................................................................................... 29-37

29.6.2 Concurrent BDM and Processor Operation................................................ 29-39

29.7 Processor Status, DDATA Definition............................................................. 29-40

29.7.1 User Instruction Set .................................................................................... 29-40

29.7.2 Supervisor Instruction Set........................................................................... 29-44

29.8 Motorola-Recommended BDM Pinout........................................................... 29-46

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