Singmai Electronics SM08 User manual

Brand
Singmai Electronics
Model
SM08
Type
User manual
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SM08
Advanced Composite Video Interface:
aCVi to HD-SDI converter
module
User Manual
Revision 0.2
23rd July 2016
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Revision History
Date Revisions Version
11-07-2016 First Draft. 0.1
23-07-2016 Added chapter on the test points.
Added comment on the Quartus version.
Added 720p/25Hz-30Hz standards to aCVi
description.
Specifications updated.
0.2
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Contents
Revision History....................................................................................................................................... 2
Contents................................................................................................................................................... 3
Tables ....................................................................................................................................................... 3
Figures...................................................................................................................................................... 3
1. Introduction ...................................................................................................................................5
2. Connecting up the module ............................................................................................................6
3. aCVi Overview ................................................................................................................................8
4. Circuit description........................................................................................................................ 10
5. Re-programming the FPGA ..........................................................................................................21
6. Test Point Monitoring.................................................................................................................. 23
7. Specification................................................................................................................................. 25
Appendix A: PCB Overlay ......................................................................................................................30
Appendix B: Bill of Materials................................................................................................................. 32
Appendix C: AC-DC adaptor .................................................................................................................. 35
Tables
Table 1 Video standard selection. ...........................................................................................................6
Table 2 aCVi supported video formats. ..................................................................................................8
Table 3 PT51 and ADC sample rates. ..................................................................................................... 10
Table 4 SM08 Bill of Materials. .............................................................................................................34
Figures
Figure 1 SM08 module............................................................................................................................. 5
Figure 2 SM08 Component positions. ....................................................................................................6
Figure 3 SM06 Switches (Switches 1-5 shown ON)................................................................................ 7
Figure 4 aCVi Spectrum. ..........................................................................................................................9
Figure 5 SM08 schematics - sheet 1. ......................................................................................................12
Figure 6 SM08 schematics - sheet 2. .....................................................................................................13
Figure 7 SM08 schematics - sheet 3...................................................................................................... 14
Figure 8 SM08 schematics - sheet 4. .....................................................................................................15
Figure 9 SM08 schematics - sheet 5. .................................................................................................... 16
Figure 10 SM08 schematics - sheet 6.....................................................................................................17
Figure 11 SM08 schematics - sheet 7..................................................................................................... 18
Figure 12 SM08 schematics - sheet 8. ................................................................................................... 19
Figure 13 SM08 schematics - sheet 9. ...................................................................................................20
Figure 14 Re-programming the SM08....................................................................................................21
Figure 15 Quartus FPGA programmer................................................................................................... 22
Figure 16 SM08 Test point location. ..................................................................................................... 23
Figure 17 Horizontal sync test output................................................................................................... 23
Figure 18 Vertical sync test output. ......................................................................................................24
Figure 19 NTSC 75% colour bars - waveform. ........................................................................................ 25
Figure 20 NTSC 75% colour bars - vectors. ............................................................................................26
Figure 21 NTSC - SDI status display. ......................................................................................................26
Figure 22 PAL 75% colour bars - waveform. .......................................................................................... 27
Figure 23 PAL 75% colour bars - vectors................................................................................................ 27
Figure 24 PAL 75% colour bars - lightning. ............................................................................................28
Figure 25 PAL - CCIR17 waveform. ........................................................................................................28
Figure 26 PAL - 2T pulse.........................................................................................................................29
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Figure 27 PAL - 5.75MHz frequency sweep. .........................................................................................29
Figure 28 SM08 PCB overlay - top side.................................................................................................30
Figure 29 SM08 PCB overlay - bottom side. ..........................................................................................31
Figure 30 AC-DC adaptor specification- Page 1. ................................................................................... 35
Figure 31 AC-DC adaptor specification- Page 2.....................................................................................36
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1. Introduction
SM08 is a receiver module compatible with the aCVi Advanced Composite Video Interface format,
and also with NTSC/PAL and 960H standards. SM08 accepts analogue aCVi encoded video (and
NTSC/PAL) which it decodes and formats to an HD-SDI (or SDI) output.
aCVi is a method to transmit HD video over long distances of existing coaxial or twisted-pair cable
networks or allow the use of less expensive RG-59/UTP cable in long distance installations.
SM08 can accept either twisted pair or coaxial cable inputs (build option) and supports the
following HD aCVi formats: 720p-25/30/50/59/60Hz, 1080p-24/25/29/30Hz, 1080i-50/59/60Hz as well
as NTSC-M/PAL and NTSC-960H and PAL-960H video standards. Switching between SD and HD
formats is manual, but switching between the various HD aCVi formats and between NTSC/PAL is
automatic.
The module is also compatible with the aCVI bidirectional data interface.
Figure 1 SM08 module.
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2. Connecting up the module
The SM08 module is powered by a universal input (90-260VAC) AC-DC adaptor. The 5VDC output
of this adaptor should be connected to the jack input of the SM08. The specification of the AC-DC
power adaptor can be found in Appendix C.
Once connected, the green LED, ‘Program OK’, should light, indicating the FPGA has been
correctly programmed. See Figure 2.
SM08 can accept either coaxial or twisted pair cable inputs, but this is a build option for the board
and needs to be specified at the time of order.
The analogue CVBS input should be applied to the appropriate connector. The HD-SDI output
should be connected to a compatible monitor or waveform monitor. (Note: some aCVi supported
standards, such as 720p/25Hz and 720p/30Hz, may not be accepted by all HD-SDI receivers.)
Figure 2 SM08 Component positions.
SM08 can accept aCVI, NTSC-M/PAL or NTSC-960H/PAL-960H formats. Switching between these
various formats is manual, using switches as shown in Figure 3 and Table 1.
Switch 2 Switch 1 Format
ON ON aCVI HD
ON OFF NTSC-M/PAL
OFF ON aCVi HD
OFF OFF NTSC-960H/PAL-960H
Table 1 Video standard selection.
Within each group of standards the video standard selection is automatic. For example, if aCVi is
selected, the PT51 decoder will automatically select between 720p-25/30/50/59/60Hz, 1080p-
24/25/29/30Hz and 1080i-50/59/60Hz standards. If the video input is one of the standards within
the selected group and within the range of the horizontal phase locked loop, the ‘Lock’ LED will
light.
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Figure 3 SM06 Switches (Switches 1-5 shown ON).
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3. aCVi Overview
The following is a brief overview of the aCVi interface.
The basic concept of the aCVi interface is to build on the proven and reliable transport method of
NTSC, (the advantages of PAL – v.v. multi-path reception – is not relevant to a cable system so
NTSC is used as the model). NTSC transmissions are capable of transmitting more than 1km across
RG-59 cable but the bandwidth is limited to 5MHz. Because the cable system is a closed system, it
is only necessary for the transmitter and receiver to ‘understand’ each other and we can modify
the basic NTSC method to suit HD transmissions.
According to the SMPTE-296M specification, HD (74.25MHz sampling) video transmission requires
a luma bandwidth of 30MHz and chroma bandwidth of 15MHz. To save on system costs aCVi
supports the 30MHz luma bandwidth but constrains the chroma bandwidth to 7.5MHz (4:1:1
sampling).
The colour difference signals are modulated onto a carrier in quadrature so they effectively use
the same bandwidth: the chroma subcarrier is ~27.8MHz.. The high frequency luma and the
modulated chroma overlap above 18.6MHz but because of the line to line phase relationship of the
chroma, may be separated using a luine comb filter (and also because of the use of single chip
image sensors, there is usually little high frequency content to cause image artifacts).
The effective bandwidth of the complete signal is therefore approximately 9.3MHz (chroma upper
sideband + filter roll off) + 27.8MHz or about 37MHz, setting a minimum sampling frequency of 2 x
37MHz or 74MHz. For convenience we choose 74.25MHz as a sampling frequency as this is related
to the SMPTE272M standard; (see Figure 4).
For transmission over 300m of RG-59 cable we can expect 18dB loss at higher frequencies
(6.2dB/100m @ 50MHz). However the synchronizing signals are at a much lower frequency where
the loss is only about 1-2dB so reliable rastering of the received signal should always be assured.
The peak to peak video level of aCVi is 1.26V (100% colour bars) which maintains compatibility with
any legacy SD equipment on the network and also allows common low-power 3.3V drivers to be
used.
Table 2 lists the currently supported video formats for aCVi.
Format Pixels/line Line frequency FSC/FHratio Subcarrier
720p/25 3960 18.75kHz 1482.5 27.796875MHz
720p/30 3300 22.5kHz 1235.5 27.79875MHz
720p/50Hz 1980 37.500kHz 741.5 27.80625MHz
720p/59.94Hz
1
1650 44.955kHz 618.5 27.804695MHz
720p/60Hz 1650 45.000kHz 617.5 27.7875MHz
1080p/24Hz 2750 27.0kHz 1029.5 27.7965MHz
1080p/25Hz 2640 28.125kHz 988.5 27.8015625MHz
1080p/29.97Hz
1
2200 33.716kHz 824.5 27.7990759MHz
1080p/30Hz 2200 33.750kHz 823.5 27.793125MHz
1080i/50Hz 2640 28.125kHz 988.5 27.8015625MHz
1080i/59.94Hz
1
2200 33.716kHz 824.5 27.7990759MHz
1080i/60Hz 2200 33.750kHz 823.5 27.793125MHz
Table 2 aCVi supported video formats.
1Input clock is 148.3516484MHz (else 148.5MHz).
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Figure 4 aCVi Spectrum.
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4. Circuit description
Figures 5-13 show the schematics for the SM08. The component overlay for the PCB is shown in
Appendix A.
Below is a brief technical description of the SM08 module.
Sheet 1.
J1 is the 5VDC power input connector to the SM08 module. The 5VDC is protected from over-
voltage and reverse polarity inputs by D1, D2 and resettable fuse, F1. The input is then filtered by L1
and C1 to provide the ‘clean’ 5VDC for the analogue input stage and also linear regulated by U1 and
U2 to provide the 3.3VDC and 2.5VDC supply voltages.
Sheet 2.
U3 provides the 1.2VDC for the internal voltage of the FPGA. U4 provides the 2.5VDC for the
analogue PLL circuity of the FPGA and L2 and C26 filter the VCCINT for the FPGA PLL digital blocks.
C4-C30 provides local decoupling for the FPGA.
Sheet 3.
Sheet 3 is the FPGA. The FPGA is an Altera EP4CE15 device in a MBGA 164 pin 0.5mm pitch package.
The FPGA contains the PT51 aCVi/NTSC/PAL decoder, a SingMai PT13 control microprocessor, and
the HD-SDI/SDI formatting.
Sheet 4.
The FPGA is a volatile device and needs programming on switch on, which it does using U6, a 4Mb
EEPROM. The device is automatically configured on switch on, and successful configuration is
indicated by D3 LED (‘Program OK’). The EEPROM may also be reprogrammed via J2, which is
compatible with the Altera ‘USB-Blaster’ and the Quartus Programmer (see Chapter 5).
Sheet 5.
The PT51 decoder requires a line locked clock (see PT51 user manual, chapter 6). To achieve this a
voltage controlled crystal oscillator is used, with the frequency of the oscillator controlled using a
PWM output from the PT51 IP core. This output, VCO_PWM, is filtered by R11 and C32 to provide an
analogue voltage which is buffered by U7. This 0-3.3V control voltage adjusts the frequency of the
crystal voltage controlled oscillator (VCXO), X1. The adjustment range is approximately ±150ppm.
The centre frequency (1.65VDC control voltage) is 27.0MHz. Note, this adjustment range may not
be sufficient for some NTSC/PAL inputs and horizontal phase lock may not be achieved with
these video sources. However a wider range (non-crystal) VCO will not achieve the jitter
specification of the HD-SDI/SDI output.
The output of the VCXO is then multiplied to 74.25MHz or 74.18MHz (to provide support for
29.97/59.94Hz formats) – selection is performed via the FREQ_SEL port. VCO_CLK is the clock
input to the FPGA.
The VCO_CLK input is fed to an FPGA PLL. This PLL is dynamically configured depending on the
selected video standards (aCVi, NTSC/PAL or 960H). The output of the PLL provides 3 clocks as
shown in Table 2.
Clock NTSC/PAL NTSC-960/PAL-960H aCVi
ADC clock 27MHz 36MHz 74.25MHz
1
PT51 Clock 13.5MHz 18MHz 74.25MHz
1
PT51 Clock2x 27MHz 36MHz 148.5MHz
2
Table 3 PT51 and ADC sample rates.
1Clock frequency = 74.17582418MHz for 29.97Hz and 59.94Hz field rate standards.
2Clock frequency = 148.3516484MHz for 29.97Hz and 59.94Hz field rate standards.
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The ‘Lock’ LED, D4, is driven from a port of the FPGA. It is lit when the PT51 status indicates that
horizontal lock has been achieved and the input is a valid standard supported by the PT51.
Five DIP switches provide standard selection for the SM08 (see Chapter 2) and are read by the
FPGA microprocessor.
U8 is a proprietary copy-protection IC. U8 calculates a checksum from a PT13 generated data
stream, and the calculated checksum from U8 is compared with an FPGA internally generated
checksum. If the two do not match the SM08 module is shut down. This means that even if the bit
stream of the FPGA/EEPROM is captured the PT51 IP core will not run without U8 being fitted.
Sheet 6.
Sheet 6 is the analogue front end (AFE). The analogue video inputs, which may be aCVi, NTSC/PAL
or 960H formats, may be either coaxial or twisted pair (build option for the SM08).
If twisted pair, they are terminated in 100Ω (R26) and converted from differential to single ended
outputs by U9 and U10. If coaxial inputs they are treated as a pseudo-differential input, with the
ground screen of the BNC input connector connected to ground via R27 and C37, which affords
some hum rejection for long cable runs.
U13 provides a mid-rail (2.5V) bias voltage with low output impedance as the AFE runs from a
single supply voltage (5V).
U11 is a voltage controlled amplifier. The PT51 decoder provides automatic gain control and the
‘GAIN_CONTROL’ PWM output of the PT51 is used to control the gain of U11. The PWM output is
first clamped to the 2.5V reference voltage to avoid supply variations affecting the gain (D8). R42
and C52 provide low pass filtering of the PWM signal to convert it to an analogue voltage. This is
buffered and amplified by U13 to provide a 0-5V control voltage (although the voltage control
range of U11 is only 2.5V ± 650mV.
The output of U11 is AC coupled into U12A, which is a high input impedance, low input bias current
op-amp. The average DC level of video varies widely and to ensure it can be scaled into the
analogue to digital converter (ADC) properly it must be clamped. The AFE uses a sync tip clamp.
The most negative part of the AC coupled video is clamped to the VCLAMP reference voltage,
which is the most negative voltage reference voltage of the ADC. The ADC requires a 0.5V to 2.5V
(2V pk-pk) input signal and the sync tips (the most negative part of the video signal) are clamped,
using ‘ideal’ diode D7 and U12B, to the 0.5V ADC reference. The black level of the video (back
porch level) is measured and used to restore the video black level by the PT51 decoder.
Sheet 7.
U19 is the ADC, a 10-bit 80MHz component that is clocked at the rate shown in Table 2. The ADC
accepts a differential input, but is used in single-ended mode. The clamped video from U12A is
applied to the VIN+ input, and VIN- input is biased to mid rail (1.5V). U14 provides the ‘clean’ 3.0V
supply for the ADC. The output of the ADC, ADC[9:0] is the straight binary, digital composite video
which is applied directly to the PT51 decoder.
Sheet 8.
The aCVi interface allows bidirectional data to be sent between transmitter and receiver during
dedicated lines of the vertical blanking interval. Data from the transmitter to the receiver is
treated the same as video data, and the ADC ‘data’ line is decoded within the PT51.
Data to be sent from the SM08 to the transmitter is output from the PT51 and FPGA as the
DATA_OUT port. This binary data is converted into a current by U16 and R53 and injected into the
cable input (DATA_INS to AFE input, Sheet 6).
Sheet 9.
The Y, Cb and Cr video and the Hout, Vout and Fout synchronizing signals from the PT51 decoder
are formatted into an HD-SDI/SDI format inside the FPGA. The synchronizing signals are modified
to be compatible with the HD-SDI/SDI Flag requirements and the line count is derived for HD
outputs. The video and the timing signals (TRS) are combined and scrambled according to the HD-
SDI/SDI specifications and cyclic redundancy check (CRC) is added.
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The scrambled signal is then multiplexed into 5 data streams at 148.5MHz/27MHz which are driven
as LVDS outputs, together with an LVDS clock, to the HD-SDI/SDI serialiser IC, U17, which converts
these five data signals into one 1.485GHz/270MHz, HD-SDI/SDI compatible, output (J4).
Components L5 and R61 are used to improve the return loss.
Figure 5 SM08 schematics - sheet 1.
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Figure 6 SM08 schematics - sheet 2.
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Figure 7 SM08 schematics - sheet 3.
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Figure 8 SM08 schematics - sheet 4.
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Figure 9 SM08 schematics - sheet 5.
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Figure 10 SM08 schematics - sheet 6.
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Figure 11 SM08 schematics - sheet 7.
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Figure 12 SM08 schematics - sheet 8.
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Figure 13 SM08 schematics - sheet 9.
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Singmai Electronics SM08 User manual

Brand
Singmai Electronics
Model
SM08
Type
User manual
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