2. Eurotech
  3. CPU-162-23

Eurotech CPU-162-23 Owner's manual

  • Hello! I am an AI chatbot trained to assist you with the Eurotech CPU-162-23 Owner's manual. I’ve already reviewed the document and can help you find the information you need or explain it in simple terms. Just ask your questions, and providing more details will help me assist you more effectively!
CPU
-162-23
COM
Express CPU Module
CARRIER
BOARD DESIGN GUIDE
Rev 1
– 2020-07-17 – B37028A0-MN004-00_UserMan_En_1
© 2019 Advanet
Preface
This document provides information to design a carrier board for CPU-162-23 which is COM Express CPU
Module. Please read this document so that you may obtain the greatest benefit from the device.
Trademarks
All trademarks both marked and unmarked appearing in this document are the property of their respective
owners.
This document does not give permission to the implementation of patents or other rights held by Eurotech or
third parties.
Revision history
Revision
Description
Date
Draft
First release
13 Jul 2020
Adbc8043 CARRIER BOARD DESIGN GUIDE
3
B37028A0
-MN004-00_UserMan_En_1
Table of contents
Preface ........................................................................................................................................................................ 2
Trademarks .................................................................................................................................................................. 2
Revision history ........................................................................................................................................................... 2
Table of contents .......................................................................................................................................................... 3
Conventions ................................................................................................................................................................. 4
1. Overview .................................................................................................................................................................... 5
2. Mechanical specifications ........................................................................................................................................ 6
2.1 COM Express connectors ...................................................................................................................................... 6
2.2 Component height limits ........................................................................................................................................ 6
2.3 Mounting holes ...................................................................................................................................................... 6
3. Serial Console and Video Output ............................................................................................................................ 8
4. Boot Device................................................................................................................................................................ 9
5. Power Source .......................................................................................................................................................... 10
6. Control Signal .......................................................................................................................................................... 12
6.1. Reset Signal ....................................................................................................................................................... 12
6.2. Power Button Signal ........................................................................................................................................... 12
6.3. Battery Low Voltage Sense Signal ..................................................................................................................... 12
7. I/O Port ..................................................................................................................................................................... 13
7.1 High Speed Signal ............................................................................................................................................... 13
7.2. Signal Trace Guideline ....................................................................................................................................... 14
7.3. PCI Express ........................................................................................................................................................ 15
7.4 USB ..................................................................................................................................................................... 20
7.5 SATA ................................................................................................................................................................... 21
7.6 Ethernet(1Gb) ...................................................................................................................................................... 23
7.7 Ethernet(10Gb) .................................................................................................................................................... 24
7.8 UART ................................................................................................................................................................... 27
7.9 Analog VGA ......................................................................................................................................................... 28
7.10 DisplayPort ........................................................................................................................................................ 28
7.11 Embedded DisplayPort ...................................................................................................................................... 28
7.12 I
2
C ...................................................................................................................................................................... 28
7.13 SMBus ............................................................................................................................................................... 28
7.14 LPC .................................................................................................................................................................... 29
7.15 HD Audio ........................................................................................................................................................... 30
7.16 GPIO .................................................................................................................................................................. 30
7.17 Speaker ............................................................................................................................................................. 30
7.18 SPI ..................................................................................................................................................................... 31
7.19 THRM ................................................................................................................................................................ 31
8. Connector signals ................................................................................................................................................... 32
9. Carrier Board Design Checklist ............................................................................................................................. 40
Notes ............................................................................................................................................................................ 41
Conventions Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
Conventions
The following table describes the conventions for signal names used in this document.
Convention
Explanation
GND
Digital ground plane
#
Active low signal
+
Positive signal in differential pair
-
Negative signal in differential pair
NC
No connection
RSVD
Use is reserved to Eurotech
PU
Pull-up
PD
Pull-down
R **
Ω
Series connection with **Ω resistor
C **F
Series connection with **F capacitor
I/O
Bidirectional signal
I
Input signal
O
Output signal
OD
Open-drain output signal
PI
Power input
Adbc8043 CARRIER BOARD DESIGN GUIDE Overview
5
B37028A0
-MN004-00_UserMan_En_1
1. Overview
This document is a design guide for designing a carrier board on which CPU-162-23 is mounted.
CPU-162-23 is a COM Express CPU Module, featuring Intel Xeon Processor D-1500 series or Pentium
Processor D1500 series, and compatible with PICMG COM.0 R3.0. Combining CPU-162-23 with a carrier board
that meets the customer’s needs allows a variety of integrated systems to be built as desired.
In conjunction with this document, refer to the documents below.
• PICMG COM Express Carrier Design Guide Revision 2.0
• CPU-162-23 User Manual
• Intel Xeon Processor D-1500 Datasheet
Mechanical specifications Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
2. Mechanical specifications
2.1 COM Express connectors
Use the 0.5 mm pitch 440 pin connector pair to connect CPU-162-23 to the carrier board. CPU-162-23 is
equipped with the Tyco Electronics connector 3-1827231-6 or the equivalent. For a stacking connector to be
mounted on the carrier board, use the Tyco Electronics connector 3-1827233-6 or the equivalent for a board to
board spacing of 5mm, and use 3-5353652-6 of the same manufacturer or the equivalent for a board to board
spacing of 8 mm. (To meet the exacting mounting accuracy for the connector, it is recommended to use a set of
connectors which has a jig to keep the distance between two connectors)
2.2 Component height limits
The relative position of the connectors to be mounted on the carrier board and the mounting holes for CPU-162-
23 is as shown in Figure 1. The component mounting height in the overlapped part of CPU-162-23 on the carrier
board (The outline of CPU-162-23 is indicated by the dashed lines in Figure 1.) is limited. For 5 mm stacking height,
the height limite is 1.0 mm. For 8 mm stacking height, the height limit is 4.0 mm.
CPU-162-23 can support up to 4 SO-DIMMs. Special care should be taken in a carrier board design used with
CPU-162-23 with more than 3 sockets (At least one socket at the bottom side). On 8mm stacking carrier board with
3 SO-DIMM module, component height is limited to 2.6mm under the bottom-side SO-DIMM socket. On 5mm
stacking height carrier board with 3 SO-DIMM modules or 8mm stacking height with 4 SO-DIMM modules, the
carrier board have to have 42x78 mm hole to avoid mechanical interference. See Figure 2.
2.3 Mounting holes
CPU-162-23 has 5 mounting holes for fixing the board (Figure 1). Place 5 mounting holes on the carrier board
to fix the board. It is recommended to create a Φ2.7 mm through hole with a Φ6 mm pad as a mounting hole.
Connect the pad to the digital ground of the carrier board.
To mount a connector for a board to board spacing of 8 mm, use a M2.5×8 mm spacer. To mount a connector
for a board to board spacing of 5 mm, use a M2.5×5 mm spacer.
Adbc8043 CARRIER BOARD DESIGN GUIDE Mechanical specification
7
B37028A0
-MN004-00_UserMan_En_1
41
4
4
87
117
2
12
73
4
12.5
D1
C1
D110
C110
B1
A1
B110
A110
63.5
4
4
Figure 1 The position of the connector to be mounted on the carrier board and the mounting hole
Figure 2 Memory socket area
42
9
78
8
Memory socket
Area
125
95
83
Serial Console and Video Output Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
3. Serial Console and Video Output
CPU-162-23 supports a serial console. It is possible to display the BIOS menu, EFI-Shell, DOS, Linux, etc. on
the serial console Figure 3 and Figure 4 show examples of BIOS and Linux. The serial console outputs to UART
Port 0(SER_TX0, SER_RX0).
CPU-162-23 uses a standard BIOS without super I/O. Customizing the BIOS allows Super I/O to be connected
to the LPC bus. To connect Super I/O, contact our sales representative with your model number.
CPU-162-23 does not have a video output, such as VGA. To output a screen to an LCD or other display, use
an external GPU card.
Figure 3 BIOS display example
Figure 4 Linux display example
Adbc8043 CARRIER BOARD DESIGN GUIDE Boot Device
概要
9
B37028A0
-MN004-00_UserMan_En_1
4. Boot Device
CPU-162-23 can boot an OS from a USB device or a SATA device, as a boot device. To use HDD, SSD, CFast,
mSATA, M.2, etc., use an SATA interface. To use an SD card, convert from the USB interface to the SD interface
by using a USB-SD bridge, such as USB2244 manufactured by Microchip. To use an eUSB memory, connect the
eUSB device to the USB interface. Normally, SATA devices are faster than USB devices. CPU-162-23 does not
support booting from the PCI Express device.
Power source Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
5. Power Source
The three types of power sources below are necessary to supply the power from the carrier board to CPU-162-23.
VCC_12V:
The 12V power source is used for normal operation of CPU-162-23.
VCC_5V_SBY:
The 5V power source is used for normal operation of CPU-162-23.
VCC_RTC:
Power source for battery backup. The power source is used to keep the RTC alive.
Table 1 indicates specifications of each power source.
Table 1 Specification of power supply
Power source
name
Use
Rated
voltage
Voltage range
Current
consumption
VCC_12V
Main power source
12V
11.4~12.6V
5.02Atyp *1
VCC_5V_SBY
Main power source
5V
4.75~5.25V
0.34Atyp *1
VCC_RTC
Power source for battery
backup
3V
2.0~3.3V
2.6uAmax
*1 The consumption current of main power source is the maximum current measured with a 65W processor.
Figure 5 and Table 2 show the sequence of power sources from the carrier board to CPU-162-23. Also, each
power source needs to monotonously increase. Table 3 indicates the slew rate limit.
Figure 5 1Power sequence of power supply
Table 2 Power sequence (T1–T6)
No.
Sequence
Standard
T1
From activation of VCC_RTC to activation of VCC_5V_SBY
≥0ms
T2
From activation of VCC_5V_SBY to activation of VCC_12V
Not specified *1
T3
From activation of VCC_12V to assertion of PWROK
≥0ms
T4
From deassertion of PWROK to power-off of VCC_12V
≥0ms
T5
From power-off of VCC_12V to power off of VCC_5V_SBY
Not specified *1
T6
From power-off of VCC_5V_SBY to power off of VCC_RTC
≥0ms
*1 The rising orders of VCC_12V and VCC_5V_SBY are not restricted. Rising can be conducted in the order of VCC_12V and VCC_5V_SBY.
Similarly, the falling orders are not restricted. Falling can be conducted in the order of VCC_5V_SBY and VCC_12V.
VCC_RTC
VCC_12V
VCC_5V_SBY
PWR_OK
95%
95%
95%
T1
T3
T2
T4
T5
T6
Adbc8043 CARRIER BOARD DESIGN GUIDE Power source
概要
11
B37028A0
-MN004-00_UserMan_En_1
Table 3 Slew rate restriction of power source
Power source name
Item
min
max
VCC_12V
Slew rate in rising
0V/ms
120V/ms
Slew rate in falling
0V/ms
12V/ms
VCC_5V_SBY
Slew rate in rising
0V/ms
50V/ms
Slew rate in falling
0V/ms
10V/ms
Control Signal Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
6. Control Signal
6.1. Reset Signal
SYS_RESET# signal is a reset input of CPU-162-23. An input pulse to the SYS_RESET# must be wider than
30ms.
CB_RESET# signal is a reset signal output from CPU-162-23. It can be connected to reset inputs of peripheral
devices on the carrier board.
PWR_OK signal is a status signal of 12V power rail. CPU-162-23 boots after PWR_OK gets High level. Input
High level after the 12V power rail becomes stable. Keeping this signal long may be required if a slow-booting
peripheral device is on the carrier board such as a large-scale FPGA.
Table 4 Reset signal
Signal
Pin
I/O
Pwr Rail
Description
SYS_RESET#
B49
I-CMOS
3.3V
System reset *1
CB_RESET#
B50
O-CMOS
3.3V
Carrier board reset *2
PWR_OK
B24
I-CMOS
3.3V
12V power status
* I/O is the direction from CPU-162-23 side.
*1 Leave this signal unconnected when unused. (This signal is pulled up on CPU-162-23.)
*2 Minimum pulse width is 1 ms.
6.2. Power Button Signal
CPU-162-23 supports a power button signal input (PWRBTN#). In the case of mounting a power button on a
carrier board, it can be connected to CPU-162-23 as PWRBTN# signal.
CPU-162-23 automatically boots when 12V is supplied by default. The behaviour can be modified to wait for
the power button input with a customized BIOS.
Table 5 Power button signal
Signal
Pin
I/O
Description
PWRBTN#
B12
I
Power button signal
* I/O is the direction from CPU-162-23 side.
* Leave this signal unconnected when unused. (This signal is pulled up on CPU-162-23.)
6.3. Battery Low Voltage Sense Signal
CPU-162-23 supports a battery low voltage sense signal input. BATLOW# signal is connected to GPIO14 pin
of the Xeon D SoC. Users can read the state (High/Low) from a GPIO register.
Table 6 Battery low voltage sense signal
Signal
Pin
I/O
Description
BATLOW#
A27
I
Battery low voltage sense
* I/O is the direction from CPU-162-23 side.
* Leave this signal unconnected when unused. (This signal is pulled up on CPU-162-23.)
Adbc8043 CARRIER BOARD DESIGN GUIDE I/O Port
概
13
B37028A0
-MN004-00_UserMan_En_1
7. I/O Port
7.1 High Speed Signal
Following high speed signals requires special care about a characteristic impedance, wire length and via counts
and positions. Requirements and guidelines are described in this section.
10Gb Ethernet signal
10G_KR_TX[0-1]+/-, 10G_KR_RX[0-1]+/- 10Gbps
PCI Express signal
PCIE_RX[0-31]+/-, PCIE_TX[0-31]+/- 2.5 ~ 8Gbps
Serial ATA signal
SATA[0-3]_RX+/-, SATA[0-3]_TX+/- 1.5 to 6Gbps
USB3.0 signal
USB_SSRX[0-3]+/-, USB_SSTX[0-3]+/- 5Gbps
USB2.0 signal
USB[0-3]+/- 0.5Gbps
Clock signal
PCIE_CK_REF+/- 100MHz
SPI_CLK 50MHz
LPC_CLK 33MHz
I/O Port Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
7.2. Signal Trace Guideline
Please design along the following guidelines generally when designing a printed circuit board.
• Route traces by strip line or microstrip line. (Reference plane is digital ground recommendation)
• Maintain reference plane of traces.
• Turn traces more than 135 degree. (See Figure 6)
Figure 6 In the case of turning traces
• Route signals which are no trace length instruction as short as possible without redundancy.
• Route differential pair signals on the same layer.
• Maintain trace width and space between differential pairs signals.
• Place vias of target pair signals symmetrically in the case of transferring the layer of differential pair signals.
In addition, place two GND vias per a pair within 1.27mm of vias of the target pair signals. (See Figure 7)
Figure 7 In the case of transferring the layer of differential pair signals
• Place AC coupling capacitors symmetrically in the case of needing them for differential pair signals.
• Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that use or
generate clocks.
• Avoid stubs on signals because stubs cause signal reflections and affect signal quality.
B
C
A
∠
α
・α is more than 135 degree.
・A is more than 4 times of trace width.
・B and C are more than 1.5 times of trace width.
Max 1.27mm
Adbc8043 CARRIER BOARD DESIGN GUIDE I/O Port
概
15
B37028A0
-MN004-00_UserMan_En_1
7.3. PCI Express
CPU-162-23 is equipped with the PCI Express interface. CPU-162-23 is a root complex, to which PCI Express
devices such as a switch, bridge, and end point can be connected.
Table 7, Table 8, Table 9 and Table 10 indicates the link setting of PCIE[0-7]. Changing the configuration requires
a BIOS customization. The link setting of PCIE[0-7] can be modified on the BIOS menu. Please ask a sales
representative for more detail.
Table 7 PCI Express link configuration (PCIE[3..0])
COM Express
Pin Label
PCI Express
Lane
Link setting 1
Link setting 2
Link setting 3
Link setting 4
(Default)
PCIE3
3
X 1
X 1
X 2
X 4
PCIE2
2
X 1
X 1
PCIE1
1
X 1
X 2 X 2
PCIE0
0
X 1
Table 8 PCI Express link configuration (PCIE[7..4])
COM Express
Pin Label
PCI Express
Lane
Link setting 1
Link setting 2
(Default)
Link setting 3
Link setting 4
PCIE7
(*1)
7
X 1
X 1
X 2
X 4
PCIE6
6
X 1
X 1
PCIE5
5
X 1
X 2
X 2
PCIE4
4
X 1
*1 SW1 should be set ON to enable PCIE7.
Table 9 PCI Express link configuration (PCIE[31..16])
COM Express
Pin Label
PCI Express
Lane
Link setting 1 Link setting 2
Link setting 3
(Default)
PCIE31
15
X 4
X 8
X 16
PCIE30
14
PCIE29
13
PCIE28
12
PCIE27
11
X 4
PCIE26
10
PCIE25
9
PCIE24
8
PCIE23
7
X 4
X 8
PCIE22
6
PCIE21
5
PCIE20
4
PCIE19
3
X 4
PCIE18
2
PCIE17
1
PCIE16
0
Table 10 PCI Express link configuration (PCIE[15..8])
COM Express
Pin Label
PCI Express
Lane
Link setting 1
Link setting 2
PCIE15
7
X 4
X 8
PCIE14
6
PCIE13
5
PCIE12
4
PCIE11
3
X 4
PCIE10
2
PCIE9
1
PCIE8
0
I/O Port Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
Table 11 and Table 12 indicate the PCI Express signals and wiring rules.
For PCIE_RX[0..31]+/-signals, an AC coupling capacitor should be implemented on the PCI Express device side
on the carrier board. Table 13 describes specifications of the AC coupling capacitor. For the PCI Express slot, the
AC coupling capacitor has been mounted on the PCI express card. Thus, the capacitor is not necessary to mount
on the carrier board.
Table 11 PCI Express signals
Signal
Pin
I/O
Description
PCIE_CK_REF+
A88
O
PCI Express clock signal(+)
PCIE_CK_REF-
A89
O
PCI Express clock signal(-)
PCIE_TX0+
A68
O
PCI Express lane.0 TX signal(+)
PCIE_TX0-
A69
O
PCI Express lane.0 TX signal(-)
PCIE_TX1+
A64
O
PCI Express lane.1 TX signal(+)
PCIE_TX1-
A65
O
PCI Express lane.1 TX signal(-)
PCIE_TX2+
A61
O
PCI Express lane.2 TX signal(+)
PCIE_TX2-
A62
O
PCI Express lane.2 TX signal(-)
PCIE_TX3+
A58
O
PCI Express lane.3 TX signal(+)
PCIE_TX3-
A59
O
PCI Express lane.3 TX signal(-)
PCIE_TX4+
A55
O
PCI Express lane.4 TX signal(+)
PCIE_TX4-
A56
O
PCI Express lane.4 TX signal(-)
PCIE_TX5+
A52
O
PCI Express lane.5 TX signal(+)
PCIE_TX5-
A53
O
PCI Express lane.5 TX signal(-)
PCIE_TX6+
D19
O
PCI Express lane.6 TX signal(+)
PCIE_TX6-
D20
O
PCI Express lane.6 TX signal(-)
PCIE_TX7+
D22
O
PCI Express lane.7 TX signal(+)
PCIE_TX7-
D23
O
PCI Express lane.7 TX signal(-)
PCIE_TX8+
A71
O
PCI Express lane.8 TX signal(+)
PCIE_TX8-
A72
O
PCI Express lane.8 TX signal(-)
PCIE_TX9+
A74
O
PCI Express lane.9 TX signal(+)
PCIE_TX9-
A75
O
PCI Express lane.9 TX signal(-)
PCIE_TX10+
A77
O
PCI Express lane.10 TX signal(+)
PCIE_TX10-
A78
O
PCI Express lane.10 TX signal(-)
PCIE_TX11+
A81
O
PCI Express lane.11 TX signal(+)
PCIE_TX11-
A82
O
PCI Express lane.11 TX signal(-)
PCIE_TX12+
A39
O
PCI Express lane.12 TX signal(+)
PCIE_TX12-
A40
O
PCI Express lane.12 TX signal(-)
PCIE_TX13+
A36
O
PCI Express lane.13 TX signal(+)
PCIE_TX13-
A37
O
PCI Express lane.13 TX signal(-)
PCIE_TX14+
A25
O
PCI Express lane.14 TX signal(+)
PCIE_TX14-
A26
O
PCI Express lane.14 TX signal(-)
PCIE_TX15+
A22
O
PCI Express lane.15 TX signal(+)
PCIE_TX15-
A23
O
PCI Express lane.15 TX signal(-)
PCIE_TX16+
D52
O
PCI EXPRESS lane.16 TX signal(+)
PCIE_TX16-
D53
O
PCI EXPRESS lane.16 TX signal(-)
PCIE_TX17+
D55
O
PCI EXPRESS lane.17 TX signal(+)
PCIE_TX17-
D56
O
PCI EXPRESS lane.17 TX signal(-)
PCIE_TX18+
D58
O
PCI EXPRESS lane.18 TX signal(+)
PCIE_TX18-
D59
O
PCI EXPRESS lane.18 TX signal(-)
PCIE_TX19+
D61
O
PCI EXPRESS lane.19 TX signal(+)
PCIE_TX19-
D62
O
PCI EXPRESS lane.19 TX signal(-)
PCIE_TX20+
D65
O
PCI EXPRESS lane.20 TX signal(+)
PCIE_TX20-
D66
O
PCI EXPRESS lane.20 TX signal(-)
PCIE_TX21+
D68
O
PCI EXPRESS lane.21 TX signal(+)
PCIE_TX21-
D69
O
PCI EXPRESS lane.21 TX signal(-)
PCIE_TX22+
D71
O
PCI EXPRESS lane.22 TX signal(+)
PCIE_TX22-
D72
O
PCI EXPRESS lane.22 TX signal(-)
PCIE_TX23+
D74
O
PCI EXPRESS lane.23 TX signal(+)
PCIE_TX23-
D75
O
PCI EXPRESS lane.23 TX signal(-)
Adbc8043 CARRIER BOARD DESIGN GUIDE I/O Port
概
17
B37028A0
-MN004-00_UserMan_En_1
PCIE_TX24+
D78
O
PCI EXPRESS lane.24 TX signal(+)
PCIE_TX24-
D79
O
PCI EXPRESS lane.24 TX signal(-)
PCIE_TX25+
D81
O
PCI EXPRESS lane.25 TX signal(+)
PCIE_TX25-
D82
O
PCI EXPRESS lane.25 TX signal(-)
PCIE_TX26+
D85
O
PCI EXPRESS lane.26 TX signal(+)
PCIE_TX26-
D86
O
PCI EXPRESS lane.26 TX signal(-)
PCIE_TX27+
D88
O
PCI EXPRESS lane.27 TX signal(+)
PCIE_TX27-
D89
O
PCI EXPRESS lane.27 TX signal(-)
PCIE_TX28+
D91
O
PCI EXPRESS lane.28 TX signal(+)
PCIE_TX28-
D92
O
PCI EXPRESS lane.28 TX signal(-)
PCIE_TX29+
D94
O
PCI EXPRESS lane.29 TX signal(+)
PCIE_TX29-
D95
O
PCI EXPRESS lane.29 TX signal(-)
PCIE_TX30+
D98
O
PCI EXPRESS lane.30 TX signal(+)
PCIE_TX30-
D99
O
PCI EXPRESS lane.30 TX signal(-)
PCIE_TX31+
D101
O
PCI EXPRESS lane.31 TX signal(+)
PCIE_TX31-
D102
O
PCI EXPRESS lane.31 TX signal(-)
PCIE_RX0+
B68
I
PCI Express lane.0 RX signal(+)
PCIE_RX0-
B69
I
PCI Express lane.0 RX signal(-)
PCIE_RX1+
B64
I
PCI Express lane.1 RX signal(+)
PCIE_RX1-
B65
I
PCI Express lane.1 RX signal(-)
PCIE_RX2+
B61
I
PCI Express lane.2 RX signal(+)
PCIE_RX2-
B62
I
PCI Express lane.2 RX signal(-)
PCIE_RX3+
B58
I
PCI Express lane.3 RX signal(+)
PCIE_RX3-
B59
I
PCI Express lane.3 RX signal(-)
PCIE_RX4+
B55
I
PCI Express lane.4 RX signal(+)
PCIE_RX4-
B56
I
PCI Express lane.4 RX signal(-)
PCIE_RX5+
B52
I
PCI Express lane.5 RX signal(+)
PCIE_RX5-
B53
I
PCI Express lane.5 RX signal(-)
PCIE_RX6+
C19
I
PCI Express lane.6 RX signal(+)
PCIE_RX6-
C20
I
PCI Express lane.6 RX signal(-)
PCIE_RX7+
C22
I
PCI Express lane.7 RX signal(+)
PCIE_RX7-
C23
I
PCI Express lane.7 RX signal(-)
PCIE_RX8+
B71
I
PCI Express lane.8 RX signal(+)
PCIE_RX8-
B72
I
PCI Express lane.8 RX signal(-)
PCIE_RX9+
B74
I
PCI Express lane.9 RX signal(+)
PCIE_RX9-
B75
I
PCI Express lane.9 RX signal(-)
PCIE_RX10+
B77
I
PCI Express lane.10 RX signal(+)
PCIE_RX10-
B78
I
PCI Express lane.10 RX signal(-)
PCIE_RX11+
B81
I
PCI Express lane.11 RX signal(+)
PCIE_RX11-
B82
I
PCI Express lane.11 RX signal(-)
PCIE_RX12+
B39
I
PCI Express lane.12 RX signal(+)
PCIE_RX12-
B40
I
PCI Express lane.12 RX signal(-)
PCIE_RX13+
B36
I
PCI Express lane.13 RX signal(+)
PCIE_RX13-
B37
I
PCI Express lane.13 RX signal(-)
PCIE_RX14+
B25
I
PCI Express lane.14 RX signal(+)
PCIE_RX14-
B26
I
PCI Express lane.14 RX signal(-)
PCIE_RX15+
B22
I
PCI Express lane.15 RX signal(+)
PCIE_RX15-
B23
I
PCI Express lane.15 RX signal(-)
PCIE_RX16+
C52
I
PCI EXPRESS lane.16 RX signal(+)
PCIE_RX16-
C53
I
PCI EXPRESS lane.16 RX signal(-)
PCIE_RX17+
C55
I
PCI EXPRESS lane.17 RX signal(+)
PCIE_RX17-
C56
I
PCI EXPRESS lane.17 RX signal(-)
PCIE_RX18+
C58
I
PCI EXPRESS lane.18 RX signal(+)
PCIE_RX18-
C59
I
PCI EXPRESS lane.18 RX signal(-)
PCIE_RX19+
C61
I
PCI EXPRESS lane.19 RX signal(+)
PCIE_RX19-
C62
I
PCI EXPRESS lane.19 RX signal(-)
PCIE_RX20+
C65
I
PCI EXPRESS lane.20 RX signal(+)
PCIE_RX20-
C66
I
PCI EXPRESS lane.20 RX signal(-)
PCIE_RX21+
C68
I
PCI EXPRESS lane.21 RX signal(+)
I/O Port Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
PCIE_RX21-
C69
I
PCI EXPRESS lane.21 RX signal(-)
PCIE_RX22+
C71
I
PCI EXPRESS lane.22 RX signal(+)
PCIE_RX22-
C72
I
PCI EXPRESS lane.22 RX signal(-)
PCIE_RX23+
C74
I
PCI EXPRESS lane.23 RX signal(+)
PCIE_RX23-
C75
I
PCI EXPRESS lane.23 RX signal(-)
PCIE_RX24+
C78
I
PCI EXPRESS lane.24 RX signal(+)
PCIE_RX24-
C79
I
PCI EXPRESS lane.24 RX signal(-)
PCIE_RX25+
C81
I
PCI EXPRESS lane.25 RX signal(+)
PCIE_RX25-
C82
I
PCI EXPRESS lane.25 RX signal(-)
PCIE_RX26+
C85
I
PCI EXPRESS lane.26 RX signal(+)
PCIE_RX26-
C86
I
PCI EXPRESS lane.26 RX signal(-)
PCIE_RX27+
C88
I
PCI EXPRESS lane.27 RX signal(+)
PCIE_RX27-
C89
I
PCI EXPRESS lane.27 RX signal(-)
PCIE_RX28+
C91
I
PCI EXPRESS lane.28 RX signal(+)
PCIE_RX28-
C92
I
PCI EXPRESS lane.28 RX signal(-)
PCIE_RX29+
C94
I
PCI EXPRESS lane.29 RX signal(+)
PCIE_RX29-
C95
I
PCI EXPRESS lane.29 RX signal(-)
PCIE_RX30+
C98
I
PCI EXPRESS lane.30 RX signal(+)
PCIE_RX30-
C99
I
PCI EXPRESS lane.30 RX signal(-)
PCIE_RX31+
C101
I
PCI EXPRESS lane.31 RX signal(+)
PCIE_RX31-
C102
I
PCI EXPRESS lane.31 RX signal(-)
PCIE_TX0+
A68
O
PCI Express lane.0 TX signal(+)
PCIE_TX0-
A69
O
PCI Express lane.0 TX signal(-)
PCIE_TX1+
A64
O
PCI Express lane.1 TX signal(+)
PCIE_TX1-
A65
O
PCI Express lane.1 TX signal(-)
PCIE_TX2+
A61
O
PCI Express lane.2 TX signal(+)
PCIE_TX2-
A62
O
PCI Express lane.2 TX signal(-)
PCIE_TX3+
A58
O
PCI Express lane.3 TX signal(+)
PCIE_TX3-
A59
O
PCI Express lane.3 TX signal(-)
PCIE_TX4+
A55
O
PCI Express lane.4 TX signal(+)
PCIE_TX4-
A56
O
PCI Express lane.4 TX signal(-)
PCIE_TX5+
A52
O
PCI Express lane.5 TX signal(+)
PCIE_TX5-
A53
O
PCI Express lane.5 TX signal(-)
PCIE_TX6+
D19
O
PCI Express lane.6 TX signal(+)
PCIE_TX6-
D20
O
PCI Express lane.6 TX signal(-)
PCIE_TX7+
D22
O
PCI Express lane.7 TX signal(+)
PCIE_TX7-
D23
O
PCI Express lane.7 TX signal(-)
PCIE_RX0+
B68
I
PCI Express lane.0 RX signal(+)
PCIE_RX0-
B69
I
PCI Express lane.0 RX signal(-)
PCIE_RX1+
B64
I
PCI Express lane.1 RX signal(+)
PCIE_RX1-
B65
I
PCI Express lane.1 RX signal(-)
PCIE_RX2+
B61
I
PCI Express lane.2 RX signal(+)
PCIE_RX2-
B62
I
PCI Express lane.2 RX signal(-)
PCIE_RX3+
B58
I
PCI Express lane.3 RX signal(+)
PCIE_RX3-
B59
I
PCI Express lane.3 RX signal(-)
PCIE_RX4+
B55
I
PCI Express lane.4 RX signal(+)
PCIE_RX4-
B56
I
PCI Express lane.4 RX signal(-)
PCIE_RX5+
B52
I
PCI Express lane.5 RX signal(+)
PCIE_RX5-
B53
I
PCI Express lane.5 RX signal(-)
PCIE_RX6+
C19
I
PCI Express lane.6 RX signal(+)
PCIE_RX6-
C20
I
PCI Express lane.6 RX signal(-)
PCIE_RX7+
C22
I
PCI Express lane.7 RX signal(+)
PCIE_RX7-
C23
I
PCI Express lane.7 RX signal(-)
WAKE0#
B66
I
PCI Express Wake-up signal*1
* I/O direction is from CPU-162-23.
* Leave the signal unconnected when unused.
*1 The signal is pulled up on CPU-162-23.
Adbc8043 CARRIER BOARD DESIGN GUIDE I/O Port
概
19
B37028A0
-MN004-00_UserMan_En_1
Table 12 PCI Express signal trace routing rule
Parameter
Min
Typ
Max
Unit
PCIE_CLK_REF+/-
Characteristic impedance (differential)
77
85
93
Ω
Signal length (PCI Express device)
402
mm
Signal length (PCI Express slot)
228
mm
Length matching between differential pairs
0.127
mm
Spacing from other signals
0.508
mm
Via Usage
2
PCIE_TX/RX[0..7]+/-
Characteristic impedance (differential)
77
85
93
Ω
Signal length (PCI Express Gen1,Gen2 device)
402
mm
Signal length (PCI Express Gen3 device)
254
mm
Signal length (PCI Express Gen1,Gen2 slot)
228
mm
Signal length (PCI Express Gen3 slot)
101
mm
Length matching between differential pairs
0.127
mm
Spacing from other signals
0.508
mm
Via Usage (TX)
2
Via Usage (RX Gen1,Gen2,Gen3 device)
4
Via Usage (RX Gen1,Gen2 slot)
4
Via Usage (RX Gen3 slot)
2
* There are no trace length rules in other single-ended signals. Please route with a 50Ω±10% characteristic impedance.
Table 13 PCI Express AC coupling capacitors
Parameter
Gen1
Gen2
Gen3
Unit
Capacitance
0.1
0.1
0.22
μF
Tolerance
±10
±10
±10
%
Package size
< 1608
< 1608
< 1608
mm
Temperature characteristic
X7R
X7R
X7R
PCI Express clock (PCIE_CLK_REF+/-) is output from CPU-162-23. In the case of mounting a PCI Express
device or slot on a carrier board, please connect PCIE0_CLK_REF+/- signal to a PCI Express device or slot.
(See Figure 8)
In the case of mounting more than two PCI Express devices or slots on a carrier board, please distribute PCI
Express clock to each device or slot by using a clock buffer (IDT:ICS9DBL411BGILF or equivalent).
(See Figure 9)
Figure 8 In the case of supplying PCI Express clock to a PCI Express device or slot
CPU-162-23
I/O Port Adbc8043 CARRIER BOARD DESIGN GUIDE
B37028A0-MN004-
00_UserMan_En_1
Figure 9 In the case of distributing PCI Express clock to multiple PCI Express devices or slot
7.4 USB
CPU-162-23 is equipped with 4 ports of USB3.0 interfaces and 4 ports of USB2.0 interfaces, to which a USB
device can be connected respectively.
USB3.0 uses 4 signals lines of USB_SSTX[n]+/- and USB_SSRX[n]+/-.
USB2.0 uses 2 signal lines of USB[n]+/-.
When corresponding to the both of USB3.0 and USB2.0, 6 signal lines are used for USB_SST[n]+/-,
USB_SSRX[n]+/-, and USB[n]+/-.
Table 14 to Table 16 indicate the USB signals and wiring rules.
The USB bus power (5V) should be supplied from the carrier board, and an over-current sensing circuit should
be placed. The USB_0_1_OC# signal should be set an open collector or open drain signal that becomes LOW
when over-current occurs on USB0 or USB1.
It is recommended to expose USB1+/-signals to a connector on a carrier board if a BIOS customize is expected.
Table 14 USB signal
Signal
Pin
I/O
Description
USB_SSTX0+
D4
O
USB 3.0 port0 TX signal(+)
USB_SSTX0-
D3
O
USB 3.0 port0 TX signal(-)
USB_SSRX0+
C4
I
USB 3.0 port0 RX signal(+)
USB_SSRX0-
C3
I
USB 3.0 port0 RX signal(-)
USB_SSTX1+
D7
O
USB 3.0 port1 TX signal(+)
USB_SSTX1-
D6
O
USB 3.0 port1 TX signal(-)
USB_SSRX1+
C7
I
USB 3.0 port1 RX signal(+)
USB_SSRX1-
C6
I
USB 3.0 port1 RX signal(-)
USB_SSTX2+
D10
O
USB 3.0 port2 TX signal(+)
USB_SSTX2-
D9
O
USB 3.0 port2 TX signal(-)
USB_SSRX2+
C10
I
USB 3.0 port2 RX signal(+)
USB_SSRX2-
C9
I
USB 3.0 port2 RX signal(-)
USB_SSTX3+
D13
O
USB 3.0 port3 TX signal(+)
USB_SSTX3-
D12
O
USB 3.0 port3 TX signal(-)
USB_SSRX3+
C13
I
USB 3.0 port3 RX signal(+)
USB_SSRX3-
C12
I
USB 3.0 port3 RX signal(-)
USB0+
A46
I/O
USB 2.0 port0 signal(+)
USB0-
A45
I/O
USB 2.0 port0 signal(-)
USB1+
B46
I/O
USB 2.0 port1 signal(+)
USB1-
B45
I/O
USB 2.0 port1 signal(-)
USB2+
A43
I/O
USB 2.0 port2 signal(+)
USB2-
A42
I/O
USB 2.0 port2 signal(-)
USB3+
B43
I/O
USB 2.0 port3 signal(+)
USB3-
B42
I/O
USB 2.0 port3 signal(-)
USB_0_1_OC#
B44
I
USB port0, port1 over current detection signal *1
CPU-162-23
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
/