RTD Embedded Technologies, Inc. | www.rtd.com v DMx820 User’s Manual
Device Memory ......................................................................................................................................................................... 28
6.2.1 Memory Map Overview ...................................................................................................................................... 28
Detailed Register Description ................................................................................................................................................... 37
6.3.1 System Block ..................................................................................................................................................... 37
FPGA_VERSION .......................................................................................................................................................... 37
SVN_VERSION ............................................................................................................................................................ 37
BOARD_RESET ........................................................................................................................................................... 38
BRD_STAT ................................................................................................................................................................... 38
INT_ENABLE ................................................................................................................................................................ 38
INT_STATUS ................................................................................................................................................................ 39
6.3.2 Standard I/O ....................................................................................................................................................... 40
PORTx_OUTPUT ......................................................................................................................................................... 41
PORTx_INPUT ............................................................................................................................................................. 41
PORTx_TRISTATE ...................................................................................................................................................... 42
PORTx_MODE ............................................................................................................................................................. 42
PORTx_PERIPH_SEL_L ............................................................................................................................................. 42
PORTx_PERIPH_SEL_H ............................................................................................................................................. 42
STROBE_STATUS....................................................................................................................................................... 43
6.3.3 82C54 Timer Counter Control ............................................................................................................................ 44
TC_ID ........................................................................................................................................................................... 44
TC_INT ......................................................................................................................................................................... 44
TC_xy_CONTROL........................................................................................................................................................ 45
6.3.4 FIFO Channel n ................................................................................................................................................. 46
FIFOn_ID ...................................................................................................................................................................... 46
FIFOn_INT .................................................................................................................................................................... 46
FIFOn_IN_CLK ............................................................................................................................................................. 46
FIFOn_OUT_CLK ......................................................................................................................................................... 47
FIFOn_IN_DATA_DREQ .............................................................................................................................................. 48
FIFOn_CON_STAT ...................................................................................................................................................... 48
FIFOn_RW_PORT ....................................................................................................................................................... 49
6.3.5 Programmable Clock n ...................................................................................................................................... 49
PROGCLKn_ID ............................................................................................................................................................ 49
PROGCLKn_MODE ..................................................................................................................................................... 49
PRGCLKn_CLK ............................................................................................................................................................ 50
PRGCLKn_START_STOP ........................................................................................................................................... 50
PROGCLKn_PERIOD .................................................................................................................................................. 52
PROGCLKn_COUNT ................................................................................................................................................... 52
6.3.6 Advanced Interrupt n.......................................................................................................................................... 53
ADVINTn_ID ................................................................................................................................................................. 53
ADVINTn_INT_MODE .................................................................................................................................................. 53
ADVINTn_CLK ............................................................................................................................................................. 53
ADVINTn_PORTx_MASK ............................................................................................................................................ 54
ADVINTn_PORTx_CMP............................................................................................................................................... 54
ADVINTn_PORTx_CAPT ............................................................................................................................................. 54
6.3.7 Dual Incremental Encoder n .............................................................................................................................. 55
INCENCn_ID ................................................................................................................................................................ 55
INCENCn_INT .............................................................................................................................................................. 56
INCENCn_CLK ............................................................................................................................................................. 57
INCENCn_MODE ......................................................................................................................................................... 57
INCENCn_VALUEy ...................................................................................................................................................... 58
6.3.8 Quad Pulse Width Modulator n .......................................................................................................................... 59
PWMn_ID ..................................................................................................................................................................... 59
PWMn_MODE .............................................................................................................................................................. 59
PWMn_CLK .................................................................................................................................................................. 60
PWMn_PERIOD ........................................................................................................................................................... 60
PWMn_WIDTHx ........................................................................................................................................................... 60
6.3.9 82C54 Timer Counter n ..................................................................................................................................... 61
DESCRIPTION OF OPERATION ................................................................................................................................. 61
Control Word and Count Value Program ...................................................................................................................... 61
Mode definition ............................................................................................................................................................. 62
Reading Counter Values .............................................................................................................................................. 66
PLX Registers ........................................................................................................................................................................... 70
6.4.1 Memory Map Overview ...................................................................................................................................... 70
6.4.2 DMA Register Description ................................................................................................................................. 70
DMAMODEn ................................................................................................................................................................. 70