User Manual
AMT49502 Demo Board
UM-AMT49502
MCO-0001171
December 9, 2021
INTRODUCTION
The AMT49502 demo board is designed to aid system designers with evaluating the operation and performance of Allegro’s
AMT49502 48V Safety Automotive, Half-Bridge MOSFET Driver. This application note describes the components of the
AMT49502 Demo Board and explains how it can be used to achieve normal operation. To simplify understanding, compo-
nents of the demo board are categorized into different topics.
Figure 1: AMT49502 Demo Board
Table of Contents
Introduction ......................................................................... 1
Power Supplies .................................................................... 2
VBB Supply ...................................................................... 2
VBRG Supply ................................................................... 2
VL Supply ........................................................................ 2
Communication Ports ........................................................... 2
Switches ............................................................................. 2
RESETn ............................................................................. 3
Output Terminals .................................................................. 3
Jumpers .............................................................................. 3
LEDs .................................................................................. 3
AMT49502KLP SMT Demo Board Schematic (1 of 2) ............... 4
AMT49502KLP SMT Demo Board Schematic (2 of 2) ............... 5
Revision History ................................................................... 6
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
POWER SUPPLIES
Three power supplies must be available on the board for full opera-
tion. These are the VBB, VBRG, and VL power supplies. In each
case, there is a ground terminal next to the supply terminal. This
ground terminal is connected to the common ground plane.
VBB Supply
This terminal provides the main power to the AMT49502. There
are two connection options for energizing VBB and VBRG:
1. Common VBB, VBRG: Connect power to X7 and t J8 (no
external power connection to X1).
2. Independent VBB, VBRG: Remove J8 and connect separate
power supplies to X1 and X7.
The diode D1 protects the VBB pin from negative transients by
ensuring unidirectional current flow. This diode can be bypassed
by engaging jumper J1.
VBRG Supply
The voltage bias on the half bridge is supplied by this terminal. As
discussed in the previous section, J8 interconnects VBRG to VBB.
VL Supply
This supply provides power to the control logic (HS and LSn),
the ENABLE pin, and the DIAG status LED (LED3). Because
this is a logic supply, its maximum voltage is dependent on the
product variant (3.3 V or 5 V).
VL may be generated from VREG via linear regulator U2 (J2 in
position U2) or a suitable external supply may be connected via
connector X4 (J2 in position X4).
The linear regulator U2 is fitted on both the 5 V and 3.3 V boards.
Although this is a 5 V regulator, the AMT49502‑3 logic inputs
are tolerant to this voltage level, will operate correctly, and will
not suffer any damage. However, care should be taken to ensure
that any 3V3 devices connected to ENABLE, HS, or LS will not
suffer damage; therefore, 1K buffer resistors are placed in series
to provide a level of protection to devices connected to X3.
COMMUNICATION PORTS
Communication to the microcontroller is accomplished via a
USB micro-B header or an IDC 26-way ribbon header.
The default method of communication is the USB micro-B con-
nection. This header is connected to an on‑board FTDi FT232RL
device (U4) that translates the USB signals to serial communica-
tion logic. The logic levels can be set to either 3.3 V or 5 V using
jumper J14.
To switch from the default method of communication to SPI
communication, the R36–R39 resistors are removed, then the
SPI‑compatible signals are connected to the X3 header pins 1, 3,
5, 7, 9, and 11.
SWITCHES
The DIL four‑way switch actuator (S1) contains three active
switches—S1, S2, and S3. The operation of these switches is
described in Table 1.
Table 1: AMT49502 Demo Board Switch Operation
Switch Control Pin On State Off State
S1 ENABLE ENABLE connected
to VS
ENABLE
floating
S2 HS HS connected
to VS
HS Floating
S3 LSn LSn connected
to GND
LSn floating
Both the ENABLE a HS pins contain an internal pull-down resis-
tor so when they are left floating, they are pulled to logic low.
The LSn pin contains an internal pull-up resistor that pulls it to
logic high when it is left floating.
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
RESETn
The AMT49502 contains a RESETn input pin that allows the
device to be put into standby mode when it is pulled low. This
pin has a voltage rating up to the supply voltage, so it can be
directly connected to VBB via R26. This 470 kΩ resistor limits
the current flowing into RESETn. The jumper J11 is in series
with RESETn. To put the device into sleep mode, jumper J11
is be removed. When J11 is removed and left open, the internal
pull-down resistor pulls the pin to a logic low level.
To clear latched faults, RESETn can also be pulsed low for the
reset pulse width, tRST. To achieve this function, J11 is removed
and RESETn is connected directly to a logic controller.
OUTPUT TERMINALS
The half-bridge contains three output terminals; S, LSD, and
LSS. These terminals can be connected to various external
devices to produce different series-connected and external load
configurations. The jumper (J7), found between S and LSD,
allows the user to switch between operational configurations.
When J7 is engaged, the AMT49502 can be used in a comple-
mentary half-bridge configuration allowing an external load to be
connected. Removal of J7 allows the device to drive independent
high-side and low-side MOSFETs for the series-connected load
configuration. Note that, in this configuration, the low-side VDS
monitor should be disabled by setting the LO bit to 1 in the Mask
1 register. This is necessary as the reference voltage for the drain
of the low-side MOSFET is the S terminal, which will be pulled
to the supply when the high-side MOSFET is on and will cause a
false low-side VDS fault if the low-side VDS monitor is active.
Current-carrying loads must be connected to the S and LSD ter-
minals instead of the J7 pins because they have a higher current‑
carrying capability.
JUMPERS
The 10 different jumpers of the AMT49502 demo board are used
as follows:
• J1 bypasses the VBB protection diode.
• J2 selects the source of the logic supply. This can be either
from the on‑board regulator (U2) or the external supply(X4).
• J7 connects the source (S) of the high side MOSFET to the
drain (LSD) of the low side MOSFET. Removal of J7 allows
independent control of both MOSFETs.
• J8 connects the VBB and VBRG supplies together.
• J9 short‑circuits the gate resistor of the high‑side MOSFET to
allow it to operate in slew rate control mode. This jumper must
be removed from the board when operating with gate drive
control disabled.
• J10 short‑circuits the gate resistor of the low‑side MOSFET to
allow it to operate in slew rate control mode. This jumper must
be removed from the board when operating with gate drive
control disabled.
• J11 pulls RESETn to a high logic level when it is engaged.
RESETn is internally pulled to logic low if J11 is removed.
• J12 connects VREG to the supply of the on‑board regulator.
This jumper must be engaged if VS is being supplied from the
regulator.
• J13 is left open in its default state. When this jumper is
engaged, it allows complementary control of HS and LSn.
• J14 toggles between 3.3 V and 5 V logic when using the USB
micro-B communication port.
LEDS
The AMT49502 demo board contains three red LEDs. Each LED
is used as a different indicator:
• LED1 is connected between VBB and ground through a
current source and is used to indicate when the VBB terminal
is energized.
• LED2 is connected to VBRG and is used to indicate when
the bridge is energized. This LED may be considered as an
additional safety feature of the demo board because it remains
on until the DC link capacitor is discharged.
• LED3 is connected to DIAG, and it turns on when DIAG goes
low. This LED, therefore, displays when the AMT49502 has a
fault in the diagnostic register.
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
1
2
3
4
LM2936HV-3.3
GND
IN
OUT
3V3
U2
100n
63V
C2
X3.19
X3.21
X3.13
X3.17
X3.3
X3.7
X3.9
X3.11
X3.15
GND1
GND5
V5
1
2
3
4 5
6
7
8
123 4
S1
GND
VREG
GL
GH
GND
VBRG
C
S
X1.2
X1.1
- +
E-202
CRD1
LED1
GND
X4.2
X4.1
100n
16V
C3
GND
LSS
VBB
EN
LSn
HS
RSTn
STRn
SCK
SDI
SDO
DIAG
BC807
Q1
2k2
R17
LED3
GND
V5
DIAG
GND2
GND
GND
1k
R4
1k
R5
1k
R6
1k
R7
1k
R8
1k
R9
1k
R10
1k
R11
1k
R12
330n
25V
C7
33R
R32
470k
R31
470k
R30
33R
R33
GND3 GND4
6k65
R2
GND
ENABLE
HS
LSn
RESETn
STRn
SCK
SDI
SDO
DIAG
CSO
OOS
X3.23
1k
R14
1k
R13
OOS
CSO
X3.25
CSM
CSP
GND
VBB
GND
GND
1
CSP
14
CSM
13
LSS
15
GH
17
GL
16
S
18
C
19
CP2
21
CP1
22
VBB
23
VBRG
24
VREG
20
TAB
25
DIAG
2
RESETn
4
HS
5
LSn
6
SDI
7
SDO
9
SCK
8
STRn
10
ENABLE
3
CSO
12
OOS
11
AMT49502KLP
U1
22u
16V
+
C1
J1
470n
100V
C5
DNF
10u
100V
+
C4
GND
10u
25V
C6
1000u
160V
+
C8
J7
X2.3
X2.2
X2.1
LSD
100n
100V
C9
IRLR3110Z
M1
M2
1W
0R022
R24
1W
0R022
R25
X7.1
X7.2
GND
J8
GND
- +
E-202
CRD2
LED2
GND
GND
J9
J10
25V
2.2u
C10
VREG
RSTn
47k
R26
J11
RSTn
GND
GND
GND
VREG
J12
J2
DIAG
DIAG
VL
27k
R15
27k
R16
STRn
SCK
SDI
SDO
X3.5
X3.1
VL
GND
VBRG
GND
S
LSS
VBB
POWER
VBRG
POWER
(Vbrg Bleed)
GND
LSD
VL
GND
"DNF"
font = Text to be visible on PCB silkscreen.
(italics) = "Do No Fit" (component not tted).
Note:
Bold
Note:
1W
10k
R35
GND
LSn = HS
VL
X4
U2
LSn
HS
EN
J13
1N4148W
D1
RSTn
T IT L E :
Allegro Microsystems
955 Premier Road
Manchester
NH 03103 USA
AMT49502KLP SMT Demonstration Board Rev1
P A C KA G E :
LP: TSSOP24
1
R E V :
P C B :
EDC166R1
A U T H O R :
M.Hunkin 3rd Feb 2020
D A T E :
S H EET :
1 of 2
S IZ E :
A4
Net-Tie1
AMT49502 DEMO BOARD SCHEMATIC
Figure 2: AMT49502KLP SMT Demo Board Schematic (1 of 2)
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
1
1
2
2
3
3
4
4
DD
CC
BB
AA
TXD 1
DTR# 2
RTS# 3
VCCIO
4
RXD 5
RI# 6
GND1
7
NC1
8DSR# 9
DCD# 10
CTS# 11
CBUS4 12
CBUS2 13
CBUS3 14
USBDP
15 USBDM
16
3V3OUT
17
GND2
18
RESET#
19
VCC
20
GND3
21
CBUS1 22
CBUS0 23
NC2
24
AGND
25
TEST
26
OSCI
27
OSCO
28
FT232RLU4
Port Protect
VCC1
1
A1
2
A2
3
GND1
4GND2 5
B2 6
B1 7
VCC2 8
USB6B1
U3
GND
100n
10V
C16
GND
3V3
3V3
●
J14
USB-Micro-B
SHD 6
GND 5
ID (NC) 4
D+ 3
D- 2
+V 1
X8
47p
10V
C11
47p
10V
C12
GND GND
4.7u
16V
C13
100n
16V
C14
10n
16V
C15
GND GND GND
3V3
5V
font = Text to be visible on PCB silkscreen.
Bold
Note:
X3 pinout:-
1
3
5
11
13
9
7
15
17
19
21
23
25
2
4
6
12
14
10
8
16
18
20
22
24
26
GND
STRn
VL
SCK
SDI
SDO
HS
RSTn
CSO
OOS
LSn
0RR36
0R
R37
0R
R38
0R
R39
SCK
SDI
SDO
STRn
EN
DIAG
TITLE:
Allegro Microsystems
955 Premier Road
Manchester
NH 03103 USA
AMT49502KLP SMT Demonstration Board Rev1
PACKAGE: LP: TSSOP24
1
REV:
PCB: EDC166R1
AUTH OR: M.Hunkin 3rd Feb 2020
DATE:
SHEET: 2 of 2
SIZE: A4
X3 PINOUT
26 DIAG 25
24 EN 23
22 RSTn 21
20 HS 19
18 LSn 17
16 OOS 15
14 CSO 13
12 SDO 11
10 SDI 9
8 SCK 7
5 VL 5
4 STRn 3
2 GND 1
Figure 3: AMT49502KLP SMT Demo Board Schematic (2 of 2)
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Revision History
Number Date Description
– December 9, 2021 Initial Release
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
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