2
Revisions and Notes
Date
Owner
Revision
Notes
Feb. 25th 2018
Noam Wiedenfeld
1.0
Initial release
Disclaimer
No warranty of accuracy is given concerning the contents of the information contained in this
publication. To the extent permitted by law no liability (including liability to any person by reason of
negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect
loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the
right to change details in this publication without prior notice. Product and company names herein
may be the trademarks of their respective owners.
© 2018 SolidRun Ltd. All Rights Reserved.
Please verify that you have the most current version of this document from: www.solid- run.com
3
Table of Content
Introduction ........................................................................................................................................................ 4
Overview ............................................................................................................................................................. 4
Highlighted Features .......................................................................................................................................... 4
Supporting Products ........................................................................................................................................... 5
Description ......................................................................................................................................................... 5
Block Diagram ................................................................................................................................................. 5
Feature Summary ........................................................................................................................................... 6
Core System Components .................................................................................................................................. 7
i.MX8 SoC Family ............................................................................................................................................ 7
Memory .......................................................................................................................................................... 8
10/100/1000 MBPS ETHERNET PHY ............................................................................................................. 10
WI-FI (11AC/B/G/N 2TX2R) TYPE 1216 AND BT 5.0 ...................................................................................... 10
MIPI CSI-2 CAMERA INTERFACE ................................................................................................................... 11
i.MX8 SOM External Interfaces ......................................................................................................................... 12
General ......................................................................................................................................................... 12
Supported Interfaces .................................................................................................................................... 12
Power and Reset ............................................................................................................................................... 23
Reset ............................................................................................................................................................. 23
i. MX8 SOM Integration Manual ........................................................................................................................ 24
Power up sequence ...................................................................................................................................... 24
Booting Options ............................................................................................................................................ 24
I2C Interfaces ................................................................................................................................................ 26
GPIO Interfaces ............................................................................................................................................. 26
i. MX8 SOM Debugging Capability ................................................................................................................. 26
i.MX8 Typical Power Consumption................................................................................................................... 27
i. MX8 SOM Mechanical Description ................................................................................................................. 28
Ordering Information ....................................................................................................................................... 29
5
Introduction
This User Manual relates to the SolidRun SOM i.MX8M series, which includes:
•
Dual core ARM A53 (1.5 GHz) of the i.MX8M SoC.
•
Quad lite core ARM A53 (1.5GHz) of the i.MX8M SoC.
•
Quad core ARM A53 (1.5GHz) of the i.MX8M SoC.
Overview
The SolidRun’s SOM i.MX8M is a high-performance system on module (SOM) based on the
highly integrated NXP i.MX8M family of products.
Highlighted Features
• Ultra-small footprint SOM (47x30mm) including three board-to-board
connectors (250 total pins number).
• NXP i.MX8M SoC (supports dual, quad lite and quad versions)
o
Up to quad Cortex A53 and up to 1.5GHz
o
Cortex-M4 subsystem processor supports real time tasks.
o
Industry-leading audio, voice and video processing for applications
o
OpenGL ES 3.1, OpenCL 1.2, OpenGL 3.0, OpenVG and Vulkan
standards
• LPDDR4 memory in x32 configurations supports up to 4GB (Quad version)
• Power management devices
• Gigabit Ethernet interface based on Qualcomm Atheros 8031
• Wi-Fi (11ac/b/g/n 2Tx2R) + BT (V4.1 LE) M.2 Type 1216 based on Qualcomm
Atheros QCA6174A-5.
• BT V5.0 based on Nordic’s nRF52832.
• PCIe clock generator supporting Gen2.
• 4-Lanes CSI connector for direct connection to a camera.
6
NOR
eMMC
Supporting Products
The following products are provided from SolidRun both as production level platforms and as
reference examples on how to incorporate the SOM in different levels of integration:
• HummingBoard Pulse– A board computer that incorporates the SOM retains the same
Android and different Linux distributions while adding extra hardware functionalities and
access to the hardware.
• CuBox-Pulse – A minicomputer that is only 2"x2"x2" in size that runs Android and Linux with
different distribution variants, use cases.
Description
Block Diagram
The following figure describes the i.MX8 Blocks Diagram.
10/100/1000
AR8031
GE PHY
RGMII
32 Bits
Up to 4GB
USB1 (USB3/ USB2)
USB2 (USB3/ USB2) QSPIA, SS0
4K HDMI Level
adapter
SDIO1, 8 Bits
PCIe 2
UART 1 (RX/TX)
IMX-8M
I2C1
C
O
N
N
E
C
T
O
R
S
UART 2/3 (RX/TX/CTS/RTS)
ESPI2 SS0
I2C2/ I2C3
SDIO2 (4 BITS/ VSelect)
CSI 1 (2, 4 Lanes)
SAI2/3(TX/RX/TXC/MCLK/TXFS)
SAI1 (Full Bus)
GPIO
Boot Mode, Boot SEL
Reset, Conttrol
QUAD
QUAD Lite
DUAL
PCIe 1
WI-FI AC
EEPROM
UART 4
BT 5.0
CSI 2 (2, 4 Lanes)
F
P
C
Cortex M4
3.3V
5V
Power
3.3V
PMIC
CLK2_O
PCIe_CLK2
PCIe_CLK1
PCIe CLK
PCIe_CLK2 Buffer
WI-FI
7
Feature Summary
Following is the features summary of the SOM. Notice that some of the features are pinout
multiplexed (please refer to the pin mux table below and the NXP i.MX8M data sheets):
• NXP i.MX8M series SoC (Dual/Quad Lite/Quad ARM® Cortex™ A53 Processor, up to
1.5 GHz)
• Cortex-M4 subsystem processor.
• Up to 4GByte LPDDR4 memory
• Eight bits eMMC memory.
• QSPI NOR Flash memory.
• I2C EEPROM.
• HDMI 2.0a, HDMI 1.4 interface
• 4-lanes MIPI-DSI interface
• Two 4 lanes MIPI CSI-2 ()
• 10/100/1000 Mbps Ethernet PHY supporting 1588 standard (PPS output)
• Wi-Fi (11ac/b/g/n 2Tx2R) + BT (V4.1 LE) M.2 Type 1216 based on Qualcomm Atheros
QCA6174A-5.
• BT V5.0 based on Nordic’s nRF52832
• Two USB 3.0 Host and OTG
• Two PCIe interfaces (PCIe-1 is available only if Wi-Fi is not in use).
• PCIe clock generator.
• Four bits SD interface
• Single eSPI interface.
• Up to three Synchronous Audio Interfaces.
• Up to three Serial interfaces.
• Required power sources:
o
A single 5.0V interface
o
1.8/3.3V to support uSD card optional IO power.
8
Core System Components
i.MX8 SoC Family
The i.MX8M Dual / 8M QuadLite / 8M Quad processors feature advanced implementation of a quad
Arm® Cortex®-A53 core, which operates at speeds of up to 1.5 GHz. A general- purpose Cortex®-M4
core processor is for low-power processing.
The following figure describes the i.MX8 SoC’s main features (For more details refer to NXP’s
i.MX8 datasheet).
i. MX8 supports three variants; the following table describes the main differences:
9
LPDDR4
eMMC
Memory
The IMX-8 SOM support varieties of memory interfaces for booting and data storage. The following
figure describes the IMX-8 SOM memory interfaces.
Carrier SOM
LPDDR4
•
Up to 4GB memory space (QUAD-Light and Dual up to 3GB).
•
32 Bits data bus.
•
Up to 3200 MT/s.
•
Supports D1, D2 and D4 die chips (Two CS).
•
Support various low power modes, clock and power gated operation.
•
Support Self-Refresh mode.
eMMC NAND Flash
•
Up to 64GB memory space.
•
8 Bits data bus.
•
Support MMC standard, up to version 5.0.
•
Up to 1600 Mbps of data transfer for MMC cards using 8 parallel data lines in SDR
mode.
•
Up to 3200 Mbps of data transfer for MMC cards using 8 parallel data lines in DDR
mode.
•
IMX-8 uSDHC-1.
•
Can be used as BOOT NVM *
USB2/3
32 Bits
NOR
ESPI2, SS0
IMX-8
QSPAI, SS0
uSD
SDIO2, 4 Bits
QUAD
QUAD-Light
DUAL
SDIO1, 8 Bits
I2C1
EEPROM
EEPROM
I2C2/3
NOR
10
Quad Serial NOR Flash (SOM)
•
Each channel can be configured as 1/2/4-bit operation.
•
Support both SDR mode and DDR mode
•
No reset
•
IMX-8 QSPIA/nSS0.
•
Can be used as BOOT NVM *
EEPROM (SOM)
• 1Kb EEPROM
• ON-Semi’s CAT24AA01TDI or compatible
• IMX-6 I2C1
• Address 0X50 (7 bits format)
• Stores SOM’s configurations.
Micro-SD (Carrier)
• Optional on Carrier board
• IMX-8 uSDHC-1.
• Implements 4 data bits.
• Support SD/SDIO standard, up to version 3.0.
• Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR
mode using 4 parallel data lines.
• Can be used as BOOT NVM *
Serial NOR Flash (Carrier)
• Optional on Carrier board
• 1 bits data bus.
• IMX-8 eSPI2/nSS0
• Can be used as BOOT NVM *
*Please Note – All boot configuration signals are available on the SOM
connector.
11
2
D
C
o
n
n
e
c
t
o
r
10/100/1000 MBPS ETHERNET PHY
The Ethernet PHY is based on the Qualcomm / Atheros AR8031. The following figure describes
the Giga Ethernet interface.
P PS
M
•
IMX-8 RGMII interface.
•
IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-Te.
•
Atheros AR8031 PHY.
•
Supports 1588 (PPS signal).
•
25M clock supports Synchronous Ethernet.
WI-FI (11AC/B/G/N 2TX2R) TYPE 1216 AND BT 5.0
The following figure describes the WI-FI and BT support in the IMX-8 SOM.
USB
SW
IMX-8
TX
RGMII REF_CLK
RX
GE
AR8031
MDC/MDIO 25
25M
PHY &
MAG
C
o
n
n
e
c
t
o
r
PCIe
CLK Buff.
IMX-8
CLKO2
PCIe-1
UART-4 TX/RX
M.2 1216
11ac/b/g/n
+
BT 4.1 LE
BT 5.0
12
WI-FI
The WI-FI module is an M.2 1216 standard LGA module. The i.MX8 WI-FI module is Silex’s
WCBN3507A which based on Qualcomm Atheros QCA6174A-5 chip. The WI-FI main features are:
• Operate at ISM frequency Band (2.4/ 5 GHz)
• IEEE Standards Support 802.11ac, 802.11a, 802.11b, 802.11g and 802.11n
• IMX-8 PCIe-1 interface
• Enterprise level security supporting: WPA, WPA2
• Support 2 transmission and 2 receiving, transmission rate can up to
867Mbps(Physical Rate) in downstream and upstream
• USB2 connection is optional from carrier board to support BT over the M.2 module (*).
• Global certification.
BT 5.0
The i.MX8 SOM uses U-BLOX’s NINA-B111 module. The module is based on Nordic’s
nRF52832 BT SoC. The module main features are:
• Bluetooth 5.
• Advanced Serial Port Service.
• GATT server and client.
• Open CPU with Arm® Mbed™ and Nordic SDK.
• External antenna.
• Global certification.
Please Note: (*) the Silex M.2 module doesn’t support BT over UART.
MIPI CSI-2 CAMERA INTERFACE
The i.MX8 SOM supports a 4-Lanes MIPI CSI-2 interface. A 22 pins
FPC connector on the SOM board enables a direct connection to a
Camera supporting the CSI interface.
The connector pin-out is according to Allied Vision, a cameras
manufacturer. The figure to the right describes the interface
signals.
12
WI-FI
Resistor
Assembly
Option
REF_CLK
REF_CLK
PCIe
CLK Buff.
C
o
n
n
e
c
t
o
r
• IMX-8 MIPI CSI channel 2.
• Implements all three CSI-2 MIPI layers.
• Scalable data lane support, 1 to 4 Data Lanes.
• Supports high speed mode (80Mbps - 1.5Gbps) per lane, providing
4K@30fpscapability for the 4 lanes.
• Virtual Channel support.
i.
MX8 SOM External Interfaces
General
The SOM incorporates three Hirose DF40 board-to-board headers. The
selection of the Hirose DF40 is due to the following criteria:
• Miniature (0.4m pitch)
• Highly reliable manufacturer
• Availability (worldwide distribution channels)
• Excellent signal integrity (supports 6Gbps)
o Please contact Hirose or SolidRun for reliability and test result data.
• Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board- to-
Board header). SR-SOM-MX6 headers are fixed, the final mating height is determined by
carrier implementation.
Supported Interfaces
PCIe
The i.MX8 SOM supports two PCIe interfaces. The following figure describes the PCIe
interfaces.
IMX-8
PCIe-1
TX_M/P
RX_M/P
PCIe-1 REF_CLK
X
PCIe-2
TX_M/P
RX_M/P
PCIe-2 REF_CLK
CLK2
13
The PCIe main features are:
• On board clock buffer sources all PCIe interfaces, on SOM and on Carrier.
• The IMX-8 CLK2_P/N clock output feeds the PCIe clock buffer.
• PCIe-1 can be used by the WI-FI module on the SOM or other module on the carrier. It is an
assembly option.
• 1.5 / 2.5 / 3.0 / 5.0 / 6.0 Gbps Serializer / Deserializer.
• Compliant with PCI Express Base Specification 2.1.
• Supports Spread Spectrum Clocking in Transmitter and Receiver.
• x1 Gen2 lane.
• The PCIe TX signals are DC coupled by capacitors.
• The clock are HSTL compatible, no decoupling capacitors.
USB 3.0
The i.MX8 supports two USB 3.0 interfaces. The following figure describes the USB
interfaces.
C
o
n
n
e
c
RX_P/N
t
DP/DN
o
r
The USB main features are:
• USB 1 and USB 2 are directly connected to the connectors (No HUB).
• The TX signals are DC coupled by capacitors.
• Complies with USB specification rev 3.0 (xHCI compatible).
• USB dual-role operation and can be configured as host or device.
• Super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low speed
(1.5 Mbit/s) operations.
• Supports four programmable, bidirectional USB endpoints.
• OTG (on-the-go) 2.0 compliant, which includes both device and host capability. Super-speed
operation is not supported when OTG is enabled.
• The USB 3.0 module operates in following modes:
IMX-8
USB1
TX_P/N
RX_P/N
DP/DN
USB1 VBUS
USB1 ID
USB2
TX_P/N
USB2 VBUS
14
o
Host Mode: SS/HS/FS/LS
o
Device Mode: SS/HS/FS
o
OTG: HS/FS/LS.
• Power control signal are not part of the USB module, any available GPIO can be used.
MIPI CSI
The following figure describes the CSI interface.
CSI_LANE
CSI_LANE
CSI_LANE
CSI_LANE
CSI_CL
• i.MX8 MIPI CSI channel 1.
• Implements all three CSI-2 MIPI layers.
• Scalable data lane support, 1 to 4 Data Lanes.
• Supports high speed mode (80Mbps - 1.5Gbps) per lane, providing
4K@30fpscapability for the 4 lanes.
• Virtual Channel support.
MIPI DSI
The following figure described the DSI interface.
IMX-8
DSI_LANE0
C
o
DSI_LANE1
n
DSI_LANE2
n
DSI DSI_LANE3
DSI_CLK
e
c
t
o
r
The DSI main features are:
• Implements all three DSI Layers.
• Support for Command and Video Modes.
IMX-8
CSI 1
C
o
n
n
e
c
t
o
r
15
C
o
n
n
e
c
t
o
r
• Host Version.
• Scalable data lane support, 1 to 4 Data Lanes. (Optional bidirectional support on lane 0).
• Support for all DSI data types and formats.
• Virtual Channel support.
• MIPI Alliance Specification for Display Serial Interface Version 1.1 compliant.
Audio
The i.MX8 SOM supports up to three Audio channels, SAI1, SAI2 and SAI3. The following figure
describes the audio interface.
RXD, TXD, T/RXC, T/RXFS, MCL
RXD, TXD, T/RXC, T/RXFS, MCLK
SPDIF OUT
The Audio main features are:
• SAI1 supports 8TX and 8 RX channels.
• SAI2 and SAI3 supports RX and TX,
• SPDIF Out.
• Transmitter with independent bit clock and frame sync supporting 1 data line.
• Receiver with independent bit clock and frame sync supporting 1 data line.
• Each data line can support a maximum Frame size of 32 words.
For more details check the i.MX8 datasheet and AN.
Please Note: SAI1 signals are used as boot configuration during POR.
IMX-8 SAI1
SAI2
SAI3
SPDIF
16
HDMI
The i.MX8 supports the HDMI interface including the signal termination. The following figure
describes the HDMI interface.
The HDMI main features are:
• On board pull-up termination to support HDMI levels.
• HDMI HPD support 5V level,
• HDMI DDC doesn’t support PU, need to support on carrier board.
• Up to 4Kp60 video/graphics display over HDMI 2.0a with HDCP 2.2 encryption and audio
formats including Dolby Digital, DTS, TrueHD, LPCM.
For more details check the i.MX8 datasheet.
Please Note: to support DPI, the pull-Up termination resistors are not
assembled.
17
UART
The i.MX8 SOM can support up to 4 UART interfaces. The following figure describes the UART
interfaces.
RX, TX (TerminaL
RX, TX,CTS, RT
RX, T
RX, TX Resistor4 - RX, T
Assembly
Option 2 – CTS, RTS
BT 5
MODULE
The UART interfaces main features are:
• UART 1 supports TX and RX. Can be used as debug terminal.
• UART 2 supports TX, RX, CTS and RTS. When using the RTS and CTS signals UART 4 is not
available.
• UART 3 Supports TX, RX, CTS and RTS.
• UART 4 support TX and RX. It has an assembly options:
o
On SOM BT module.
o
Free UART on carrier board.
• High-speed TIA/EIA-232-F compatible, up to Mbit/s.
• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection).
• 7 or 8 data bits for RS-232 characters, or 9 bit RS-485 format.
• Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B)
signals.
• RS-485 driver direction control via CTS_B signal.
• Auto baud rate detection (up to 115.2 Kbit/s).
• DCE/DTE capability.
For more information check the i.MX8 datasheet.
IMX-8 UART 1
UART 3
UART 2
UART 4
C
o
n
n
e
c
t
o
r
18
eSPI
The i.MX8 SOM supports an eSPI interface. The following figure describes the eSPI
interface.
nSS0, MOSI, MISO, CLK
• i.MX8’s eSPI channel 2.
• Single chip select nSS0.
• Master/Slave configurable.
• Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable.
Please Note: eSPI channel 1 is not available as default configuration. The
signals supporting channel 1 are available as GPIO.
I2C
i. MX8 supports up to four I2c Interfaces. The following figure describes the I2C interfaces.
EEPROM
PMIC
1K Camera
FPC
IMX-8 0x50
I2C1
I2C2
I2C3
The I2C main features are:
• I2C-1 is used only on the SOM. It is connected to the SOM EEPROM, PMIC and camera
FPC connector.
• I2C-2 and I2C-3 are available on the connector by default.
• I2C-4 is not available as default configuration; it signals are available as GPIO.
• Multimaster operation.
• Software programmability for one of 64 different serial clock frequencies.
IMX-8
eSPI 2
C
o
n
n
e
c
t
o
r
19
• In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.
• In Fast mode, data transfer rates up to 400 kbits/s can be achieved.
For more details check the i.MX8 datasheet.
uSD
The uSD supports the following features:
• i.MX8 uSDHC-1.
• Implements 4 data bits.
• Support SD/SDIO standard, up to version 3.0.
• Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR
mode using 4 parallel data lines.
• 1.8V or 3.3V support using SD2_VSELECT signal.
20
Connector’s Signal Description
J5001
PIN
PWR
Main
GPIO
PIN
PWR
Main
GPIO
1
3V3
PMIC_ON
2
3
3V3
BOOT_MODE0
4
DSI_DN3
5
3V3
BOOT_MODE1
6
DSI_DP3
7
GND
GND
8
GND
GND
9
DSI_CKP
10
GND
GND
11
DSI_CKN
12
DSI_DN0
13
GND
GND
14
DSI_DP0
15
DSI_DN2
16
GND
GND
17
DSI_DP2
18
PCIE1_REF_CLKP_CN
19
GND
GND
20
PCIE1_REF_CLKN_CN
21
DSI_DN1
22
GND
GND
23
DSI_DP1
24
3V3
PCIE_nPME
gpio3.IO[5]
25
GND
GND
26
3V3
PCIe_nWAKE
gpio3.IO[12]
27
3V3
PWM1_OUT
28
3V3
USB1_SS_SEL
gpio3.IO[15]
29
3V3
UART3_TXD
gpio5.IO[27]
30
GND
GND
31
3V3
UART3_RXD
gpio5.IO[26]
32
PCIE1_TXP_C
33
GND
GND
34
PCIE1_TXN_C
35
36
GND
GND
37
3V3
UART3_CTS
gpio5.IO[9]
38
PCIE1_RXP_C
39
3V3
UART3_RTS
gpio5.IO[10]
40
PCIE1_RXN_C
41
3V3
SAI1_TXD2 (BT_CFG10)
gpio4.IO[14]
42
GND
GND
43
3V3
DSI_TS_nINT
gpio5.IO[7]
44
3V3
UART2_RXD
gpio5.IO[24]
45
46
3V3
UART2_TXD
gpio5.IO[25]
47
GND
GND
48
3V3
UART2_CTS
uart4.RX/gpio5.IO[28]
49
50
3V3
UART2_RTS
uart4.TX/gpio5.IO[29]
51
SAI1_TXD4 (BT_CFG12)
gpio4.IO[16]
52
GND
GND
53
WIFI_DP
54
CSI_P1_DN0
55
WIFI_DN
56
CSI_P1_DP0
57
GND
GND
58
GND
GND
59
CSI_P1_CKP
60
CSI_P1_DP2
61
CSI_P1_CKN
62
CSI_P1_DN2
63
GND
GND
64
GND
GND
65
CSI_P1_DP3
66
CSI_P1_DP1
67
CSI_P1_DN3
68
CSI_P1_DN1
69
GND
GND
70
GND
GND
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