MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor ix
Figures
Figure Page
Number Title Number
es
1-1 MC92604 Simplified Block Diagram ..................................................................................... 1-3
1-2 MC92604 Block Diagram....................................................................................................... 1-4
1-3 PHY and Backplane Applications........................................................................................... 1-5
2-1 MC92604 Transmitter Block Diagram .................................................................................. 2-2
2-2 Configuration Register.......................................................................................................... 2-10
3-1 MC92604 Receiver Block Diagram........................................................................................ 3-2
4-1 Control Register (MDIO RA 0) .............................................................................................. 4-3
4-2 Status Register (MDIO RA 1)................................................................................................. 4-4
4-3 PHY Identifier Registers (MDIO RA 2 and 3) ....................................................................... 4-5
4-4 Auto-Negotiation (AN) Advertisement Register (MDIO RA 4) ............................................ 4-6
4-5 AN Link Partner Ability Register (MDIO RA 5) ................................................................... 4-7
4-6 AN Expansion Register (MDIO RA 6)................................................................................... 4-8
4-7 Extended Status Register (MDIO RA 15)............................................................................... 4-8
4-8 Permanent Configuration Control Register (MDIO RA 16)................................................... 4-9
4-9 Channel Configuration and Status Register (MDIO RA 17) ................................................ 4-11
4-10 BERT Error Counter Register (MDIO RA 18) ..................................................................... 4-12
5-1 PLL Power Supply Filter Circuits........................................................................................... 5-6
6-1 Instruction Register ................................................................................................................. 6-2
6-2 Device Identification Register ................................................................................................ 6-3
7-1 Transmitter Interface, Non-DDR Timing Diagram................................................................. 7-4
7-2 Transmitter Interface, DDR Timing Diagram......................................................................... 7-5
7-3 Receiver, Non-DDR Timing Diagram (TBIE = Low or COMPAT = Low) ........................... 7-7
7-4 Receiver, Non-DDR Timing Diagram (TBIE = High and COMPAT = High)........................ 7-8
7-5 Receiver, DDR Timing Diagram (TBIE = Low or COMPAT = Low).................................... 7-9
7-6 Receiver, DDR Timing Diagram (TBIE = High and COMPAT = High).............................. 7-10
7-7 Reference Clock Timing Diagram ........................................................................................ 7-11
7-8 Link Differential Output Timing Diagram............................................................................ 7-12
7-9 Link Differential Input Timing Diagram .............................................................................. 7-12
7-10 MDIO Interface Timing Diagram ......................................................................................... 7-13
7-11 JTAG I/O Timing Diagram ................................................................................................... 7-14
8-1 196 MAPBGA Nomenclature................................................................................................. 8-2
8-2 196 MAPBGA Dimensions .................................................................................................... 8-3
8-3 MC92604 Package Ball Mapping ........................................................................................... 8-4
A-1 Freescale Part Number Key ................................................................................................... A-1
B-1 Unencoded Transmission Character Bit Ordering ..................................................................B-1
B-2 Encoded Transmission Character Bit Ordering ......................................................................B-1
B-3 Character Transmission...........................................................................................................B-2