Integral INMPCIE64G50MXB Datasheet

2

Features:

 Standard ATA/IDE Bus Interface

- 512 Bytes / Sector

- ATA command set compatible

- Selectable Master/Slave Setting

 Capacities

- Integral Z Series (MLC) 16GB, 32GB, 64GB

- Integral E Series (SLC) 16GB

 Data Transfer mode

- Support Data Transfer up to PIO mode 6

- Support Data Transfer up to Multiword DMA mode 2

- Support Data Transfer up to Ultra DMA mode 5

 Performance

Integral Z Series (MLC Flash)

 Sustain Read Speed up to 35MB/s

 Sustain Write Speed up to 15MB/s

Integral E Series (SLC Flash)

 Sustain Read Speed up to 45MB/s

 Sustain Write Speed up to 35MB/s

 Temperature Ranges

- 0

0

C to 70

0

C for operating

- -25

0

C to 85

0

C for storage

 Operating Voltage

- 3.3V

 Intelligent ATA/IDE Module

- Built-in Embedded Flash File System

- Implements dynamic wear-leveling algorithms and static wear-leveling algorithms to increase

endurance of flash media

- Built-in ECC corrects up to 12 random bits error per 512 bytes

 RoHS Compliance

3

TABLE OF CONTENTS

1.0 BLOCK DIAGRAM .................................................................................................................... 4

1.1 CAPACITY SPECIFICATION .................................................................................................... 4

2.0 SPECIFICATION ........................................................................................................................ 5

2.1 PIN ASSIGNMENTS ................................................................................................................. 5

2.2 PIN DESCRIPTION.................................................................................................................. 6

3.0 ELECTRICAL CHARACTERISTICS ...................................................................................... 8

3.1 ABSOLUTE MAXIMUM RATING ............................................................................................. 8

3.2 DC CHARACTERISTICS OF 5.0V I/O CELLS(HOST INTERFACE) ......................................... 8

3.3 AC CHARACTERISTICS ......................................................................................................... 9

3.3.1 PIO Data Transfer .................................................................................................. 9

3.3.2 Multiword DMA Data Transfer .......................................................................... 12

3.3.3 Ultra DMA Data Transfer .................................................................................... 15

3.4 POWER MANAGEMENT ....................................................................................................... 21

4.0 SOFTWARE INTERFACE ....................................................................................................... 21

4.1 ATA TASK FILE REGISTERS ............................................................................................... 21

4.2 COMMAND SETS .................................................................................................................. 22

4.3 IDENTIFY DRIVE INFORMATION ......................................................................................... 23

5.0 PHYSICAL DIMENSION ......................................................................................................... 25

6.0 WEIGHT .................................................................................................................................... 25

4

1.0 Block Diagram

1.1 Capacity Specification

Density

Total Bytes

Cylinders

Heads

Sectors

16GB

16,441,270,272

16383

16

63

32GB

32,279,224,320

16383

16

63

64GB

pls call

16383

16

63

5

2.0 Specification

2.1 Pin Assignments

Pin Number

Signal

Pin Number

Signal

1

HD0

2

HD15

3

HD1

4

GND

5

HD2

6

HD14

7

HD3

8

HD13

9

GND

10

HD12

11

HD4

12

HD11

13

HD5

14

HD10

15

GND

16

HD9

17

HD6

18

GND

19

HD7

20

HD8

21

GND

22

nHRESET

23

NC

24

nHIOW

25

NC

26

CSEL

27

GND

28

nHIOR

6

29

GND

30

nDMACK

31

NC

32

DMARQ

33

NC

34

GND

35

GND

36

NC

37

HA0

38

NC

39

HA1

40

GND

41

HA2

42

IORDY

43

nIOIS16

44

INTRQ

45

nPDIAG

46

nHCS0

47

3V3

48

nHCS1

49

3V3

50

GND

51

3V3

52

nDASP

2.2 Pin Description

Pin No.

Signal

I/O*

Description

22

-RESET

I

Hardware reset signal from the host

1, 3, 5, 7, 11, 13, 17,

19, 20, 16, 14, 12,

10, 8, 6, 2

HD0~HD15(Device Data)

I/O

16-bit bi-direction Data Bus. DD(7:0) are

used for 8-bit register transfers.

32

DMARQ(DMA Request)

O

For DMA data transfers. Device will

assert DMARQ when the device is ready

to transfer data to or from the host.

24

-DIOW(I/O Write)

I

This is the strobe signal used by the host

to write to the device register or Data

port

STOP(Stop UDMA Burst)

The host assert this signal during an

UDMA burst to stop the DMA burst

42

IORDY(I/O channel ready)

O

This signal is used to temporarily stop

the host register access (read or write)

when the device is not ready to respond

to a data transfer request.

DDMARDY(UDMA ready)

The device will assert this signal to

indicate that the device is ready to

receive UDMA data-out burst.

7

DSTROBE(UDMA data

strobe)

When UDMA mode DMA Read is active,

this signal is the data-in strobe generated

by the device.

26

CSEL(Cable select)

I

This pin is used to configure this device

as Device 0 or Device 1.

30

-DMACK(DMA

acknowledge)

I

This signal is used by the host in respond

to DMARQ to initiate DMA transfer.

44

INTRQ(Interrupt)

O

When this device is selected, this signal is

the active high Interrupt Request to the

host

43

IOIS16

O

During PIO transfer mode0,1or 2, this

pin indicates to the host the 16-bit data

port has been addressed and the device is

prepared to send or receive a 16-bit data

word.

When transferring in DMA mode, the

host must use a 16-bit DMA channel and

this signal will not be asserted.

37, 39, 41

HA0~HA2(Device Address)

I

This is 3-bit binary coded Address Bus.

45

-PDIAG(Passed diagnostics)

I/O

This signal will be asserted by Device 1 to

indicate to Device 0 that Device 1 has

completed diagnostics,

-CBLID(Cable assembly

type identify)

46,48

-CS0, -CS1(Chip select)

I

These signals are used to select the

Command Block and Control Block

registers. When –DMACK is asserted,

-Cs0 and –Cs1 shall be negated and

transfers shall be 16-bit wide.

52

-DASP(Device active, Device

1 present)

I/O

During the reset protocol, -DASP shall be

asserted by Device 1 to indicate that the

device is present.

47, 49, 51

VCC

P

Power supply

9, 15, 21, 27, 29, 35,

4, 18, 26, 34, 40, 50

GND

--

Ground.

*Note:

“I” An input from the host system to the device.

8

“O” An output from the device to the host system.

“I/O” An input/output(bi-direction) common.

“P” Power supply.

3.0 Electrical Characteristics

3.1 Absolute Maximum Rating

Item

Symbol

Parameter

MIN

MAX

Unit

1

V

DD

-V

SS

DC Power Supply

-0.3

+5.5

V

2

VIN

Input Voltage

Vss-0.3

V

DD

+0.3

V

3

Ta

Operating Temperature

0

+70

0

C

4

Tst

Storage Temperature

-25

+85

0

C

Parameter

Symbol

MIN

TYP

MAX

Unit

V

DD

Voltage

V

DD

3.0

3.3

3.6

V

4.5

5.0

5.5

V

3.2 DC Characteristics of 5.0V I/O Cells(Host Interface)

Symbol

Parameter

Conditions

MIN

TYP

MAX

Unit

Vil

Input Low Voltage

TTL(5V)

--

0.85

V

Vih

Input High Voltage

1.25

--

V

Vil

Input Low Voltage

TTL(3.3V)

--

1.05

V

Vih

Input High Voltage

1.75

--

V

Vol

Output Low Voltage

|Iol| = 4~32 mA

--

0.4

V

Voh

Output High Voltage

|Ioh|= 4~32 mA

2.4

--

V

Iin

Input Leakage Current

No pull-up or pull

down

-10

±1

10

μA

Ioz

Tri-state Output Leakage

Current

-10

±1

10

μA

9

3.3 AC Characteristics

3.3.1 PIO Data Transfer

10

PIO timing parameters

Mode 0

ns

Mode 1

ns

Mode2

ns

Mode 3

ns

Mode 4

ns

Note

t

0

Cycle time (min)

600

383

240

180

120

1,4

t

1

Address valid to

DIOR-/DIOW- setup (min)

70

50

30

25

t

2

DIOR-/DIOW- (min)

165

125

100

80

70

1

t

2i

DIOR-/DIOW- recovery time

(min)

--

70

25

1

t

3

DIOW- data setup (min)

60

45

30

20

t

4

DIOW- data hold (min)

30

20

15

10

t

5

DIOR- data setup (min)

50

35

20

t

6

DIOR- data hold (min)

5

t

6z

DIOR- data tristate (max)

30

2

t

9

DIOR-/DIOW- to address

valid hold (min)

20

15

10

t

RD

Read Data Valid to IORDY

active (if IORDY initially low

after t

A

) (min)

0

t

A

IORDY Setup time

35

3

t

B

IORDY Pulse Width (max)

1250

t

C

IORDY assertion to release

(max)

5

Notes-

1. t

0

is minimum total cycle, t

2

is minimum DIOR-/DIOW- assertion time, and t

2i

is the minimum

DIOR-/DIOW- negation time. A host implementation shall lengthen t

2i

to ensure that t

0

is equal to or

greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation

shall support any length host implementation.

2. This parameter specifies the time from the negation edge of DIOR- to the time that the data is

released by the device.

3. The delay from the activation of FIOR- or DIOW- until the state of IORDY is first sampled. If

IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete. If

the device is not driving IORDY negated at the t

A

after the activation of DIOR-

or DIOW-, that t

5

shall be met and t

RD

is not applicable. If the device is driving IORDY

11

negated at the time t

A

after the activation of DIOR- or DIOW-, then tRD shall be met and t

5

is not

applicable.

4. Mode may be selected at the highest mode for the device if CS(1:0) and DA(2:0) do not change

between read or write cycle or selects at the highest mode supported by the slowest device if CS(1:0)

and DA(2:0) do change between read or write cycles.

12

3.3.2 Multiword DMA Data Transfer

(Initialing a Multiword DMA data burst)

(Sustaining a Multiword DMA data burst)

13

(Device terminating a Multiword DMA data burst)

(Host terminating a Multiword DMA data burst)

14

Multiword DMA timing parameters

Mode 0

ns

Mode 1

ns

Mode2

ns

Note

t

0

Cycle time (min)

480

150

120

See note

t

D

DIOR-/DIOW- asserted pulse width (min)

215

80

70

See note

t

E

DIOR- data access (max)

150

60

50

t

F

DIOR- data hold (min)

5

t

G

DIOR-/DIOW- data setup (min)

100

30

20

t

H

DIOW- data hold (min)

20

15

10

t

I

DMACK to DIOR-/DIOW- setup (min)

0

t

J

DIOR-/DIOW- to DMACK hold (min)

20

5

t

KR

DIOR- negated pulse width (min)

50

25

See note

t

KW

DIOW- negated pulse width (min)

215

50

25

See note

t

LR

DIOR- to DMACK delay (max)

120

40

35

t

LW

DIOW- to DMACK delay (max)

40

35

t

M

CS(1:0) valid to DIOR-/DIOW- (min)

50

30

25

t

N

CS(1:0) hold (min)

15

10

t

Z

DMACK- to read data released (max)

20

25

Notes- t

0

is the minimum total cycle. t

D

is the minimum DIOR-/DIOW- assertion time, and t

K

(t

KR

or t

KW

,

as appropriate) is the minimum DIOR-/DIOW- negation time. A host shall lengthen t

D

and/or t

K

to

ensure that t

0

is equal to the value reported in the devices IDENTIFY DEVICE data.

15

3.3.3 Ultra DMA Data Transfer

Ultra DMA data burst timing requirements

16

Ultra DMA data burst timing descriptions

17

(Initialing an Ultra DMA data-in burst)

(Sustained Ultra DMA data-in burst)

18

(Device terminating an Ultra DMA data-in burst)

(Host terminating an Ultra DMA data-in burst)

19

(Initialing an Ultra DMA data-out data burst)

(Sustained Ultra DMA data-out burst)

20

(Host terminating an Ultra DMA data-out burst)

(Device terminating an Ultra DMA data-out burst)

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