www.ams.com Revision 1.0 / 12.4.2013 page 1/27
AS3709
uPMIC with 5 DCDC and 2 LDOs
AN02-Evaluation Kit Description
Application Note:
AS3709
-
AN02
-
Evaluation Kit Description
AS3709-AN02-Evaluation Kit Description
www.ams.com Revision 1.0 / 12.4.2013 page 2/27
Table of Contents
1
General Description ............................................................................................................. 3
1.1
Kit Content ........................................................................................................................... 4
2
Getting Started ..................................................................................................................... 5
3
Hardware Description........................................................................................................... 6
4
Software Description ............................................................................................................ 8
4.1
LDO ...................................................................................................................................... 9
4.2
DCDC ................................................................................................................................. 10
4.3
Housekeeping .................................................................................................................... 12
4.4
OTP_Startup ...................................................................................................................... 14
5
Board Schematics; Layout and BOM ................................................................................. 16
5.1
Schematics of AS3709 Evaluation Board .......................................................................... 17
5.2
Board Layout of AS3709 Evaluation Board ....................................................................... 21
5.3
BOM ................................................................................................................................... 25
6
Ordering Information .......................................................................................................... 26
Revision History
Revision Date Owner Description
1.0 12.4.2013 skre Initial release
AS3709-AN02-Evaluation Kit Description
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1 General Description
This document describes the AS3709 Evaluation Kit.
The AS3709 is an ultra compact µPMIC containing 5 high-efficiency, constant-frequency
synchronous buck converters. In addition 2 universal IO LDOs are available for lower current power
rails. The wide input voltage range (2.7V to 5.5V), automatic power-save mode and minimal
external component requirements make the AS3709 perfect for any single Li-Ion battery-powered or
fixed 3.3V/5V supply application.
The Evaluation Kit has to be externally supplied. The graphical user interface (GUI) runs on PC
running Windows 7 and allows the user to control the AS3709. Use the enclosed USB cable to
connect the PC with the Evaluation Board. A µC is directly located onboard which allows to control
the board without any external controllers (e.g. ams USB box).
AS3709-AN02-Evaluation Kit Description
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1.1 Kit Content
The AS3709 Evaluation Kit includes all items listed in Figure 1: Kit Content.
Figure 1: Kit Content
Label Item Comment
1 Battery 3.6VDC
2 Evaluation Board v1.2 AS3709 (32-pin QFN 4x4mm)
3 USB flash drive Includes application note and software
4 USB connection cable -
3
2
1
4
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2 Getting Started
Drive the AS3709 Evaluation Kit only with the recommended settings and values as described in
the datasheet. Please check www.ams.com for the latest version.
For a detailed description of the Kit please read sections 3-5 of this document.
− Check all Jumpers for the default setting (factory-set) shown in picture 2, Figure 1: Kit
Content.
− Install the GUI from the attached USB flash drive
− Establish the connection between PC and Evaluation Board via the enclosed USB cable
− Connect the battery to VSUP (BU1) and GND (BU2) which is included in this kit. Check first if
the battery is loaded (appr. 3.6 VDC).
− Start the GUI
− First of all please perform a firmware upgrade on the Evaluation Board in order to ensure a
proper communication to the GUI! The appropriate firmware file for the Evaluation Board comes
with the GUI software and can be found in the GUI installation directory (default: C:\Program
Files (x86)\ams\AS3709 Evaluation Software).
o Open “Help” in the top command bar
o Press “Firmware update”
o Double click the “usb2i2c.bin” file to initiate the procedure
Never disconnect the battery or interrupt the connection to the PC during the update!!!
− If the AS3709 Evaluation Board is supplied and connected properly to the PC and the
appropriate firmware file is installed, the fields at the right bottom corner of the GUI becomes
green
For further information do not hesitate to contact us.
AS3709-AN02-Evaluation Kit Description
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3 Hardware Description
The AS3709 Evaluation Board has to be powered via an external power supply or battery. The
AS3709 can be controlled with the onboard µC or any other controller board via 10 pole connector
which enables fast code debugging. Furthermore the Evaluation Board includes 2 pieces AS3709,
U1 and U2 for supporting 5 x 1A Mode and 2 & 3 Mode at the same time. This benefit enables the
evaluation in 1A, 2A and 3A mode without doing any hardware change on the board. U1 is
hardware/software set to 5 x 1A Mode and U2 is hardware/software set to 2A & 3A Mode.
On U1 it is also possible to customize the mode setting, combining of SD1 + SD2 or SD3 + SD4 or
SD4 +SD5 or SD3 +SD4 + SD5. Therefore a hardware and software change is necessary and the
hardware-based setting must be in accordance with the software setting. The configuration settings
for U1 can be found in schematic page 1.
Figure 2: Evaluation Board Overview
C
A
E
B
D
F
AS3709-AN02-Evaluation Kit Description
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Label Name Designator Description Info
A USB
connector
U5 USB Mini B Interface to the PC
B Controller
interface
J11 Controller
interface
Can be connected to an external
controller (e.g. ams USB box)
C VSUP, GND BU1,BU2 Supply Voltage Range: 2.7V to 5.5V
D AS3709 U1 PMU 5 x 1A Mode
E SCLK, SDA J20, J21 I2C bus Toggle between the chips U1 and U2.
Only one chip can be controlled at the
same time.
The jumper-setting for SDA and SCLK
has to be the same either U1 or U2.
F AS3709 U2 PMU 2A & 3A Mode
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4 Software Description
The graphical user interface (GUI) is used to control the AS3709 Evaluation board.
Start the GUI and setup the Hardware according chapter 2, Getting Started.
Make sure hardware is recognized and indicators on the bottom right side of the GUI are green
colored.
Figure 3: AS3709 Evaluation Software
AS3709-AN02-Evaluation Kit Description
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4.1 LDO
The AS3709 features 2 LDO’s.
Figure 4: LDO Settings
Label
Name Comment
A LDO on Enabling / Disabling of LDOs
B Vout Regulator Output voltage
C Current Limit Current Limit setting
D GPIO Control GPIO controlling of LDOs
A
B
C
D
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4.2 DCDC
The AS3709 features 5 DCDC step down regulators (2 - 4MHz).
Figure 5: DCDC settings
Label
Name Comment
A SD on Enabling / Disabling of DCDCs
B Vout Regulator Output voltage
C Frequency Selecting of SD frequency between 2MHz, 3MHz, 4MHz
D Mode Mode selection
E GPIO Control GPIO controlling of DCDCs
F Low voltage This bit is set in case Vout drops below low voltage threshold (-5%)
(1msec debounce time default)
G DVM (Dynamic
Voltage
Can be applied to the regulator SD1, SD2, SD3 and SD5 but only for
one at a time. By changing the output voltage of a regulator which has
A
B
C
D
E
F
H
G
I
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Label
Name Comment
Management) DVM enabled, the voltage is decreased/increased by single 12.5mV
steps.
0 : 0 µsec, immediate change (no DVM)
1 : 4 µsec time delay between steps
2 : 8 µsec time delay between steps
3 : 16 µsec time delay between steps
H SD1+SD2 Mode SD1 + SD2 (SD2 slave) can be combined to deliver up to 2A output
current. The hardware-based setting must be in accordance with the
software setting.
I SD3 + SD4 Mode
SD4 + SD5 Mode
Combining of SD3 + SD4 or SD4 + SD5 in order to deliver up to 2A
output current or combining of SD3 + SD4 + SD5 in order to deliver up
to 3A output current. The hardware-based setting must be in
accordance with the software setting.
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4.3 Housekeeping
Figure 6: Housekeeping settings
Label
Name Comment
A GPIOs
• Setting of GPIOs to normal or inverted mode
• “GPIO x HIGH” determines the output signal on GPIOx pin
when selected as output source
• “GPIO x HIGH” indicates the logic level on GPIOx pin when
configured as digital input pin
• Choosing one out of 8 GPIO special functions
• Choosing one out of 8 GPIO modes
B Stand_by /
Voltage Control
per GPIO
• Assign GPIO1 or/and GPIO2 to the available controller inputs
• Select which regulator gets controlled by the respective
controller
• Set the regulator output voltage when the respective controller
goes high
• Setting of “sd_freq”
0 : 2MHz if sdx_fsel=0, 3MHz if sdx_fsel=1
1 : 3MHz if sdx_fsel=0, 4MHz if sd1_fsel=1
C Internal
References
• Selection of internal CLK frequency
• Low power mode: all specifications except noise parameters
A
B
C
D
F
G
E
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Label
Name Comment
are still valid. Iq reduced by approx. 30µA
D Stand-by
Regulator Enable
• Choose which regulator should be enabled during stand-by
mode
• Setting of stand-by delay (0ms, 8ms, 16ms or 32ms)
• Disable reset signal (pin XRES) in stand-by mode
• Go into stand-by mode
E Temperature
Supervision
• Activation of Temperature Supervision
• Detection if 140°C threshold has been reached (flag “140°C
reached”)
• The flag “140°C reached” has to be reset with the “Reset
Overtemp 140” button
F Reset / Power
Off
• Selection of reset threshold for falling VSUP (“Reset Voltage
Fall”)
• Set Reset Time, after the last regulator has started
• Enable RESET with ON key press for 4s/8s
• Enter power off mode if low VSUP is detected (“Power off at
supply low”)
0: If low VSUP is detected, VSUP is continuously monitored
and chip startup initiated if VSUP is above ResVoltRise
1: If low VSUP is detected, enter power off mode
• Disable “Supply Reset enable”: sets a RESET if VSUP < 2.7V
enable “Supply Reset enable”: sets a RESET if VSUP < “Reset
Voltage Fall”
• With “reslevel_5V” the reset level can be set to higher values
• Enabling “Fast reset enable” sets the Reset Voltage Fall
(ResVoltFall) debounce time from 3msec to 4µsec
• “Force Reset” and “Power Off” button
• Detection of reset reason
G Interrupt
• Setting, which event should cause an interrupt
• Detection, which event has caused an interrupt
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4.4 OTP_Startup
Figure 7: OTP_Startup settings
Label
Name Comment
A Timeslots
• 6 timeslots
• For each timeslot one of the available regulators or available
GPIOs can be defined
LDO settings: voltage and current limit
DCDC settings: voltage and frequency (“sdx_frequ”)
0 : 2MHz if sdx_fsel=0, 3MHz if sdx_fsel=1
1 : 3MHz if sdx_fsel=0, 4MHz if sd1_fsel=1
GPIO settings: normal or inverted, GPIO special functions and
GPIO modes
• Beginning with timeslot 2 a delay (see “Delay Interval” in
section B, Figure 7: OTP_Startup settings) can be inserted
with respect to the previous timeslot (sequential startup)
B General Settings
• Selection of “Delay Interval” (no delay, 1ms or 4ms)
• Set “Reset time”, after the last regulator has been started
• Selection of reset threshold for rising VSUP (“Reset Voltage
Rise”)
A
B
C
D
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Label
Name Comment
•
Enabling of fast regulation mode for all DCDC regulators
(“SD1_5 fast”)
• Choosing of SD frequency range, 2/3MHz or 3/4MHz (“SD1_5
fsel”)
• Define which DCDC regulator should work in slave mode
• GPIO1 and GPIO2 can be defined as input
• Enter power off mode if low VSUP is detected (“pwr_off
vsuplow”, for more details see section F, Figure 6:
Housekeeping settings)
• With “reslevel_5V” the reset level can be set to higher values
• Set the on key reset delay time (“on_reset Delay”)
0: 8 sec (“if onkey_reset”=1)
• 1: 4 sec (“if onkey_reset”=1)
• “Auto off” defines startup behaviour at first VSUP connection
0: Startup of chip if VSUP>ResVoltRise
1 : Enter power off mode (Startup with ON key)
• With “Reset to Default” button the bits can be reset to their
default value
C GPIO Selector GPIO1 and GPIO2 can be defined as controller for the DCDCs
D OTP
• Loading of existing OTP startup sequence
• Saving OTP startup sequence as a .txt file
• Reading the OTP registers of the chip
• Writing into the OTP registers of the chip
• Testing the startup just from the OTP
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5 Board Schematics; Layout and BOM
The AS3709 Evaluation Board is a 4-layer FR4 board. The main components are the AS3709
together with some active components, passive components, several test points and connectors.
Figure 8: AS3709 PCB Layer Stack up
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5.1 Schematics of AS3709 Evaluation Board
Figure 9: Schematic page 1
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Size
Date
Project Title
Revision
Sheet ofOriginator SKRE
AS3709 Evaluation Board
A4
1.2
06.05.2013
7
3
C4
10µF
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
VSUP
VSUP
VSUP
VSUP
VSUP
C2
2.2µF
GND GND
VIN_LDO2(U1)
GND GND
VIN_LDO1(U1)
GND
GPIO1(U1)
GPIO2(U1)
GND
LX_SD2
LX_SD3
LX_SD4
LX_SD5
FB_SD1
FB_SD2
FB_SD3
FB_SD4
FB_SD5
V2_5(U1)
LDO2(U1)
LDO1(U1)
GPIO1(U1)
GPIO2(U1)
SCLK(U1)
SDA(U1)
XRES(U1)
SCLK(U1)
XRES(U1)
ON(U1)
SDA(U1)
R1
1M
VSUP
GND
V2_5(U1)
1
TP4
SD1(U1)
1
TP5
SD2(U1)
1
TP8
SD3(U1)
1
TP18
SD4(U1)
1
TP17
SD5(U1)
1
TP1
LDO2(U1)
1
TP2
LDO1(U1)
1
TP9
V2_5(U1)
1
TP10
GPIO1(U1)
1
TP13
GPIO2(U1)
1
TP15
XRES(U1)
1
TP3
VSUP
1
TP14
VSUP
V2_5(U1)
GPIO1(U1)
GPIO2(U1)
XRES(U1)
R11
10k
R12
1M
GND
LX_SD1
FB_SD1
LX_SD2
FB_SD2
LX_SD3
FB_SD3
LX_SD4
FB_SD4
LX_SD5
FB_SD5
R13
0R
R14
0R
R15
0R
GND
GND
GND
LX_SD1 LX_SD2 FB_SD1
LX_SD3 LX_SD4
LX_SD5
LX_SD1
FB_SD3
2A or 3A mode
3A: Assemble R13, R14, C21 a. C22. FB_SD4
and FB_SD5 must be connected to GND (short
C10 and C12). Remove L4, L5
2A: Assemble R13 a. C21. FB_SD4
must be connected to GND (short C10). Remove L4
2A mode
Assemble R15 a. C23. FB_SD2 must be
connected to GND (short C6). Remove L2
5 x 1A mode
LQM2HPN1R0MG0L
L1
1µH
LQM2HPN1R0MG0L
L2
1µH
LQM2HPN1R0MG0L
L3
1µH
LQM2HPN1R0MG0L
L4
1µH
LQM2HPN1R0MG0L
L5
1µH
V2_5(U1)
401-1426-1-ND
KMR211GLFS
S1
401-1426-1-ND
KMR211GLFS
S2
ON(U1)
LDO1
13
VIN_LDO1
14
FB_SD2
15
GNDSENSE
30
FB_SD5
31
PVSS_SD5
32
VIN_LDO2
11
FB_SD3
10
LDO2
12
VSUP_SD3
7
FB_SD4
6
LX_SD3
8
PVSS_SD4
5
VSUP_SD5
2
VSUP_SD4
3
LX_SD4
4
SCLK
24
SDA
25
VSUP_SD1
22
LX_SD1
21
GPIO2
28
XRES
27
ON
26
VSUP_SD2
18
FB_SD1
19
LX_SD2
17
PVSS_SD2
16
LDOs
DCDC SD 1-5
Logic & Control
AS3709
uPMIC
EP_VSS
33
GPIO1
29
LX_SD5
1
PVSS_SD3
9
PVSS_SD1
20
V2_5
23
AS3709-BQFT-00
U1
AS3709
1
TP21
ON(U1)
ON(U1)
C24
2.2µF
C3
2.2µF
C25
2.2µF
C1
2.2µF
C5
2.2µF
C8
2.2µF
C13
2.2µF
C11
2.2µF
C7
1µF
C6
10µF
C9
10µF
C10
10µF
C12
10µF
C23
10µF
C21
10µF
C22
10µF
Optional (n.m.)
Optional (n.m.)
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Figure 10: Schematic page 2
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Size
Date
Project Title
Revision
Sheet ofOriginator SKRE
AS3709 Evaluation BoardA4 1.2
06.05.2013
7
4
LDO1
13
VIN_LDO1
14
FB_SD2
15
GNDSENSE
30
FB_SD5
31
PVSS_SD5
32
VIN_LDO2
11
FB_SD3
10
LDO2
12
VSUP_SD3
7
FB_SD4
6
LX_SD3
8
PVSS_SD4
5
VSUP_SD5
2
VSUP_SD4
3
LX_SD4
4
SCLK
24
SDA
25
VSUP_SD1
22
LX_SD1
21
GPIO2
28
XRES
27
ON
26
VSUP_SD2
18
FB_SD1
19
LX_SD2
17
PVSS_SD2
16
LDOs
DCDC SD 1-5
Logic & Control
AS3709
uPMIC
EP_VSS
33
GPIO1
29
LX_SD5
1
PVSS_SD3
9
PVSS_SD1
20
V2_5
23
AS3709-BQFT-00
U2
AS3709
GND GND GND GND
VSUP VSUP
GND
GND
VSUP
GND
GND
SCLK(U2)
SDA(U2)
XRES(U2)
GPIO1(U2)
GPIO2(U2)
401-1426-1-ND
KMR211GLFS
S3
401-1426-1-ND
KMR211GLFS
S4
R3
1M
R4
1M
R5
10k
GND
V2_5(U2)
VSUP
GND
ON(U2)
cSD1/2(U2)
cSD3/4/5(U2)
XFL4020-102MEC
L7 1µH
VSUP
GND
GND
GND
V2_5(U2)
GND
1
TP24
V2_5(U2)
1
TP26
GPIO1(U2)
1
TP27
GPIO2(U2)
1
TP28
XRES(U2)
V2_5(U2)
GPIO1(U2)
GPIO2(U2)
XRES(U2)
LDO2(U2)
LDO1(U2)
1
TP22
LDO2(U2)
1
TP23
LDO1(U2)
V2_5(U2)
GPIO1(U2)
GPIO2(U2)
1
TP25
ON(U2)
ON(U2)
ON(U2)
XRES(U2)
SCLK(U2)
SDA(U2)
XFL3012-102MEB
L6
1µH
LX_SD1/2
LX_SD3/4/5
FB_SD1(U2)
FB_SD3(U2)
1
TP29
cSD1/2(U2)
1
TP30
cSD3/4/5(U2)
C34
2.2µF
C31
2.2µF
C32
2.2µF
C33
2.2µF
C39
2.2µF
C37
2.2µF
C27
2.2µF
C35
2.2µF
C36
2.2µF
C15
1µF
C26
10µF
C28
10µF
C29
10µF
C38
10µF
C30
10µF
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Figure 11: Schematic page 3
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Size
Date
Project Title
Revision
Sheet ofOriginator SKRE
AS3709 Evaluation BoardA4 1.2
06.05.2013
7
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J9
Stipline16
VSUP
VSUP
GND
FB_SD1
FB_SD5
GND
GND
GND
GPIO1(U1) GPIO2(U1)
V2_5(U1)
SCLK(U1)
XRES(U1)
SDA(U1)
ON(U1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J8
Stipline16
GND
VSUP
VSUP
GND
VSUP
GND
FB_SD2FB_SD3
FB_SD4
GND
VSUP GND
VIN_LDO2(U1) VIN_LDO1(U1)
LDO2(U1) LDO1(U1)
VSUP
GPIO1(U1)
GPIO2(U1)
475-2816-2-ND
D1
LED
475-2816-2-ND
D2
LED
R16
1k0
R17
1k0
GND
J6
GPIO1
J7
GPIO12
1
2 3
SI1304BDL-T1-E3
Q1
XRES(U2)
GND
VSUP
R6
1k0
475-2816-2-ND
D3
LED
J10
BU1
VSUP
BU2
GND
VSUP
GND
VBUS_5V VSUP
VSUP
R2
0R
R18
0R
VIN_LDO2(U1)
VIN_LDO1(U1)
1
2
J1
1
2
J2
1
2
3
J3
GND
1
2
3
J4
GND
1
2
3
J5
GND
GND
1
TP11
GND
1
TP12
GND
1
TP6
VBUS_5V
1
TP7
VSUP
1
2 3
SI1304BDL-T1-E3
Q2
XRES(U1)
GND
VSUP
R19
1k0
475-2816-2-ND
D8
LED
J22
GND
VSUP
1
2
3
J23
GND
1
2
3
J24
GND
1
2
3
J25
GND
AS1746
Dual SPDT Switch
GND
6
V+
1
EP
11
U6A
AS1746
(n.m.)
AS3709-AN02-Evaluation Kit Description
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Figure 12: Schematic page 4
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Size
Date
Project Title
Revision
Sheet ofOriginator SKRE
AS3709 Evaluation BoardA4 1.2
06.05.2013
7
6
PIC24FJ64GB
PGED1
1
PGEC1
2
RP2
3
RP3
4
VSS
5
RA2
6
RP4
8
RA4
9
VDD
10
RB5
11
VBUS
12
RP7
13
RP9
15
DISVREG
16
VCAP
17
D+
18
D-
19
VUSB
20
RP15
23
VSS
24
VDD
25
MCLR
26
RP5
27
RP6
28
RA3
7
RP8
14
RP13
21
RP14
22
EP
29
PIC24FJ64GB002-I/ML-ND
U3
PIC24FJ64GB002
BUS_PWR
1
D-
2
D+
3
ID
4
GND
5
CASE
6
U5
USB_AB_MINI_SMD_MOLEX
AS1360
LDO
OUT
2
IN
3
GND
1
U4
AS1360
R8
100k
D+
D-
VBUS_5V
C17
100nF
GND
VBUS_5V
GND GND
D-
D+
VDD_PIC_3V3
J18
9729062
J19
SCLK(U1) SDA(U1)
D+
D-
1
2
3
4
5
6
J12
VBUS_5V
GND
VDD_PIC_3V3
R7
10k
C14
100nF
C40
100nF
C20
100nF
GND
VDD_PIC_3V3
1907503
C16
10µF
GND
R9
8k2
R10
8k2
VSUP VSUP
J15 J16
SDA_pullup
RP13
RP13
GPIO1(U1)
GPIO2(U1)
XRES(U1)
programming IF
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
J11
HEADER10_THMD GND
RP8
RP9
J13
J14
J17
GPIO1(U1)
RP2
GPIO2(U1)
XRES(U1)
GND
GND
0603ESDA-TR1
D4
ESD
D5
ESD
D6
ESD
GND
1
TP20
VDD_PIC_3V3
RP3
RP4
SCLK(U2) SDA(U2)
1
2
3
J20
SCLK
1
2
3
J21
SDA
2
5
3
4
U6B
AS1746
10
7
9
8
U6C
AS1746
RP5
RP5
SCLK SDA
SCLK
SDA
1
TP16
SCLK
1
TP19
SDA
MM3Z6V2T1GOSCT-ND
D7
6V2
C18
1µF
C19
1µF
(n.m.)
(n.m.)
(n.m.)
(n.m.)
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