Silicon Labs Si53159-EVB User guide

Brand: Silicon Labs

Model: Si53159-EVB

Type: User guide

Si53159-EVB

Si53159 EVALUATION BOARD USER’S GUIDE

Description

The Si53159 is a nine port PCIe clock buffer compliant

to the PCIe Gen1, Gen2 and Gen3 standards. The

Si53159 is a 48-pin QFN device that operates on a

3.3 V power supply and can be controlled using SMBus

signals along with hardware control input pins. The

device is spread aware and accepts frequency spread

differential clock frequency range from 100 to 210 MHz.

The connections are described in this document.

EVB Features

This document is intended to be used in conjunction

with the Si53159 device and data sheet for the following

tests:

 PCIe Gen1, Gen2, Gen3 compliancy

 Power consumption test

 Jitter performance

 Testing out I

C code for signal tuning

 In-system validation where SMA connectors are

present

Si53159

DIFF5

connection

for

application

DIFF4

connection

for

application

DIFF2 connection

for application

VDD = 3.3 V

power supply

GND

SDATA

GND

SCLK

DIFF1 connection for

application

DIFF2 Output Enable

DIFF4/DIFF5 Output Enable

DIFF6/DIFF8 Output Enable

Power connectors

Differential

Clock Input

DIFF3 connection

for application

DIFF6

connection

for

application

DIFF7 connection

for application

DIFF8 connection

for application

DIFF3 Output Enable

DIFF1 Output Enable

DIFF0 Output Enable

DIFF0 connection

for application

CKPWRGD/Power down enable

Si53159-EVB

2 Rev. 0.1

1. Front Panel

Figure 1. Evaluation Module Front Panel

Table 1. Input Jumper Settings

Jumper Label Type Description

OE0 I

OE0, 3.3 V Input for Enabling DIFF0 Clock Output.

1 = DIFF0 enabled, 0 = DIFF0 disabled.

OE1 I

OE1, 3.3 V Input for Enabling DIFF1 Clock Output.

1 = DIFF1 enabled, 0 = DIFF1 disabled.

OE2 I

OE2, 3.3 V Input for Enabling DIFF2 Clock Output.

1 = DIFF2 enabled, 0 = DIFF2 disabled.

OE3 I

OE3, 3.3 V Input for Enabling DIFF3 Clock Output.

1 = DIFF3 enabled, 0 = DIFF3 disabled.

OE4/5 I

OE4/5, 3.3 V Input for Enabling DIFF4 and DIFF5 Clock Outputs.

1 = DIFF4 & DIFF5 enabled, 0 = DIFF4 & DIFF5 disabled.

OE6/8 I

OE6/8, 3.3 V Input for Enabling DIFF6, DIFF7 and DIFF8 Clock Outputs.

1 = DIFF6, DIFF7 & DIFF8 enabled, 0 = DIFF6, DIFF7 & DIFF8 disabled.

CLKPWGD/PD

3.3 V LVTTL Input.

After CLKPWGD (active high) assertion, this pin becomes a real-time input for

asserting power down (active low).

SDATA I/O

SMBus-Compatible SDATA.

SCLK I

SMBus-Compatible SCLOCK.

I2C connect -For I2C read and

write. In sequence SData, Gnd,

SCLK from left to right

3.3V Power Supply Connector

Power Connectors

DIFF6 Differential out

DIFF3 Differential output

DIFF2 Differential output

DIFF1 Differential output

DIFF0 Differential output

Differential Buffer Input

for on Si53159-EVB only

OE2, OE3, OE4/5 and

OE6/8 hardware inputs

control for DIFF2, DIFF3,

DIFF4 though DIFF5 and

DIFF6 through DIFF8

outputs respectively

Si53159 device mount

GND Connector

OE0 and OE1 hardware

input control for DIFF0

and DIFF1 respectively

DIFF4 Differential output

DIFF5 Differential output

DIFF7 Differential output

DIFF8 Differential output

CKPWRGD/ Power down input

control

Si53159-EVB

Rev. 0.1 3

1.1. Generating DIFF Outputs from the Si53159

Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF

outputs DIFF[0:8] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0)

and high (1) as shown in the figure below, the jumper placed on the middle and left pin will set input OE0 to low;

and jumper placed on the middle and right pin will set input OE0 to high.

The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is

explained in detail below.

1.1.1. OE [0:8] Inputs

The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in

corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)

results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.

Each of the hardware OE [0:8] pins are mapped via I

C to control bit in Control register. The hardware pin and the

enable the DIFF output. The DIFF outputs and their corresponding I

C control bits and hardware pins are listed in

Table 2.

Table 2. Output Enable Control

C Control Bit

Output Hardware Control Input

Byte1 [bit 4] DIFF0 OE0

Byte1 [bit 2] DIFF1 OE1

Byte2 [bit 1] DIFF2 OE2

Byte2 [bit 0] DIFF3 OE3

Byte1 [bit 7] DIFF4 OE4/5

Byte1 [bit 6] DIFF5 OE4/5

Byte2 [bit 5] DIFF6 OE6/8

Byte2 [bit 4] DIFF7 OE6/8

Byte2 [bit 3] DIFF8 OE6/8



Si53159-EVB

4 Rev. 0.1

2. Schematics

Figure 2. QFN-48 Device Connection

Figure 3. Device Power Supply

DUTGND

XTL P/N:

ECS-250-20-5PXDU-F-TR

Use SMD footprint

DUTGND

VDD1

VDD2

VDD12

VDD13

VDD23

VDD34

VDD40

CKPWRGD_PD#

SDATA

SCLK

DIFF1_17

DIFF1#_18

DIFF2_19

DIFF2#_20

DIFF3_21

DIFF3#_22

DIFF4_26

DIFF4#_25

DIFF5_28

DIFF5#_27

DIFF6_31

DIFF6#_30

DIFF7_33

DIFF7#_32

OE0

OE1

OE3

OE2

OE4/5

OE6/8

DIFF0_14

DIFF0#_15

DIFF8_36

DIFF8#_35

XIN_DIFFIN#

XOUT_DIFFIN

SSON

NC_44

NC_43

NC_48

NC_47

VDD1

0.1uF

R10

YC1

0.1uF

YC2

C60

0.1uF

C61

0.1uF

Si53159

VDD_PCI

VDD_PLL3

OE0

OE1

SSON

VSS_PLL3

VSS_PLL4

OE2

OE3

OE4/5

OE6/8

VDD_PLL4

VDD_PLL2

SRC0

SRC0#

VSS_PLL2

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4#

SRC4

VSS_SRC

VDD_SRC

SRC5#

SRC5

VSS_PLL1

SRC6#

SRC6

SRC7#

SRC7

VDD_PLL1

SRC8#

SRC8

SCLK

SDATA

CKPWRGD_PDB

VDD_REF

XOUT

XIN/CLKIN

NC_43

NC_44

VSS_REF

VSS_PCI

NC_47

NC_48

VCC_3.3V

VDD1

VDD2

VDD12

VDD13

VDD23

VDD34

VDD40

0.1uF

10uF

JP4

JUMPER

JP7

JUMPER

10uF

C16

1uF

GND1

HEADER 1x1

TP4

JP3

JUMPER

C15

1uF

C14

1uF

C38

1uF

VDD_3.3V1

HEADER 1x1

C17

1uF

C13

1uF

JP2

JUMPER

C37

10uF

R35

TP5

JP8

JUMPER

JP1

JUMPER

TP1 TP2

C12

10uF

C36

1uF

C11

10uF

JP5

JUMPER

10uF

C35

10uF

R34

TP3

C10

10uF

Si53159-EVB

Rev. 0.1 5

Figure 4. Clock and Control Signals

Figure 5. Differential Clock Signals

SCLK/SDATA

DUTGND

VDD_3.3V

SSON

NC_43

NC_44

OE0

OE1

SCLK

SDATA

XIN_DIFFIN#

XOUT_DIFFIN

OE2

OE3

OE4/5

OE6/8

NC_47

NC_48

CKPWRGD_PD#

P12

HEADER 1x3

R16

HEADER 1x3

R60

10K

P13

HEADER 1x3

R57

10K

R46

10K

R23

10K

R63

10K

XO UT_ DIF F IN1

SMA

HEADER 1x3

R38

10K

HEADER 1x3

P10

HEADER 1x3

R48

10K

R20

10K

R15

10K

P11

HEADER 1x3

R24

10K

HEADER 1x3

R17

10K

XIN_ DIF F IN#1

SMA

R36

10K

R33

10K

L1 SHOULD BE

SHORT AS POSSIBLE

L1 SHOULD BE

SHORT AS POSSIBLE

L1 SHOULD BE

SHORT AS POSSIBLE

L1 SHOULD BE

SHORT AS POSSIBLE

DUTGND

L1 SHOULD BE

SHORT AS POSSIBLE

L1 SHOULD BE

SHORT AS POSSIBLE

DUTGND

L1 SHOULD BE

SHORT AS POSSIBLE

L1 SHOULD BE

SHORT AS POSSIBLE

DUTGND

L1 SHOULD BE

SHORT AS POSSIBLE

DUTGND

DIFF0_14

DIFF0#_15

DIFF1#_18

DIFF1_17

DIFF3#_22

DIFF3_21

DIFF4#_25

DIFF4_26

DIFF2#_20

DIFF2_19

DIFF5#_27

DIFF5_28

DIFF6#_30

DIFF6_31

DIFF7_33

DIFF7#_32

DIFF8_36

DIFF8#_35

C28

2.0pF

DIFF0

SMA

C57

2.0pF

DIFF6

SMA

C52

2.0pF

C33

2.0pF

DIFF8#_1

SMA

DIFF2

SMA

C30

2.0pF

C27

2.0pF

C54

2.0pF

C53

2.0pF

DIFF7#_1

SMA

DIFF1

SMA

C50

2.0pF

DIFF4#_1

SMA

C55

2.0pF

DIFF3#_1

SMA

C32

2.0pF

C51

2.0pF

DIFF5#_1

SMA

C29

2.0pF

DIFF8

SMA

DIFF6#_1

SMA

C34

2.0pF

DIFF2#_1

SMA

C58

2.0pF

DIFF7

SMA

DIFF4

SMA

DIFF1#_1

SMA

DIFF3

SMA

C56

2.0pF

C59

2.0pF

DIFF5

SMA

DIFF0#_1

SMA

C31

2.0pF

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reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

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