Silicon Labs Si53119-EVB User guide

Silicon Labs
Brand
Silicon Labs
Model
Si53119-EVB
Type
User guide
Rev. 0.1 11/14 Copyright © 2014 by Silicon Laboratories Si53119-EVB
Si53119-EVB
Si53119 EVALUATION BOARD USER’S GUIDE
Description
The Si53119-EVB can be used to evaluate the Si53119-
A01AGM, 19-output PCIe buffer in zero delay and non-
zero delay modes.
Features
10-inch traces to evaluate signal integrity at the
longest trace lengths
The signal traces of the input and outputs have a single-
ended impedance of 50 , and differential impedance of
100 .
The series resistance on the outputs are set to match to
this impedance design.
DC pin controls per data sheet specification.
Ability to measure input to output propagation delay.
Ability to program features of Si53119 via I
2
C lines.
Si53119-EVB
2 Rev. 0.1
1. Schematics
Figure 1. Schematic 1
CLK_IN
CLK_IN#
SA_0
SA_1
SDA
SCL
DIFF_0
DIFF_1 DIFF_2 DIFF_3 DIFF_4 DIFF_5 DIFF_6 DIFF_7 DIFF_8 DIFF_9
DIFF_10
DIFF_11
DIFF_0# DIFF_1# DIFF_2# DIFF_3# DIFF_4# DIFF_5# DIFF_6# DIFF_7# DIFF_8# DIFF_9#
DIFF_10#
DIFF_11#
100M_133M#
BYPASS/BWSEL
PWRGD/#
CLK_IN_RET
CLK_IN#_RET
VDD_IOVDD
VDDA
VDDR
DIFF_12
DIFF_12#
DIFF_13
DIFF_13#
DIFF_14
DIFF_14#
DIFF_15
DIFF_15#
DIFF_16
DIFF_16#
DIFF_17
DIFF_17#
DIFF_18
DIFF_18#
Si53119
U1
100M_133M#
3
HBW_BYPASS_LBW#
4
PWRGD_PWRDN#
5
CLK_IN
8
CLK_IN#
9
SA_0
10
SDA
11
SCL
12
SA_1
13
FBOUT_NC#
14
FBOUT_NC
15
DIF_10
47
DIF_10#
48
DIF_11
49
DIF_11#
50
DIF_12
53
DIF_12#
54
DIF_13
55
DIF_13#
56
DIF_14
59
DIF_14#
60
DIF_15
61
DIF_15#
62
DIF_16
65
DIF_16#
66
DIF_17
67
DIF_17#
68
DIF_18
71
DIF_18#
72
VDDA
1
GNDA
2
GND
6
VDDR
7
GND
16
VDD_IO
21
GND
22
GND
27
VDD
28
VDD_IO
33
GND
34
GND
39
VDD_IO
40
VDD
45
GND
46
GND
51
VDD_IO
52
VDD_IO
57
GND
58
GND
63
VDD
64
VDD_IO
69
GND
70
GND
73
DIF_0
17
DIF_0#
18
DIF1
19
DIF1_#
20
DIF_2
23
DIF_2#
24
DIF_3
25
DIF_3#
26
DIF_4
29
DIF_4#
30
DIF_5
31
DIF_5#
32
DIF_6
35
DIF_6#
36
DIF_7
37
DIF_7#
38
DIF_8
41
DIF_8#
42
DIF_9
43
DIF_9#
44
R110K
R210K
R310K
R910K
R410K
R1610K
R1710K
R6
0
R5
0
Si53119-EVB
Rev. 0.1 3
Figure 2. Schematic 2
Si53119-EVB
4 Rev. 0.1
Figure 3. Schematic 3
5 4 3 2 1
D
C
B
A
Si53119-EVB
Rev. 0.1 5
2. Jumpers
Jumpers can be set per the diagram above. Please refer to the Si53119-A01AGM data sheet for a description on
how the pin states affect the device. (M--Insert link here to data sheet when it’s released.)
1. P15 and P17 disable I2C control when shorted.
2. P14 can be used to set PWRGD# (VDD or Ground).
3. P16 can be used to set outputs clocks to either 100MHz or 133MHz (controls the 100_133@# pin).
4. Jumpers J11, J14, and J19 are tri-level jumpers that control BYPASS/BWSEL, SA_0, and SA_1 respectively.
5. P1 needs to be shorted to enable generation of VDD/2.
Default jumper setting on the EVB:
1. P15, P17 are shorted, disabling I
2
C.
2. P14 is shorted to VDD (PWRGD# = High).
3. P16 is shorted to VDD (100_133# = High).
4. BYPASS/BWSEL, SA_0, SA_1 are all pulled low (J11, J14, J19 pulled to ground).
5. P1 is shorted to enable VDD/2 (needed for tristate input pin conditioning).
3. Input and Power Supply Sequencing
The Si53119 should be powered up with supply at both the VDD and VDD_IO nodes (at the jumpers available on
the EVB). A 100 MHz or 133 MHz HCSL input clock should be applied to pins 8 and 9, and should comply with
HCSL formats. There is no internal or onboard resistive termination, therefore HCSL termination needs to be
provided at the input if needed by the driver. The input clock should be applied only after the supplies are stable.
4. Quick Start Guide:
1. Enable supply on the VDD pin.
2. Enable supply on the VDDIO pin.
3. Apply input clock on SMA connectors J26, J29 and measure the return path clock on J32, J33 (as shown
below).
Figure 4. Clock Return Path
a. The input clock measured at J32, J33 needs a 50-ohm termination on the scope.
b. The attenuation will be 1:10 after the above termination. Appropriate scaling (10x) needs to be set at the
scope to adjust for the scaling.
4. The output clocks are now set up and can be measured on an oscilloscope or frequency domain measurement
instrument.
Si53119-EVB
6 Rev. 0.1
5. Usage of the EVB
Once the EVB has been set up, the following can be evaluated:
1. Signal integrity of the device when driving 10-inch, 100-ohm differential traces.
2. Effect of capacitance load on output signal integrity.
3. Output-to-output skew over 10-inch traces.
4. Input-to-output prorogation delay in BYPASS, HBW, and LBW modes using the input clock return path.
5. Measuring the power consumption of the device.
6. Modification of the device settings via the I
2
C interface.
Si53119-EVB
Rev. 0.1 7
6. Bill of Materials
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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Silicon Labs Si53119-EVB User guide

Silicon Labs
Brand
Silicon Labs
Model
Si53119-EVB
Type
User guide
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