ESD VME-CPU/T10 VME Master CPU Owner's manual

Brand: ESD

Model: VME-CPU/T10 VME Master CPU

Type: Owner's manual

VME-CPU/T10

VME Master with 64-bit PowerPCTM T1022,

XMC/PMC Slots

VME-CPU/T10-F

VME Master with 64-bit PowerPCTM T1014

VME-CPU/T10

Hardware Manual

to Product V.1940.01,

V.1940.02

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 1 of 64

esd electronics gmbh

Vahrenwalder Str. 207 • 30165 Hannover • Germany

http://www.esd.eu

Phone: +49 (0) 511 3 72 98-0 • Fax: +49 (0) 511 3 72 98-68

N O T E

The information in this document has been carefully checked and is believed to be entirely reliable.

esd electronics makes no warranty of any kind with regard to the material in this document, and

assumes no responsibility for any errors that may appear in this document. In particular

descriptions and technical data specified in this document may not be constituted to be guaranteed

product features in any legal sense.

esd electronics reserves the right to make changes without notice to this, or any of its products, to

improve reliability, performance or design.

All rights to this documentation are reserved by esd electronics. Distribution to third parties, and

reproduction of this document in any form, whole or in part, are subject to esd electronics's

written approval.

esd electronics gmbh

Vahrenwalder Str. 207

30165 Hannover

Germany

Phone: +49-511-372 98-0

Fax: +49-511-372 98-68

E-Mail: [email protected]

Internet: www.esd.eu

This manual contains important information and instructions on safe and efficient

handling of the VME-CPU/T10. Carefully read this manual before commencing any work

and follow the instructions.

The manual is a product component, please retain it for future use.

Trademark Notices

PowerPC™ and the PowerPC logo™ are trademarks of IBM in the United States and/or other countries.

VITA™ is a trademark of the VMEbus International Trade Association in the United States and other countries.

PCI Express® is a registered trademark of PCI-SIG.

QorIQ® is a registered trademark of NXP USA Inc. in the United States and/or other countries.

Cyclone® is a registered trademark of the Altera Corporation in the United States and other countries.

Linux® is the registered trademark of Linus Torvalds in the United States and/or other countries.

VxWorks® is a registered trademark of Wind River Systems, Inc.

QNX® is a registered trademark of QNX Software Systems Limited, and are registered trademark and/or used in certain

jurisdictions.

EtherCAT® is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.

All other trademarks, product names, company names or company logos used in this manual are reserved by their

respective owners.

Page 2 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

Document file: I:\Texte\Doku\MANUALS\VME\VME-CPU-T10\Englisch\VME-CPU-T10_Manual_en_14.odt

Date of print: 2021-08-24

Document type

number: DOC0800

Hardware version: VME-CPU/T10: 1.0

VME-CPU/T10-F: 1.0

Document History

The changes in the document listed below affect changes in the hardware as well as changes in

the description of the facts, only.

Rev. Chapter Changes versus previous version Date

1.0 - First English manual 2016-12-02

1.1

1.2 Text about customized digital IO expansion of health controller deleted

2017-01-187.6.5 Correction of description: Pin-out conforms with P4V2-46dz

13 Order information for BSP-Support supplemented

1.2

1.2 Block circuit diagram without optional MCU (Health)

2018-11-14

2.1.1 PCB top layer view (with PMV voltage keying pins)

2.3.4 Note on voltage keying pins inserted

3.2.1 Note on default settings inserted

3.2.2 Note on default settings inserted

3.2.3 New chapter ”PMC voltage Keying Pins”

4. Description of installation step 5 revised.

7.8 Description of XMC-CPU-ADAPTER-NXP deleted

13. Order Information of VME-CPU/T10-Cable_Console inserted, CPU-

ADAPTER-NXP removed

1.3

Note on declaration of conformity added under safety instructions

2019-03-01

2.3.4 Note on Mezzanine filler panels inserted

4. Note on Mezzanine filler panels and conductive O-ring added

7.1 Note on cable added

9.2 Cross-references corrected

13. New chapter: “EU-Declaration of Conformity”

1.4

1.3 Block circuit diagram corrected: CPU QorIQ T1014

2021-08-24

5.2 Table supplemented, CPU: NXP QorIQ T1022 (VME-CPU/T10) or T1014

(VME-CPU/T10-F)

Technical details are subject to change without further notice.

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 3 of 64

Classification of Warning Messages and Safety Instructions

This manual contains noticeable descriptions, warning messages and safety instructions, which

you must follow to avoid personal injuries or death and property damage.

This is the safety alert symbol.

It is used to alert you to potential personal injury hazards. Obey all safety messages

and instructions that follow this symbol to avoid possible injury or death.

DANGER, WARNING, CAUTION

Depending on the hazard level the signal words DANGER, WARNING or CAUTION are used to

highlight safety instructions and warning messages. These messages may also include a warning

relating to property damage.

DANGER

Danger statements indicate a hazardous situation which, if not avoided, will result in

death or serious injury.

WARNING

Warning statements indicate a hazardous situation that, if not avoided, could result in

death or serious injury.

CAUTION

Caution statements indicate a hazardous situation that, if not avoided, could result in

minor or moderate injury.

NOTICE

Notice statements are used to notify people on hazards that could result in things other than

personal injury, like property damage.

NOTICE

This NOTICE statement indicates that the device contains components sensitive to

electrostatic discharge.

NOTICE

This NOTICE statement contains the general mandatory sign and gives information that

must be heeded and complied with for a safe use.

INFORMATION

Notes to point out something important or useful.

Page 4 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

Safety Instructions

● When working with the VME-CPU/T10 follow the instructions below and read the manual carefully to

protect yourself from injury and the VME-CPU/T10 from damage.

● The device is a built-in component. It is essential to ensure that the device is mounted in a way that

cannot lead to endangering or injury of persons or damage to objects.

● Do not use damaged or defective cables to connect the VME-CPU/T10.

● In case of damages to the device, which might affect safety, appropriate and immediate measures

must be taken, that exclude an endangerment of persons and domestic animals and property.

● Current circuits which are connected to the device have to be sufficiently protected against

hazardous voltage (SELV according to EN 60950-1).

● The VME-CPU/T10 may only be driven by power supply current circuits, that are contact protected.

A power supply, that provides a safety extra-low voltage (SELV) according to EN 60950-1, complies

with this conditions.

● The device has to be securely installed in the control cabinet before commissioning.

● Protect the VME-CPU/T10 from dust, moisture and steam.

● Protect the VME-CPU/T10 from shocks and vibrations.

● The VME-CPU/T10 may become warm during normal use. Always allow adequate ventilation around

the VME-CPU/T10 and use care when handling.

● Do not operate the VME-CPU/T10 adjacent to heat sources and do not expose it to unnecessary

thermal radiation. Ensure an ambient temperature as specified in the technical data.

DANGER

Hazardous Voltage - Risk of electric shock due to unintentional contact with uninsulated live

parts with high voltages inside of the system into which the VME-CPU/T10 is to be integrated.

→

All current circuits which are connected to the device have to be sufficiently protected

against hazardous voltage (SELV according to EN 60950-1) before you start with the

installation.

Ensure the absence of voltage before starting any electrical work

DANGER

Risk of personal injury due to explosion or leakage of the battery!

Improper usage of the battery such as overheating, short-circuiting or mechanical damage

may cause an explosion or leakage.

→

Do not replace the battery by an incorrect type.

Do not recharge the battery.

Insert the battery properly, with the +/- terminals correctly oriented.

Dispose used batteries according to the national instructions.

NOTICE

Electrostatic discharges may cause damage to electronic components.

To avoid this discharge the static electricity from your body before you touch the VME-

CPU/T10.

Qualified Personnel

This documentation is directed exclusively towards personnel qualified in control and automation

engineering. The installation and commissioning of the product may only be carried out by qualified

personnel, which is authorized to put devices, systems and electric circuits into operation according to

the applicable national standards of safety engineering.

Conformity

The VME-CPU/T10 is an industrial product and meets the demands of the EU regulations and EMC

standards printed in the conformity declaration at the end of this manual.

Warning: In a residential, commercial or light industrial environment the VME-CPU/T10 may cause

radio interferences in which case the user may be required to take adequate measures.

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 5 of 64

The VME-CPU/T10 is a sub-assembly intended for incorporation into an apparatus. The manufacturer

of the final system must decide, whether additional EMC or EMI protection requirements are necessary.

Data Safety

This device is equipped with an Ethernet or other interface which is suitable to establish a connection to

data networks. Depending on the software used on the device, these interfaces may allow attackers to

compromise normal function, get illegal access or cause damage.

esd does not take responsibility for any damage caused by the device if operated at any networks. It is

the responsibility of the device's user to take care that necessary safety precautions for the device's

network interface are in place.

Intended Use

The intended use of the VME-CPU/T10 is the operation as VME Master with 64-bit PowerPCTM T1022,

XMC/PMC Slots.

The VME-CPU/T10-F is a customized version of the VME-CPU-board with NXP® QorIQ® T1014

processor.

The guarantee given by esd does not cover damages which result from improper use, usage not in

accordance with regulations or disregard of safety instructions and warnings.

● The VME-CPU/T10 is intended for installation in a VME system only.

● The operation of the VME-CPU/T10 in hazardous areas, or areas exposed to potentially explosive

materials is not permitted.

● The operation of the VME-CPU/T10 for medical purposes is prohibited.

Service Note

The VME-CPU/T10 does not contain any parts that require maintenance by the user. The VME-

CPU/T10 does not require any manual configuration of the hardware. Unauthorized intervention in the

device voids warranty claims.

Disposal

Devices which have become defective in the long run have to be disposed in an appropriate way or

have to be returned to the manufacturer for proper disposal. Please, make a contribution to

environmental protection.

Typographical Conventions

Throughout this manual the following typographical conventions are used to distinguish technical terms.

Convention Example

File and path names /dev/null or <stdio.h>

Function names open()

Programming constants NULL

Programming data types uint32_t

Variable names Count

Number Representation

All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix

of 0x. For example, 42 is represented as 0x2A in hexadecimal.

Abbreviations

API Application Programming Interface

CPU Central Processing Unit

HW Hardware

I²C Inter-Integrated Circuit

I/O Input/Output

n.a. not applicable

OS Operating System

PCIe Peripheral Component Interconnect Express

PMC PCI Mezzanine Card

SDK Software Development Kit

USB Universal Serial Bus

XMC PCIe Mezzanine Card

Page 6 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

Table of contents
 Safety Instructions...........................................................................................................................5
Overview...................................................................................................................................... 9
1 Differences between VME-CPU/T10 and VME-CPU/T10-F...................................................9
2 VME-CPU/T10 Standard Version.........................................................................................10
3 Version VME-CPU/T10-F.....................................................................................................12
PCB View with Connectors.........................................................................................................13
1 VME-CPU/T10.....................................................................................................................13
1.1  PCB Top Layer VME-CPU/T10...................................................................................13
1.2 PCB Bottom Layer View with Coding Switches VME-CPU/T10...................................14
2 VME-CPU/T10-F..................................................................................................................15
2.1  PCB Top Layer VME-CPU/T10-F...............................................................................15
2.2 PCB Bottom Layer View with Coding Switches VME-CPU/T10-F................................16
3 Front Panel..........................................................................................................................17
3.1 Reset...........................................................................................................................17
3.2 LED Indication of the BiColor LEDs A, B, C, D............................................................18
3.3 LED Indication of the Ethernet LEDs...........................................................................18
3.4 PMC / XMC Slots........................................................................................................19
Hardware Configuration..............................................................................................................20
1 Coding Switches..................................................................................................................20
2 Jumpers and Keying Pins....................................................................................................21
2.1 Jumpers J232-2, J232-1, JETH...................................................................................21
2.2 Jumpers J100, J120....................................................................................................22
2.3 PMC Voltage Keying Pins............................................................................................23
Hardware Installation and Change of Battery.............................................................................24
1 Installation............................................................................................................................ 24
2 Demounting......................................................................................................................... 25
3 Change of Battery ...............................................................................................................26
Technical Data............................................................................................................................27
1 General Technical Data........................................................................................................27
2 CPU and Memory................................................................................................................28
3 FPGA .................................................................................................................................. 28
4 Ethernet Interface................................................................................................................28
5 Serial Interfaces...................................................................................................................29
6 I²C Interface......................................................................................................................... 29
7 Parallel MRAM.....................................................................................................................29
8 XMC Interface .....................................................................................................................30
9 PMC Interface......................................................................................................................30
10 Memory Interface...............................................................................................................30
11 USB, USB Host Interface...................................................................................................31
12 Real-Time Clock (RTC)......................................................................................................31
13 AC - Fail.............................................................................................................................31
14 Software Support............................................................................................................... 32
15 Firmware License...............................................................................................................32
Description of the VME Interface................................................................................................33
Connector Assignments..............................................................................................................34
1 Ethernet 1000BASE-T (LAN1, LAN2)..................................................................................34
2 DEBUG Interface (X940).....................................................................................................35
3 VME P1 Connector .............................................................................................................36
4 VME P2 Connector .............................................................................................................37
4.1 VME-CPU/T10-P2ADA Adapters.................................................................................38
5 PMC J1-Connectors ............................................................................................................ 39
VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 7 of 64

5.1 PMC Connector J11 (Slot 1)........................................................................................39
5.2 PMC Connector J21 (Slot 2)........................................................................................40
6 PMC J2-Connectors.............................................................................................................41
6.1 PMC Connector J12 (Slot 1)........................................................................................41
6.2 PMC Connector J22 (Slot 2)........................................................................................42
6.3 PMC J4 IO Connectors................................................................................................43
6.4 PMC I/O Connector J14 (Slot 1)..................................................................................43
6.5 PMC I/O Connector J24 (Slot 2)..................................................................................44
7 XMC J5 I/O Connectors.......................................................................................................45
7.1 XMC - J15 ..................................................................................................................45
7.2 XMC - J25 .................................................................................................................46
8 JTAG X900.......................................................................................................................... 47
8.1 XMC-CPU-ADAPTER-BDI..........................................................................................47
9 Debug Interface X400 .........................................................................................................48
10 and JTAG FPGA Interface X1900......................................................................................48
11 USB Interface on X1200.....................................................................................................49
CPU............................................................................................................................................ 50
1 User configuration via GPIO register ...................................................................................50
2 Watchdog............................................................................................................................. 51
VME........................................................................................................................................... 52
1 Description of the VMEbus...................................................................................................52
2 VME Configuration...............................................................................................................53
2.1 Configuration-/Status-Register 16-Bit, Offset 0xFF20 0000.........................................54
2.1.1 Master Configuration.............................................................................................54
2.1.2 VME Window Configuration..................................................................................56
3 VME Interrupts.....................................................................................................................56
3.1 Assignment of the Interrupts........................................................................................56
3.2 Interrupts..................................................................................................................... 57
3.3 Handling of the Vector Interrupts VIRQ7 .. VIRQ1.......................................................57
3.4 “Inhibit-Mode”.............................................................................................................. 57
User LED Configuration............................................................................................................58
MRAM ...................................................................................................................................... 59
1 MRAM Register.................................................................................................................. 59
2 MRAM over MemoryMapped MRAM Access.....................................................................59
Bootloader................................................................................................................................60
1 License..............................................................................................................................60
2 Configuration and Console Access....................................................................................60
EU-Declaration of Conformity...................................................................................................62
Order Information.....................................................................................................................63
Page 8 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

Overview

1. Overview

This manual describes the VME-CPU/T10 and the VME-CPU/T10-F together as VME-CPU/T10,

differences will be noted.

The standard version VME-CPU/T10 comes with all essential components and functionalities and

is designed as replacement for the MVME5110.

The VME-CPU/T10-F is only equipped with certain components as described on page 12.

1.1 Differences between VME-CPU/T10 and VME-CPU/T10-F

The table below describes only the differences between the VME-CPU/T10 and the VME-

CPU/T10-F. For further detail read the description of the boards on page 10 and 12 or chapter

“Technical Data“ from page 27

VME-CPU/T10 VME-CPU/T10-F

Processor QorIQ® T1022 QorIQ T1014

Number of CPU-cores 2 1

NV-RAM 512kByte – MRAM serial

512kByte – MRAM parallel

RTC Epson RX8035 – Battery None

Serial interfaces 1 x RS232 / FP

(Rx/Tx/Cts/Rts only)

Additionally optional: 1 x RS232 / P2

1 x RS232 / FP

(Rx/Tx/Cts/Rts only)

PMC slot 2 x 32Bit ---

XMC slot 2 x 1 Lane (alternative to PMC slot) ---

PMC-IO P4V2-64ac / P4V2-46dz No

Power consumption < 15W typ < 10W typ

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 9 of 64

Overview

1.2 VME-CPU/T10 Standard Version

Figure 1: Block circuit diagram of VME-CPU/T10

The VME-CPU/T10 is a 64-Bit VME PowerPCTM Master CPU board with 2 XMC/PMC slots. The

NXP® PowerPC® QorIQ® T1022 with 1.2 GHz features two 64-bit e5500 Power Architecture®

processor cores with high performance data path acceleration architecture (DPAA) and network

peripheral interfaces.

The local memory bus is 64 bits wide plus 8 bits ECC with an overall capacity of 512 Mbyte.

16 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U-Boot environment offer non-

volatile memory spaces.

The VME-CPU/T10 is equipped with a second 16 Mbyte backup SPI Flash selectable by jumper

that can be used for system recovery, if a system crash occurs during a firmware update.

The Altera® Cyclone® V FPGA is connected to the CPU by local bus for low latency data exchange

and by PCI Express® for high bandwidth data exchange. The VMEbus master interface offers a

A16/A24, D16/D8 (EO) and an SGL arbiter. A VMEbus slave interface is not supported.

The XMC1 interface comes with 1 lane PCIe bus and the XMC2 interface with 4 lane PCIe bus.

They are designed according to VITATM 42.3.

Both PMC interfaces support 32-bit/66 MHz PCI bus according to PCI Local Bus Specification 3.0.

The VME-CPU/T10 is equipped with two Gigabit Ethernet interfaces accessible at the front panel.

One of the Ethernet interfaces can be routed to VME P2 (100 Mbit/s only).

A Console (Serial) RS-232 interface is accessible via an RJ45 connector at the front panel and

additionally via VME P2 connector.

Page 10 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

CPU

NXP

QorIQ T1022

CPU

NXP

QorIQ T1022

DDR3

RAM

with ECC

DDR3

RAM

with ECC

FPGA

Cyclone V

FPGA

Cyclone V

Serial_1/2

I/O

PMC

J11

J12

XMC

J25

Optional

PCIe/PCI

Bridge

PCIe/PCI

Bridge

PCIPCIe 1x

PCIe 1x

RGMII

RTC

T1 T2

T2 T3

T3 T4

Temperature Sensors

I²C

PHY

Local Bus

SPI-Flash

PCIe 1x VME

EEPROM

ENV

EEPROM

ENV

EEPROM

Boot

EEPROM

Boot

EEPROM

SPD

EEPROM

SPD

I²C

VME- Bus

5V_IN

VME

I/O

DC-

Converter

DC-

Converter

VCC

PB_Reset

PMC

J21

J22

PMC

J14

PMC

J24

I/O

RS-232_1

XMC

J15

PCIe 1x

MRAM

Parallel

MRAM

Parallel

X1220

USB

SPI

Config

RS-232_1/2

Overview

The Flash memory carries the standard boot program “Das U-Boot” and enables the VME-

CPU/T10 to boot various operating systems from on-board Flash or network.

BSPs are available from esd as described in the “Order Information” on page 63.

The esd EtherCAT master is available for the BSPs developed by esd (see page 64).

Customization of the VME-CPU/T10 is available on request:

Customized options are available for customized serial production in reasonable quantities. Please

contact our sales team for detailed information.

For example...

- CPU Type

The VME-CPU/T10 is also available with the power saving single core QorlQ CPU T1014 with

1 lane PCIe (therefore only one XMC interface) on request.

- Memory

The memory can be extended with larger MRAM, DDR3 RAM and Flash. An additional serial

MRAM is also available. Instead of the battery a Gold Cap can be equipped.

- Extended Temperature Range

If an extended temperature range is requested please ask for the -40 °C … +70 °C version of the

VME-CPU/T10.

- Special P0 Pin Routing

A special P0 pin routing according to VITA 35 P4V0-64 or customized routings, e.g. Ethernet, serial

or PMC Slot2 J4 are available on request.

- Health Controller

On request a health controller is available for monitoring of the board's status, as voltages,

temperature, board type. Additionally a watchdog can be used.

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 11 of 64

Overview

1.3 Version VME-CPU/T10-F

Figure 2: Block circuit diagram of VME-CPU/T10-F

The NXP® PowerPC® QorIQ® T1014 with 1.2 GHz features a 64-bit e5500 Power Architecture®

processor core with high performance data path acceleration architecture (DPAA) and network

peripheral interfaces.

The PMC/XMC slots are not available in the VME-CPU/T10-F version.

The VME-CPU/T10-F comes with two Gigabit Ethernet interfaces. One Ethernet interface is routed

to VME P2 (100 Mbit/s only) and can be routed to the front panel. The other interface is accessible

at the front panel.

A Console (Serial) RS-232 interface with RJ45 connector is accessible at the front panel.

Page 12 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

PCB View with Connectors

2. PCB View with Connectors

2.1 VME-CPU/T10

2.1.1 PCB Top Layer VME-CPU/T10

Figure 3: PCB top view VME-CPU/T10

NOTICE

Read chapter “Hardware Installation” on page 24 before starting the installation of the

hardware!

See also from page 34 for signal assignment of the connectors.

The JTAG connector (X400) and the CPU Debug connector (X900) have to be connected on the

PCB bottom side of the VME-CPU/T10 (see Figure 4 for the position of the connectors and pins).

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 13 of 64

PCB View with Connectors

2.1.2 PCB Bottom Layer View with Coding Switches VME-CPU/T10

Figure 4: PCB bottom view VME-CPU/T10

See also from page 34 for signal assignments of the connectors.

esd offers special adapters as accessories, see “Order Information” on page 63.

The coding switches are described on page 20.

Page 14 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

PCB View with Connectors

2.2 VME-CPU/T10-F

2.2.1 PCB Top Layer VME-CPU/T10-F

Figure 5: PCB top view VME-CPU/T10-F

NOTICE

Read chapter “Installation” on page 24 before starting the installation of the hardware!

See also from page 34 for signal assignment of the connectors.

The CPU Debug connector (X900) has to be connected on the PCB bottom side of the VME-

CPU/T10-F (see Figure 6 for the position of the connectors and pins).

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 15 of 64

PCB View with Connectors

2.2.2 PCB Bottom Layer View with Coding Switches VME-CPU/T10-F

Figure 6: PCB bottom view VME-CPU/T10-F

See also from page 34 for signal assignments of the connectors.

esd offers special adapters as accessories, see “Order Information” on page 63.

The coding switches are described on page 20.

Page 16 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

PCB View with Connectors

2.3 Front Panel

Figure 7: Connectors and LEDs VME-CPU/T10

The PMC interfaces are not available on the VME-CPU/T10-F version.

2.3.1 Reset

In the front panel a reset button is accessible, which is managed by dedicated hardware.

Here a debouncing of the signal is made.

- Push the button for at least 1 sec for a reset of the system.

The function of the Reset button can be disabled by software configuration.

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 17 of 64

PCB View with Connectors

2.3.2 LED Indication of the BiColor LEDs A, B, C, D

Four BiColor LEDs are equipped in the front panel.

LED Indicator State Description

Signal name

in schematic

diagram

Green ON CPU_OK

LED1940

Red ON FPGA not booted / CPU in Reset

Red Flash tbd.

BGreen Flash VME_Access

LED1942

Red Flash VME_Access_Error occurred

Green ON No-Fail

LED1944

Red ON SYSFAIL

Red Flash e.g.: VME_Irq pending

DUser-defined LED1946

Table 1: LEDs A - D

2.3.3 LED Indication of the Ethernet LEDs

The Activity and Link/Speed LEDs are integrated in the RJ45 sockets of LAN1 and LAN2.

LED Colour Function Indicator

State Description

Agreen Activity Flickering Ethernet activity

(reception and transmission of Ethernet data)

Lyellow Link/Speed ON Ethernet link is established,

Ethernet bit rate: 10/100/1000 Mbit/s

Table 2: Description of Ethernet LEDs

INFORMATION

If LAN 2 is routed to VME P2, the LEDs in the RJ45 socket of LAN 2 retain their function.

Page 18 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

PCB View with Connectors

2.3.4 PMC / XMC Slots

INFORMATION

The XMC/PMC interfaces are not available in the version VME-CPU/T10-F.

In the VME-CPU/T10 standard version two slots for PMC-AddOns are provided. Both slots use a

common PCI-Bus (32-bit, 33/66MHz).

The PMC-IO signals are connected to the VMEbus P2 according to „P4V2-64ac“ or „P4V2-46dz“.

Furthermore both slots can be used as XMC slots, yet the XMC IO-connectors J16/J26 are not

equipped. The second XMC slot can only be used if the CPU T1022 is equipped. (Due to a

reduced number of PCIe lanes of the CPU T1014).

For the generation of the 3.3V operating voltage of the PMC / XMC slots the following is provided:

a.) If the 3.3V supply voltage of the VMEbus is available, it is electronically connected to the

corresponding PMC slot.

b.) If the 3.3V supply voltage of the VMEbus is not available, the 3.3V for the PMC slot are

generated via a switching regulator from the 5V VME voltage. The maximum current on the 3.3V-

side is 2.5A per slot.

The VIO supply is configured individually for each slot via jumpers (see page 22). The voltage

keying pins (see page 23) have to be bolted to the VME-CPU/T10 board in accordance with the

configured signalling voltage (3.3 V or 5 V).

NOTICE

To ensure the EC conformity of the product in the front panel the cut outs of unused PMC

slots (PMC slot 1 and 2) have to be covered by the Mezzanine filler panels (see figure 7

page 17).

VME-CPU/T10 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 Page 19 of 64

Hardware Configuration

3. Hardware Configuration

3.1 Coding Switches

Figure 8: Coding switches on the PCB bottom layer (cut-out)

See also Figure 4 or 6 for the position of the coding switch on the board.

On delivery the DIP switches are all off.

Coding

Switch Pin Description

SW1790

1 SPI-SEL# OFF Booted from U840 flash (default)

ON Booted from U830 flash

2 SPI.0.WPFLASH# OFF Write protection of SPI-Flash disabled (default)

ON Write protection SPI-Flash enabled

3 LC.VME.SLOT1# OFF VME-CPU/T10 is not inserted in VME Slot 1 (default)

ON VME-CPU/T10 is inserted in VME Slot 1

4 LC.ETH_P2#

OFF Ethernet signals of LAN2 are routed to the front panel

(default)

The Ethernet signals of LAN2 are routed to JETH.

Note: Jumper JETH must be set accordingly to route

the signals to pins (1c,2c,3c,4c) on P2 (see page 21)

SW901

1 LC_IO23

User-defined via FPGA and driver

2 LC_IO22

3 LC_IO21

4 LC_IO20

SW900

1 LC_IO15

User-defined via FPGA and driver

2 LC_IO14

3 LC_IO13

4 LC_IO12

Table 3: Coding Switch SW1790, SW901, SW900

Page 20 of 64 Hardware Manual • Doc. No.: V.1940.21 / Rev. 1.4 VME-CPU/T10

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ESD VME-CPU/T10 VME Master CPU Owner's manual

ESD VME-CPU/T10 VME Master CPU Owner's manual

ESD VME-CPU/T10 VME Master CPU Owner's manual

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