Cirrus Logic 3CFM User manual

Brand: Cirrus Logic

Model: 3CFM

Category: Remote controls

Type: User manual

This manual is also suitable for

Crystal CDB4228A

Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.



Cirrus Logic, Inc. 2000

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

CDB4228A

Evaluation Board for CS4228A

Features

lDemonstrates recommended layout and

grounding arrangements

lCS8414 receives AES/EBU, S/PDIF & EIAJ-

340 compatible digital audio

lCS8404 transmits AES/EBU, S/PDIF & EIAJ-

340 compatible digital audio

lPC software provides easy to use board and

device control

lInterfaces for external serial audio I/O and

microprocessor control

Description

The CDB4228A evaluation board is an excellent means

for quickly evaluating the CS4228A 2 in, 6 out, 24-bit,

96kHz capable CODEC. Evaluation requires an analog

signal source and analyzer, a digital signal source and

analyzer, a PC compatible computer for control, and a

power supply.

System timing can be supplied by the CS8414 digital au-

dio receiver I.C., or an onboard oscillator. Control is

provided by PC software. The evaluation board may also

be configured to accept external timing, data, and control

signals for operation in a user application during system

development.

ORDERING INFORMATION

CDB4228A Evaluation Board

CS4228A

Digital Audio Port

PC Control Port

Analog

Outputs

CS8414

Digital

Audio

Receiver

CS8404

Digital

Audio

Transmitter

External

Oscillator Analog

Inputs

MCLK

LRCLK

SCLK

SDIN1

SDIN2

SDIN3

SDOUT

SCK

SDA/CDIN

CDOUT

PLD

Control

Port

OCT ’00

DS511DB1

CDB4228A

2DS511DB1

TABLE OF CONTENTS

1. CDB4228A SYSTEM OVERVIEW .................................................................. 4

2. CS4228A CODEC ........................................................................................... 4

3. BOARD CONTROL ........................................................................................ 4

3.1 Graphical User Interface ......................................................................4

3.2 External Control Interface .................................................................... 4

4. DIGITAL AUDIO I/O ........................................................................................4

4.1 Receiver ...............................................................................................4

4.2 Transmitter ...........................................................................................4

4.3 Digital Audio Port .................................................................................5

4.4 Master Clock ........................................................................................5

4.5 Serial Data Format ...............................................................................5

5. ANALOG INPUT ............................................................................................. 5

6. ANALOG OUTPUT .........................................................................................5

7. EXTERNAL CONTROL MODE ......................................................................5

7.1 Serial Mode ..........................................................................................6

7.2 MCLK Multiplexer ................................................................................6

7.3 Transmitter Clock Divider ....................................................................6

8. POWER SUPPLY CIRCUITRY .......................................................................6

9. GROUNDING AND POWER SUPPLY DECOUPLING ..................................6

10. BILL OF MATERIALS .............................................................................. 31

LIST OF FIGURES

Figure 1. CDB4228A Top Level Schematic .........................................................9

Figure 2. Analog Input Filter ..............................................................................10

Figure 3. External Control .................................................................................11

Figure 4. Digital Audio Port ...............................................................................12

Figure 5. Analog Output Filter 1 ........................................................................13

Figure 6. Analog Output Filter 2 ........................................................................14

Figure 7. Analog Output Filter 3 ........................................................................15

Figure 8. Analog Output Filter 4 ........................................................................16

Figure 9. Analog Output Filter 5 ........................................................................17

Figure 10.Analog Output Filter 6 ........................................................................18

Figure 11.Low Cost Analog Output Filter ...........................................................19

Figure 12.Control Port Interface .........................................................................20

Figure 13.Programmable Logic ..........................................................................21

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales/cfm

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights

of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of

this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or

otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no

part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,

photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture

or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing

in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

CDB4228A

DS511DB1 3

Figure 14.Power Supply ..................................................................................... 22

Figure 15.Master Clock Circuit ........................................................................... 23

Figure 16.CS8414 Digital Audio Receiver .......................................................... 24

Figure 17.CS8404 Digital Audio Transmitter ...................................................... 25

Figure 18.Silkscreen Top ................................................................................... 26

Figure 19.Top Side ............................................................................................. 27

Figure 20.Level 2 Ground Plane ........................................................................ 28

Figure 21.Level 3 ............................................................................................... 29

Figure 22.Bottom Side ....................................................................................... 30

LIST OF TABLES

Table 1. Board Level Serial Mode Settings ............................................................. 6

Table 2. System Connections ................................................................................. 7

Table 3. MCLK Multiplexer Settings ........................................................................ 7

Table 4. CDB4228A Jumper and Switch Settings ................................................... 8

Table 5. Transmitter Clock Divider Settings ............................................................ 8

Table 6. Bill of Materials ........................................................................................ 31

CDB4228A

4DS511DB1

1. CDB4228A SYSTEM OVERVIEW

The CDB4228A evaluation board is an excellent

means of quickly evaluating the CS4228A. Input

and output analog interfaces are provided as well as

a CS8414 digital interface receiver and CS8404

digital interface transmitter that provide an easy in-

terface to digital audio test equipment. The evalua-

tion board also allows the user to interface external

systems’ digital audio clocks and data through the

digital audio port (DAP) 20-pin header. An exter-

nal two wire or SPI control interface is also provid-

ed through a 10-pin header for easy system

development using the evaluation board.

The CDB4228A schematic has been partitioned

into 17 schematics shown in Figures 1 through 17.

Each partitioned schematic is represented in the top

level schematic shown in Figure 1.

2. CS4228A CODEC

A complete description of the CS4228A CODEC is

included in the CS4228A data sheet.

3. BOARD CONTROL

3.1 Graphical User Interface

The CDB4228A is shipped with Windows based

graphical user interface (GUI) software for inter-

facing with the CS4228A control port via a PC par-

allel port connected to the DB25 connector, J15.

Parallel port control is selected by placing the

CONTROL switch S2 in the PP position. The soft-

ware can be used to communicate with the

CS4228A in two wire or SPI mode by selecting the

MODE switch S4. Further documentation for the

software is available on the distribution diskette in

the plain text format file, README.TXT.

3.2 External Control Interface

The evaluation board can also be controlled via a

external host such as a microcontroller connected

to the EXTRNL CONTROL port JP9 by placing

the CONTROL switch S2 in the EXTRNL posi-

tion. For more information, see section 7.

4. DIGITAL AUDIO I/O

4.1 Receiver

Digital-to-Analog (DAC) performance can be

quickly tested by connecting a S/PDIF audio

source to the CS8414 receiver. The S/PDIF input

can be either optical or coax, see Figure 16. How-

ever, both inputs cannot be driven simultaneously.

The interface for the CS8414 includes a serial bit

clock, serial data, left-right clock (FSYNC), and a

256 Fs master clock. The bit clock and left-right

clock signals are bidirectional, and as a pair can be

selected to supply these signals to the system, or

can be selected as inputs from the CS4228A or

DAP. The receiver data output can be simulta-

neously connected to the SDIN1, SDIN2, and

SDIN3 inputs on the CS4228A.

The receiver can be powered down to prevent asyn-

chronous clock interference by depressing all three

rocker switches to the OFF position on the RX

PWR DIP switch S1.

The operation of the CS8414 and a discussion of

the digital audio interface are included in the

CS8414 data sheet.

4.2 Transmitter

The analog-to-digital converter performance can

be quickly evaluated by connecting an analog gen-

erator to the left and right inputs, and connecting

the S/PDIF optical or coaxial output to audio test

equipment. The CS8404 digital interface transmit-

ter is connected to the CODEC serial data output

SDOUT, and the system bit clock, left-right clock

and master clock as shown in Figure 17. The trans-

mitter and CS4228A share several serial modes,

but not all modes of each device are supported.

SMODE 4 and 5 will not work properly with the

transmitter: The data will be right-shifted by 8 bits.

The transmitter must always be supplied a 128 Fs

master clock, which is supplied by clock dividers

within the PLD. The clock divider source is the

same as that selected for the CS4228A MCLK. The

CDB4228A

DS511DB1 5

PLD can support division ratios of 1, 2, 3, and 4 to

support MCLK frequencies of 128, 256, 384, and

512 Fs respectively. The proper division ratio can

be selected in the GUI in PP mode, or S5 in EX-

TRNL mode.

4.3 Digital Audio Port

The digital audio port (DAP) provides an interface

to the CODEC serial audio clocks and data. The

DAP can be used to interface to external com-

pressed audio decoder systems such as the CS492x

or CS49300 families of digital signal processors for

ease in evaluating complete audio system solu-

tions. MCLK, LRCLK, and SCLK are bidirectional

signals. The direction of these signals can be con-

trolled by the GUI in PP mode, or S5 switches in

EXTRNL mode. The direction of SCLK and LR-

CLK is always selected as a pair.

4.4 Master Clock

Master clock (MCLK) for the evaluation board can

come from one of three sources: the on-board

CS8414 receiver, the on-board oscillator, or an ex-

ternal source via the DAP port. One of the three

sources is selected by multiplexer U2 which is con-

trolled via the GUI in PP mode or the S5 switches

in EXTRNL mode. The on-board oscillator provid-

ed with the board is 12.288 MHz for evaluation at

256 Fs at a 48kHz sample rate, or 128 Fs at a 96kHz

sample rate. The oscillator is socketed for easy re-

placement and can be powered down with header

JP1 to prevent asynchronous clock interference

when the S/PDIF receiver is being used.

The MCLK multiplexer adds a small amount of

clock jitter to the MCLK signal, which has a very

slight effect on converter performance. The system

can be evaluated without the buffer by installing a

3x2 pin header in JP2, and removing R3. A 2-sock-

et shorting jumper is then installed in JP2 to select

the system MCLK source. Refer to Figure 15.

4.5 Serial Data Format

The serial data format for the evaluation board is

set by the GUI in PP mode or by S5 switches in EX-

TRNL mode. Not all serial modes of each device

are supported. SMODE 4 and 5 are not supported

by the transmitter. Two serial formats are common

to all three devices; I2S, 16 to 24 bits/sample, and

right justified, 16 bits/sample.

Each of the three SDIN inputs to the CS4228A

comes from a multiplexer within the PLD and can be

individually sourced from the CS8414 receiver or

from the DAP. The multiplexer can be disabled and

jumpers JP3-JP5 can be used to select the source.

5. ANALOG INPUT

Analog inputs to the CDB4228A are single ended,

with a full scale of 2V RMS (5.66V p-p). The inputs

are AC coupled, then converted to a differential sig-

nal with a 2.3V common mode voltage derived from

the 5V supply. The differential signal is then anti-

aliased with a passive filter, Fc = 200 kHz, before

being sent to the ADC as shown in Figure 2.

6. ANALOG OUTPUT

The analog outputs from the DACs are buffered with

a 2-pole active butterworth filter, Fc = 50 kHz. The

filter has a DC gain of 1.56V/V for a 2V RMS full

scale output. For a lower cost alternative, the outputs

can be filtered with a single pole passive filter with

Fc = 50 kHz and RL > 10k ohms as shown in Figure

11. The outputs also have a mute circuit that is con-

trolled by the MUTEC pin on the CS4228A.

7. EXTERNAL CONTROL MODE

The CDB4228A system can be controlled without

using a PC by connecting a host controller to the

EXTRNL CTRL port. All board functions set by

the parallel port are available to the user on the 10

position DIP switch, S5. There are three parameters

on S5; board level serial mode, MCLK multiplex-

ing, and S/PDIF transmitter clock divider control.

On S5, an open switch denotes a one for that bit po-

sition.

CDB4228A

6DS511DB1

7.1 Serial Mode

The SMODE[4..0] switches on S5 set the serial

mode and the LRCLK/SCLK direction of all other

devices in the system except the CS4228A. The de-

vices controlled by SMODE include the CS8414,

the CS8404, and the DAP. SMODE settings on S5

are only active when in EXTRNL mode. The

SMODE mapping is shown in Table 1. Care must

be taken when setting up SMODE so that the LR-

CLK/SCLK direction corresponds with the

CS4228A master/slave setting to avoid bus conten-

tion. The CS4228A serial port master/slave mode is

set in the Serial Port Mode register 0x0D.

7.2 MCLK Multiplexer

The board level MCLK source is controlled by the

MCLK-SEL[2..0] switches on S5 when in EX-

TRNL mode. The multiplexer settings are shown in

Table 3. The MCLK source should be the CS8414

whenever the S/PDIF data source is used.

7.3 Transmitter Clock Divider

The TX_MCLK[1..0] switches on S5 control the

clock divider for the CS8404 S/PDIF transmitter

when in EXTRNL mode. The transmitter must be

supplied a 128 Fs MCLK which is sourced from the

CS4228A MCLK multiplexer. The clock divider

ratios are shown in Table 5.

8. POWER SUPPLY CIRCUITRY

Power is supplied to the evaluation board by four

binding posts (+5V, GND, +12V, -12V). The +5V

input supplies power to the analog and digital +5

Volt circuitry and to a 3.3V voltage regulator.

There is a power supply header for selecting either

5V or 3.3V supplies to the CS4228A VL pin. A

second header selects the interface voltage for the

programmable logic device that supplies the con-

trol port interface. The VL setting should always be

equal or greater than the PLD PWR to prevent

noise due to charge injection.

9. GROUNDING AND POWER SUPPLY

DECOUPLING

The CS4228A requires careful attention to power

supply and grounding arrangements to optimize

performance. The decoupling capacitors are locat-

ed as close to the CS4228A as possible. Extensive

use of ground plane fill on both the analog and dig-

ital sections of the evaluation board yields large re-

ductions in radiated noise.

SMODE

[4..0] Board Level Serial Mode CS8414

MODE CS8404

MODE DAP CLK

MODE CS8414

M[3..0] CS8404

M[2..0]

0 I2S, TX Master, 64Fs SCLK only Output Input Input 2 4

1 I2S, CODEC Master Input Input Input 3 4

2 I2S, DAP Master Input Input Output 3 4

3 Right Justified, TX Master, 16 bits Output Input Input 5 5

4 Right Justified, CODEC master Input OFF Input 15 4

5 Right Justified, DAP master Input OFF Output 15 4

6 Left Justified, CODEC master Input OFF Input 15 1

7 Left Justified, DAP master Input OFF Output 15 1

8 Left Justified, test mode Output Input Input 0 1

9 Left Justified, test mode Input Output Input 1 0

10 - 31 I2S, CODEC master Input Input Input 3 4

Table 1. Board Level Serial Mode Settings

CDB4228A

DS511DB1 7

CONNECTOR INPUT/OUTPUT SIGNAL PRESENT

+5V Input + 5 Volt power

+12V, -12V Input + 12/-12V Volt power for the op-amps

GND Input Ground connection from power supply

J9, SPDIF IN Input Digital audio interface input via coax

U9, SPDIF IN Input Digital audio interface input via optical

LEFT Input Analog audio input, 2V RMS (5.65Vp-p) full scale

RIGHT Input Analog audio input, 2V RMS (5.65Vp-p) full scale

DAC1 - DAC6 Output Analog audio output, 2V RMS (5.65Vp-p) full scale

J7, SPDIF OUT Output Digital audio interface output via coax

U5, SPDIF OUT Output Digital audio interface output via optical

Parallel Port Input/Output Parallel connection to PC for two wire® or SPI control port signals

EXT CTRL Input/Output I/O for two wire® or SPI control port signals

DAP Input/Output I/O for serial audio clocks and data

PGM Input/Output Programming header for PLD

Table 2. System Connections

MCLK-SEL

[2..0] MCLK Source DAP

MCLK DIR

0 Oscillator OFF

1 Oscillator Output

2 S/PDIF Receiver OFF

3 S/PDIF Receiver Output

4 DAP Input

5None OFF

6None OFF

7None OFF

Table 3. MCLK Multiplexer Settings

CDB4228A

8DS511DB1

JUMPER PURPOSE POSITION FUNCTION SELECTED

VD Selects the supply voltage for the

CS4228A digital core. 3.3V*

VL Selects the supply voltage for the

CS4228A logic interface pins 3.3V

5V*

RX PWR Selects the supply voltage for the

Altera PLD I/O pins. 3.3V

5V*

OSC PWR Connects power to the oscillator ON*

OFF

S1 Connects power and clocks to

the CS8414 ON*

OFF Power and LRCLK and SCLK are connected

Power, LRCLK, and SCLK are disconnected

S2 Selects control port interface PP*

EXTRNL Parallel port control enabled.

EXTRNL CTRL header enabled

S3 Selects the CS4228A SDIN1,2,3

source in EXTRNL control mode SPDIF*

DAP CS8414 data is routed to SDIN1,2,3

SDIN1,2,3 source is the DAP

S4 Selects the control port data for-

mat Two wire*

SPI Two wire control format

SPI control format

S5 Selects serial mode and DAP

clock directions in EXTRNL con-

trol mode.

CLOSED*

OPEN See external control mode section for more

information.

JP2 Optional pin header select for

MCLK OSC

SPDIF MCLK

MUX MCLK

MCLK source is onboard oscillator.

MCLK source is CS8414 receiver

MCLK source is multiplexer

Notes: *Default setting from factory

Table 4. CDB4228A Jumper and Switch Settings

TX-MCLK

[1..0] MCLK

Division Ratio System MCLK

Rate

0 1:1 128

*1 1:2 256

2 1:3 384

3 1:4 512

Table 5. Transmitter Clock Divider Settings

CDB4228A

DS511DB1 9

VLOGIC SEL

+12V

GND

-12V

+5V

+3.3V

VD SEL

+3.3V

+5V

A/D Input

OUTR+

OUTL-

OUTR-

OUTL+

AINL

AINR

Host Interface

Parallel Port

D[7..0]

STATUS[3..0]

ACKn

A[1..0]

RESETn

STROBEn

SPDIF In

SPDIF RX

MCLK

SDOUT

FSYNC

SCLK

M[3..0]

RXPWR

RX_CBL

RX_U

RX_C

RX_ERF

RX_VERF

Power

+5VBUS

+12VBUS

GND

-12VBUS MRESETn

PPRESETn

MUTEC

MUTE

X_RESETn

SPDIF Out

SPDIF TX

RESETn

SDIN

SCLK

LRCLK

MCLK

M[2..0]

TX_U

TX_C

TX_CBL

Digital Audio Port (DAP)/External Control

DAP

SCLK

LRCLK

DAP_SDOUT

MCLK

DAP_CTRL

X_SDA

X_SCL

X_AD0/CS

X_RESETn

MUTEC

DAP_SDIN[3..1]

Output Buffer2

Out2

MUTE

Output Buffer3

Out3

MUTE

Output Buffer4

Out4

MUTE

Output Buffer5

Out5

MUTE

Reference Clock

RefClk

SPDIF_MCLK

DAP_MCLK REFCLK

REFCLK_CTRL[3..0]

Output Buffer6

Out6

MUTE

Programmable Logic

PLD

D[7..0]

A[1..0]

STROBEn

STATUS[3..0]

SDA/CDOUT

SCL

AD0/CS

CDIN

ACKn

TX_M[2..0]

RX_M[3..0]

REFCLK_CTRL[3..0]

RXPWR DAP_CTRL

TX_CBL

TX_C

TX_U

RX_CBL

RX_C

RX_U

X_CTRLMRESETn CTRL_MODE

SCLK

TX_MCLK

CLKIN

LRCLK

RX_VERF

RX_ERF

SPDIF_SDOUT

SDIN[3..1]

DAP_SDIN[3..1]

SDIN_CTRL

MODE_CTRL[9..0]

Output Buffer1

Out1

MUTE

Control Switches

CONTROL

X_CTRL

SDIN_CTRL

CTRL_MODE

SDOUT_LOAD

MODE_CTRL[9..0]

SCLK

DAP_MCLK

CLKIN

LRCLK

SDOUT

DAP_MCLK

SPDIF_MCLK

REFCLK_CTRL[3..0]

SCLK

SPDIF_SDOUT

SPDIF_MCLK

RX_M[3..0]

LRCLK

DAP_CTRL

AOUT6

AOUT5

AOUT4

AOUT3

AOUT2

AOUT1

RXPWR

MRESETn

LRCLK

TX_M[2..0]

SDOUT

SCLK

TX_U

TX_C

TX_CBL

RX_C

RX_U

RX_CBL

SDA/CDIN

SCL

AD0/CS

X_RESETn

MUTEC

LRCLK

CLKIN

SCLK

SDOUT

MRESETn

SDIN3

AOUT4

AOUT3

AOUT5

SDIN1

SDIN2

AOUT6

MUTEC

AINR-

AOUT1

AOUT2

FILT

AINL+

AINL-

AINR+

TX_MCLK

RX_ERF

RX_VERFAINR+

AINL-

AINL+

AINR-

DAP_SDIN[3..1]

SDIN3

X_CTRL

RX_VERF

TX_M[2..0]

REFCLK_CTRL[3..0]

LRCLK

RX_M[3..0]

MUTEC

TX_CBL

CLKIN

D[7..0]

SCLK

RX_C

PPRESETn

SDIN2

SDA/CDIN

SDIN1

RX_ERF

TX_C

TX_U SDIN_CTRL

CTRL_MODE

TX_MCLK

AD0/CS

SDIN[3..1]

RX_U

A[1..0]

STATUS[3..0]

RX_CBL SPDIF_SDOUT

AD0/CS

SCL

DAP_SDIN[3..1]

SDA/CDIN

DAP_CTRL

RXPWR

MRESETn

STROBEn

ACKn

MUTE

+12VBUS

MUTE

-12VBUS MRESETn

GND X_RESETn

PPRESETn

MUTEC+5VBUS

SDIN1

SDIN2

SDIN3

SPDIF_SDOUT

DAP_SDIN1

SPDIF_SDOUT

DAP_SDIN2

SPDIF_SDOUT

DAP_SDIN3

SCL

SDIN_CTRL

X_CTRL

CTRL_MODE

SDOUT

MODE_CTRL[9..0]

GND

VCC

GND

GNDGND

VCC

GND

TP16

10uf

TP6

TP8

TP18

TP10

TP20

R98 150

R103 150

47nf

TP23

TP13

R99 150

C12

47nf

TP15

TERMINAL GREEN

TP17

TERMINAL RED

TP25

R100 150

JP3

HEADER 2X2

TERMINAL BLACK

R5 10k

TP19

TERMINAL BLUE

TP3

10uf

R104

TP21

JP11

HEADER 2X2

R6 3.16k

TP22

TP5

PHONO JACK RA

TP24

10uf

JP5

HEADER 2X2

47nf

TP7

R101 150

TP9

TP26

JP6

HEADER 2X2

TP27

TP11

C13

47nf

JP4

HEADER 2X2

TP12

R7 10k

CS4228A-KS

7 22

AOUT1

AOUT2

AOUT3

AOUT4

AOUT5

AOUT6

AINR+

AINR-

AINL+

AINL-

FILT

SCLK

LRCLK

SDIN1

SDIN2

SDIN3

SDOUT

CLKIN

SCL/CCLK

SDA/CDIN

AD0/CS

RESET

MUTEC

DGND AGND

TP14

R102 150

TP4

Figure 1. CDB4228A Top Level Schematic

CDB4228A

10 DS511DB1

+12V

-12V

GND

GNDGND GND

+12V

-12V

GND

R79

10k

R81

10k

R82

8.25k

C81

100pf

U14A

MC33078

8 4

R83

150

U14B

MC33078

C93

100pf

R76

4.99k

-U15A

MC33078

C80

100pf

C84

10uf

R75

150

C88

47nf

C89

10uf

TP86

R87

4.99k

U15B

MC33078

R78

10k

C90

47nf

C82

2.2nf

R80

150

C91

2.2nf

C86

10uf

R77

10k

R84

10k

C87

47nf

R85

10k

R86

10k

C92

100pf R88

150

C85

47nf

C83

47nf

OUTL+

AINL

OUTL-

OUTR+

AINR

OUTR-

Figure 2. Analog Input Filter

CDB4228A

DS511DB1 11

CONTROL PORT MODE SELECT

I2C

CONTROL SOURCE

PPORT

SERIAL CONTROL

SPDIF

DAP/SPDIFnXTERNAL/PPORTnSPI/2wire

MCLK_SEL0

SMODE4

MCLK_SEL1

SMODE0

MCLK_SEL2

SMODE1

TX_MCLK_RATE1

SMODE3

TX_MCLK_RATE0

SMODE2

MODE_CTR L1

MODE_CTR L6

MODE_CTR L3

MODE_CTR L9

MODE_CTR L4

MODE_CTR L8

MODE_CTR L5

MODE_CTR L2

MODE_CTR L7

MODE_CTR L0

GND

VCC

GND

VCC VCC

GND

VCC

VCC VCC

GND

VCC

GREEN LED

R43

374

GREEN LED

SW DPDT

R96

10k

SW SPDT

R44

374

SW SPDT

RP10

10k RPACK9

SW DIP10

9 12

10 11

GREEN LED

R41

33k R42

374

SDOUT_LOAD

X_CTRL SDIN_CTRLCTRL_MO DE

MODE_CTRL[9..0]

Figure 3. External Control

CDB4228A

12 DS511DB1

XTERNAL CONTROL

Digital Audio Port (DAP)

X_DAP_SDIN3

X_DAP_SDIN1

X_DAP_SDIN2

DAP_SDIN1

DAP_SDIN3

X_DAP_SDOUT

X_DAP_SDIN3

DAP_SDIN2 X_DAP_SDIN2

X_DAP_SDIN1

VCC

GND

VCC

GND

C78

47nf C79

47n

R67 33

R69 33

R70 33

C77

47nf

C76

47nf

R71 33

R105 75

JP8

HEADER 10X2

910

11 12

13 14

15 16

17 18

19 20

R68 33

R66 33

TP85

TP84

TP82

R74

10k

TP83

U13

74HC245AW M

DIR

R73 33

R72 33

JP9

HEADER 5X2

910

U12

74HC245AW M

DIR

X_SD A

X_SC L

X_AD0/CS

X_RES ETn

MUTEC

MC LK SCLK

DAP_CTRL

DAP_SDIN[3..1] DAP_SDOUT

LRCLK

Figure 4. Digital Audio Port

CDB4228A

DS511DB1 13

GND

GND-12V

GND

+12V

GND

R13

3.16k R14

3.16k

C117

47nf

TP65

C41

1nf

C38

1nf

R18

3.16k

C39

47nf

C42

47nf

U7A

MC330 78

PHONO JACK RA

2SC3326

R15

604

C43

100pf

C40

10uf

R19

1.78k

R17

3.16k

R16

100k

MU TE

Figure 5. Analog Output Filter 1

CDB4228A

14 DS511DB1

GND

R27

3.16k R28

3.16k

C118

47nf

TP77

C54

1nf

C55

100pf

R31

3.16k

U7B

MC330 78

C52

1nf

J10

PHONO JACK RA

2SC3326

R29

604

C53

10uf

R32

1.78k R33

3.16k

R30

100k

MU TE

Figure 6. Analog Output Filter 2

CDB4228A

DS511DB1 15

GND

GND-12V

GND

+12V

GND

C119

47nf

TP78

R35

3.16k

R34

3.16k

C59

1nf

C56

1nf

R39

3.16k

C57

47nf

C61

100pf

C60

47nf

U10A

MC330 78

J11

PHONO JACK RA

2SC3326

R36

604

C58

10uf

R40

1.78k

R38

3.16k

R37

100k

MUT E

Figure 7. Analog Output Filter 3

CDB4228A

16 DS511DB1

GND

R45

3.16k R46

3.16k

C120

47nf

TP79

C64

1nf

C62

1nf

R49

3.16k

U10B

MC330 78

C65

100pf

J12

PHONO JACK RA

2SC3326

R47

604

C63

10uf

R50

1.78k R51

3.16k

R48

100k

MUT E

Figure 8. Analog Output Filter 4

CDB4228A

DS511DB1 17

GND

GND-12V

GND

+12V

GND

C121

47nf

R53

3.16k

TP80

R52

3.16k

C69

1nf

C71

100pf

C66

1nf

R57

3.16k

C67

47nf

C70

47nf

U11A

MC3307 8

J13

PHONO JACK RA

2SC3326

R54

604

C68

10uf

R58

1.78k

R56

3.16k

R55

100k

MUT E

Figure 9. Analog Output Filter 5

CDB4228A

18 DS511DB1

GND

R59

3.16k R60

3.16k

C122

47nf

TP81

C74

1nf

C72

1nf

R63

3.16k

U11B

MC3307 8

C75

100pf

J14

PHONO JACK RA

2SC3326

R61

604

C73

10uf

R64

1.78k R65

3.16k

R62

100k

MUT E

Figure 10. Analog Output Filter 6

CDB4228A

DS511DB1 19

Mute

100K

100k

10k

10uF C2

3.3nF

From DAC To Amp

Mute Control

Figure 11. Low Cost Analog Output Filter

CDB4228A

20 DS511DB1

PP_nSTROBE

PP_D0

PP_D1

PP_D2

PP_D3

PP_D4

PP_D5

PP_D6

PP_D7

PP_nACK

nBUSY

SELEC T

nAUTOFEED

nERROR

nINIT

nSELECTIN

PP_D0

PP_D1

PP_D2

PP_D3

PP_D4

PP_D5

PP_D6

PP_D7

STATUS 3

STATUS 0

STATUS 2

PP_nACK

STATUS 1

nSELECTIN

nINIT

nAUTOFEED

PP_nSTROBE

nERROR

nBUSY

SELEC T

GND

VCC VCC

VCC

TP88

TP97

TP99

TP101

RP9

22 RPACK8

1 16

2 15

3 14

4 13

5 12

6 11

7 10

8 9

TP89

TP93

TP95

TP91

TP98

RP7

4.7k RPACK8

116

2 15

3 14

4 13

5 12

6 11

7 10

8 9

TP100

TP102

J15

DB25M_R A

RP5

1k RPACK9

RP6

4.7k RPACK8

116

2 15

3 14

4 13

5 12

6 11

7 10

8 9

RP4

1k RPACK9

TP87

RP8

1k RPACK9

TP90

TP92

TP94

TP96

D[7..0]

STATUS[3..0]

ACKn

A[1..0]

RESET n

STROBEn

Figure 12. Control Port Interface

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Cirrus Logic 3CFM User manual

Brand: Cirrus Logic

Model: 3CFM

Category: Remote controls

Type: User manual

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Crystal CDB4228A

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Cirrus Logic 3CFM User manual

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Cirrus Logic 3CFM User manual

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