2019 Microchip Technology Inc. DS50002884A-page 9
SAMA5D3 XPLAINED
4.2.3 Power Supplies
The on-board power supply generation is based on the Active-Semi
®
Power Management Unit (PMU) featuring a 3-channel (3.3V / 1.8V
/1.2V or 1.0V) topology. For maximum efficiency, these supply channels are generated by three integrated step-down converters.
In addition to these 3 DCDC channels, 4 LDO channels with low noise and high PSRR performance are available for the application. These
channels are disabled at startup by default and can be turned on and adjusted under software control through an I²C link. They are also
used to supply the 2.5V VDDFUSE and the 3.3V VDDANA power inputs of the processor.
The power supply sequencing of the three primary channels is controlled by the PMU itself in full compliance with the SAMAD3 require-
ments. The turn-on sequence is: 3.3V first, then 1.8V and finally 1.2V.
Table 4-3 summarizes the power specifications.
There is a known error on the ACT8865 I²C implementation. The port must be shut off after config-
uration or problems may occur with devices using the same I²C channel, e.g., TM43xx LCD display.
Refer to the ACT8865 data sheet at http://www.active-semi.com/ for more details.
This evaluation kit was equipped with an engineering version of ACT8865 PMIC known as
ACT8865QI303-T. The singularity of this engineering version is that OUT4 and OUT5 outputs, nor-
mally enabled at power-up, are disabled at power-up. Consequently, VDDANA and VDDFUSE
power inputs of the processor are OFF when the external reset pin (NRST) is released. They must
therefore be turned on by software in the very first execution steps of the application. In particular,
VDDFUSE is needed to switch SAMA5D3 devices in Secure mode.
The engineering version ACT8865QI303-T of the active semi PMIC is end-of-life (EOL) and replaced
by ACT8865QI305-T devices that have OUT4 and OUT5 enabled by default at power-up. Refer to
the following application note:
https://active-semi.com/wp-content/uploads/ActiveSemi_-ACT8865QI305-
T_versus_ACT8865QI303-T.pdf
Table 4-3: Supply Group Configuration
Nominal Name Power Domains Power Source
3.0V VDDBU
The slow clock oscillator, the internal
32K RC, the internal 12 MHz RC and a part
of the system controller
Optional on-board battery
3.3V VDDIOP0 A part of peripheral I/O lines
PMU
3.3V VDDIOP1 A part of peripheral I/O lines
3.3V VDDUTMII The three USB interfaces
3.3V VDDOSC The main oscillator cells
3.3V VDDANA The analog-to-digital converter
1.2V VDDCORE
The core, including the processor, the
embedded memories and the peripherals