Nuvoton NUC502BDN User manual

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NUC502
Apr 30, 2015 Page 1 of 266 Rev 1.1
ARM
®
ARM7TDMI Based
32-bit Microprocessor
NUC502 Series
User Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
NUC502
Apr 30, 2015 Page 2 of 266 Rev 1.1
Table of Contents
1 General Description 6
2 Features 7
3 Pad and Pin Configuration 9
4 System Diagram 21
5 Block Diagram 22
5.1 System Block Diagram 22
5.2 On-Chip Bus Block Diagram 23
6 Functional Description 24
6.1 ARM7TDMI CPU Core 24
6.2 System Manager 25
6.2.1 Overview 25
6.2.2 System Memory Mapping 25
6.2.3 AHB Bus Arbitration 27
6.2.4 Fixed Priority Mode 27
6.2.5 Power-On Settings 28
6.2.6 System Manager Control Registers 29
6.3 Clock Controller 43
6.3.1 Function Description 43
6.3.2 Clock Control Registers 44
6.4 SPI Synchronous Serial Interface Controller (Master Mode) 56
6.4.1 Overview 56
6.4.2 Features 56
6.4.3 SPIM Timing Diagram 57
6.4.4 SPIM Programming Example without DMA 57
6.4.5 SPIM Programming Example with DMA 58
6.4.6 Direct memory mapping mode 59
6.4.7 SPIM Serial Interface Control Registers Mapping 60
6.5 Audio Processing Unit 73
6.5.1 Overview and Features 73
6.5.2 APU Functional Description 73
6.5.3 AUDIO DAC Clock 73
6.5.4 APU Run Procedures 73
6.5.5 APU Control Register Mapping 74
6.5.6 APU Control Registers 75
6.6 SRAM Controller 83
6.6.1 Overview 83
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Apr 30, 2015 Page 3 of 266 Rev 1.1
6.6.2 Features 83
6.6.3 SRAM Block Diagram 84
6.6.4 SRAM System Diagram 85
6.6.5 SRAM Function Description 86
6.6.6 SRAM Register Mapping 87
6.7 USB Device Controller 91
6.7.1 Overview 91
6.7.2 Features 91
6.7.3 Functional Descriptions 92
6.7.4 Memory Mapping 93
6.7.5 USB Control Registers Mapping 93
6.8 Advanced Interrupt Controller 107
6.8.1 Overview 107
6.8.2 Features 107
6.8.3 Interrupt Sources 108
6.8.4 AIC Functional Descriptions 110
6.8.5 AIC Registers Mapping 112
6.8.6 AIC Control Registers 114
6.9 General Purpose I/O 128
6.9.1 Overview and Features 128
6.9.2 GPIO Control Register Mapping 129
6.9.3 GPIO Control Register Description 130
6.10 I2C Synchronous Serial Interface 149
6.10.1 Overview 149
6.10.2 Features 149
6.10.3 I
2
C Protocol 150
6.10.4 I
2
C Programming Examples 152
6.10.5 Software I
2
C Operation 154
6.10.6 I
2
C Serial Interface Control Registers Mapping 156
6.11 PWM-Timer 164
6.11.1 Introduction 164
6.11.2 Features 165
6.11.3 PWM Timer Start Procedure 165
6.11.4 PWM Architecture 166
6.11.5 Basic Timer Operation 168
6.11.6 PWM Double Buffering and Automatic Reload 168
6.11.7 Modulate Duty Ratio 169
6.11.8 Dead-Zone Generator 170
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Apr 30, 2015 Page 4 of 266 Rev 1.1
6.11.9 PWM Timer Start Procedure 171
6.11.10 PWM Timer Stop Procedure 171
6.11.11 PWM Timer Register Mapping 173
6.11.12 Register Description 173
6.12 Real Time Clock (RTC) 190
6.12.1 Overview 190
6.12.2 RTC Features 190
6.12.3 RTC Function Description 191
6.12.4 RTC Register Mapping 193
6.12.5 RTC Register Descriptions 194
6.13 Serial Peripheral Interface Controller (SPI Master/Slave) 207
6.13.1 SPI Function Description and Features 207
6.13.2 SPIMS Timing Diagram 208
6.13.3 SPIMS Programming Example 209
6.13.4 SPIMS Serial Interface Control Register Map 211
6.13.5 SPIMS Control Register Description 212
6.14 Timer Controller 218
6.14.1 General Timer Controller 218
6.14.2 Watchdog Timer 218
6.14.3 Timer Control Registers Map 220
6.15 UART Interface Controller 229
6.15.1 Overview 229
6.15.2 Features 229
6.15.3 Block Diagram 230
6.15.4 Functional Blocks Descriptions 230
6.15.5 Finite State Machine 231
6.15.6 UART Interface Control Registers Mapping 235
6.16 Analog to Digital Converter 250
6.16.1 Features 250
6.16.2 ADC Functional Description 250
6.16.3 ADC Control Register Mapping 251
6.16.4 ADC Control Register Description 253
7 Electrical Characteristics 260
7.1 Absolute Maximum Ratings 260
7.2 DC Specifications 260
7.3 AC Specifications 261
7.3.1 Audio DAC Characteristic 261
7.3.2 ADC Characteristic 261
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Apr 30, 2015 Page 5 of 266 Rev 1.1
7.3.3 Voice Recorder Characteristic 261
8 Package Specifications 262
9 REVISION HISTORY 265
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Apr 30, 2015 Page 6 of 266 Rev 1.1
1 General Description
The NUC502 is an ARM7TDMI-based MCU, specifically designed to offer low-cost and
high performance for various applications, like interactive toys, edutainment robots, and
home appliances. It integrates the 32-bit RISC CPU with 64KB high-speed SRAM, crypto
engine with OTP key, boot ROM, LDO regulator, ADC, DAC, I2C, SPI, USB2.0 FS Device, &
GPIO into a cost-affordable while feature-rich micro-controller.
Owing to the simplicity of the NUC502 architecture that boots SpiMemory into the high-
speed SRAM for program execution, the total system BOM is reduced to its minimum. Unlike
usual ARM-based MCU products, the NUC502 operates without the use of SDRAM, which is
usually the source of complexity, higher power consumption, and cost.
The ARM7TDMI runs up to 81MHz on the high-speed SRAM to offer enough horsepower
for many MIPS-hungry tasks, while the remaining MIPS is still able to serve the need of
application program. For those applications, like cartridge games, that require large code
storage and variation of game play scenarios, the patented Extensible XIP Addressing on
SpiMemory gives the flexibility whenever program execution speed is not a critical concern.
To protect the code against illegal pirating, the NUC502 provides a crypto engine that
works with internal OTP2 key to encrypt the data stored at external SpiMemory when the
design-in is finished. Without the knowledge of the OTP key, others can’t decrypt the data
even by means of ICE debugging.
The NUC502 is designed with special care to minimize the power consumption while
allowing for the flexibility to reach for high performance. It includes the clock gating,
variable frequency control for individual IP’s, and bus control to reduce signal toggle.
Besides, the NUC502 can be further operated under different power-saving modes: idle,
power down with RTC active, and power down mode.
With so many practical peripherals integrated around the high-performance ARM7 CPU,
the NUC502 is suitable for such applications as Interactive toys, edutainment robots, and
home appliances. Whenever MIPS-hungry task meets cost-effective demand, you’ll find the
NUC502 truly useful to satisfy the requirement.
NUC502
Apr 30, 2015 Page 7 of 266 Rev 1.1
2 Features
32-bit RISC CPU
ARM7TDMI @ 81 MHz
16-bit Thumb mode supported to save code size
Embedded 64 KB Local Memory divided into 32 segments for easier S/W
programming
Boot from SpiMemory or USB
Program download into SRAM through JTAG before OTP key programmed
Integrate JTAG port to support real time, non-stop ICE function for system
development and debugging
6KB internal ROM
Boot loader
ICP for SpiFlash & security OTP key via USB
64KB internal SRAM
Embedded 64KB SRAM for code and data
32 segments with address tags
SpiMemory interface with code protection
DMA mode for code booting from SpiMemory to internal SRAM
Direct CPU read access from SpiMemory
128-bit OTP key for code protection against illegal pirating
2-bit SPI mode supported for doubling data transfer rate
Shared (when not in use) with other SPI device for high-speed transfer via DMA
Audio Process Unit
Mono 16-bit Sigma-Delta DAC output
Equalization function supported
USB 2.0 Full speed device
6 programmable endpoints for Control, Bulk In/Out, Interrupt and Isochronous
transfers
512-byte buffer
Auto suspend function
Remote wakeup capability
I
2
C
Compatible with Philips I
2
C standard
Master mode
SPI
Programmable master/slave mode
Speed up to 40MHz
NUC502
Apr 30, 2015 Page 8 of 266 Rev 1.1
4 Channel PWM
Four 16-bit timers
Programmable duty control of output waveform (PWM)
Auto reload mode or one-shot pulse mode
Capture and compare function
Analog to Digital Converter
10-bit x 8-ch ADC for sensor, MIC, LVD, LVR
Maximum conversion rate: 400K samples per second
Power supply voltage: 3.3V
Analog input voltage range: 0 ~ 3.3 volts
Support wait-for-trigger mode & standby mode
Dedicated LVD/LVR
8-level voltage detection
Miscellaneous
Two programmable 32-bit timers with 8-bit pre-scale
One 32-bit watch dog timer
32.768KHz RTC function support
Up to 26/37 GPIO pins for LQFP-48 / LQFP-64
Two UART ports with flow control (TX, RX, CTS and RTS) and UART0 is for high
speed
Power management modes: normal, idle, power down with RTC, and power down
3.3V to 1.8V 200mA LDO regulator
Software Support
GNU-based, open-source IDE: compiler, linker and debugger
Technology & Package
0.18um CMOS
3.3-volt single supply
Dice form (NUC502)/LQFP-48 (NUC502ADN)/ LQFP-64 ( 10x10mm NUC502BDN) /
LQFP-64 (7x7mm NUC502CDN)
NUC502
Apr 30, 2015 Page 9 of 266 Rev 1.1
3 Pad and Pin Configuration
LQFP-48 Pin Out
NUC502ADN
NUC502
Apr 30, 2015 Page 10 of 266 Rev 1.1
LQFP-64 Pin Out
NUC502BDN
NUC502CDN
NUC502
Apr 30, 2015 Page 11 of 266 Rev 1.1
Pin Descriptions
In order to maximize the NUC502 application for different field, each pin of NUC502 is
very flexible and can play up to four different functions. The user can program each pin to
the wanted function for the different product.
The pin functions are controlled by the registers PAD_REG0, PAG_REG1 and PAD_REG2.
For each multiple function pin, the default function is the GPIO. When the user programs
the PAD_REG, the pins play the alternative function. If the different alternative functions are
enabled simultaneous, the priority is
Alternative Function 1 > Alternative Function 2 > Alternative Function 3 > Default
Function
For example:
If the GPA[12] is configured to be SPIMS_SO by PAD_REG1 and it is also configured to
be PWMT0 by PAD_REG0, the actual function of GPA[12] would be SPIMS_SO because the
SPIMS_SO function priority is higher than PWMT0.
Except the multiple functions, each NUC502 output driving current strength is also
controllable. The driving strength control register is the GPA_DS, GPB_DS and GPC_DS. For
different pin the driving can be 4mA or 8mA and 12mA or 16mA. For example, user can
control the GPB[1] strength to 16mA and directed drive the high current LED to save PCB
extra component to reduce the BOM cost.
Default
Function
Name
Alternative
Function 1
Alternative
Function 2
Alternative
Function 3
Power on
setting
GPIO
GPA[0]
AI[0]
MIC+
GPA[1]
AI[1]
MIC-
GPA[2]
AI[2]
GPA[3]
AI[3]
GPA[4]
AI[4]
GPA[5]
AI[5]
GPA[6]
AI[6]
GPA[7]
AI[7]
LVD
SPIM0_SS(Master)
NUC502
Apr 30, 2015 Page 12 of 266 Rev 1.1
Default
Function
Name
Alternative
Function 1
Alternative
Function 2
Alternative
Function 3
Power on
setting
GPA[8]
SPIM0_SCK
Power on set (IBR)
GPA[9]
SPIM0_SO
Power on set (IBR)
GPA[10]
SPIM0_SI
GPA[11]
SPIMS_SI
GPA[12]
SPIMS_SO
PWMT0
Power on set (IBR)
GPA[13]
SPIMS_SCK
PWMT1
Power on set
(48/64)
GPA[14]
SPIMS_SS(Slave)
USB_DET
GPA[15]
PWMT2
USB_DET
I2C_DATA
GPB[0]
PWMT3
USB_DET
I2C_CLK
GPB[1]
PWMT0
USB_DET
UART0_TXD
Power on set (ICE)
GPB[2]
PWMT1
USB_DET
UART0_RXD
GPB[3]
PWMT2
USB_DET
UART0_CTS
GPB[4]
PWMT3
USB_DET
UART0_RTS
Power on set (SPI_S0)
GPB[5]
TCK
SPIM1_SI
GPB[6]
TMS
SPIM1_SO
PWMT2
GPB[7]
TDI
SPIM1_SCK
PWMT3
GPB[8]
TDO
USB_DET
PWMT0
Power on set (SPI_S1)
GPB[9]
nTRST
USB_DET
PWMT1
Audio DAC
AO_OUT0
AO_REF18
AO_VREF
USB2.0 Device
USB_DP
USB_DM
MISC
nRESET
NUC502
Apr 30, 2015 Page 13 of 266 Rev 1.1
Default
Function
Name
Alternative
Function 1
Alternative
Function 2
Alternative
Function 3
Power on
setting
X12M
EX12M
X32K
EX32K
POWER
VPP (6.5V)
VBAT
USBVDD33
DVDD33
DVDD33
AVDD33
DVSS
DVSS
DVSS
AVSS
VCC_CORE
(OUTPUT)
Pin Function for LQFP 64
TCK
TMS
TDI
TDO
nTRST
GPC[0]
SPIM1_SO
USB_DET
GPC[1]
SPIM1_SI
USB_DET
GPC[2]
SPIM1_SCK
USB_DET
GPC[3]
PWMT0
USB_DET
GPC[4]
PWMT1
USB_DET
NUC502
Apr 30, 2015 Page 14 of 266 Rev 1.1
Default
Function
Name
Alternative
Function 1
Alternative
Function 2
Alternative
Function 3
Power on
setting
GPC[5]
PWMT2
UART1_TXD
GPC[6]
PWMT3
UART1_RXD
GPC[7]
PWMT0
UART1_CTS
GPC[8]
PWMT1
UART1_RTS
GPC[9]
PWMT2
I2C_DATA
GPC[10]
PWMT3
I2C_CLK
Table4.1 Pin function
NUC502
Apr 30, 2015 Page 15 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
79
62
46
4/8mA I/O
with
Analog input
GPA[0] General purpose
input/output digital pin
AI[0] ADC analog input 0
MICP MIC+
80
63
47
4/8mA I/O
with
Analog input
GPA[1] General purpose
input/output digital pin
AI[1] ADC analog input 1
MICN MIC-
81
64
48
4/8mA I/O
with
Analog input
GPA[2] General purpose
input/output digital pin
AI[2] ADC analog input 2
2
1
1
4/8mA I/O
with
Analog input
GPA[3] General purpose
input/output digital pin
AI[3] ADC analog input 3
3
2
2
4/8mA I/O
with
Analog input
GPA[4] General purpose
input/output digital pin
AI[4] ADC analog input 4
4
3
3
4/8mA I/O
with
Analog input
GPA[5] General purpose
input/output digital pin
AI[5] ADC analog input 5
5
4
4
4/8mA I/O
with
Analog input
GPA[6] General purpose
input/output digital pin
AI[6] ADC analog input 6
6
5
5
4/8mA I/O
with
Analog input
GPA[7] General purpose
input/output digital pin
AI[7] ADC analog input 7
LVD Low voltage detection
42
33
26
4/8mA
I/O
GPA[8] General purpose
input/output digital pin
SPIM0_SCK - Serial clock
output pin for SPIM0
41
32
25
4/8mA
I/O
GPA[9] General purpose
input/output digital pin
SPIM0_SO - Serial data
input/output pin for SPIM0.
Normal SPI mode, this pin is
used as data out.
Fast SPI read mode, this pin is
the 2
nd
bit for data in.
40
31
24
4/8mA
I/O
GPA[10] General purpose
input/output digital pin
SPIM0_SI - Serial data input
pin for SPIM0.
39
30
23
4/8mA
I/O
GPA[11] General purpose
input/output digital pin
SPIMS_SI - Serial data input
pin for SPIMS.
38
29
22
4/8mA
GPA[12] General purpose
NUC502
Apr 30, 2015 Page 16 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
I/O
input/output digital pin
SPIMS_SO - Serial data output
pin for SPIMS.
PWMT0 PWM output for timer
0
37
28
21
4/8mA
I/O
GPA[13] General purpose
input/output digital pin
SPIMS_SCK - Serial clock pin
for SPIMS (master/slave).
PWMT1 PWM output for timer
1
36
27
20
4/8mA
I/O
GPA[14] General purpose
input/output digital pin
SPIMS_SS - Serial chip select
pin for SPIMS slave mode.
USB_DET USB detected pin
35
26
19
4/8mA
I/O
GPA[15] General purpose
input/output digital pin
PWMT2 PWM output for timer
2
USB_DET USB detected pin
I2C_DATA I2C data
input/output pin, if this pin is
select for I2C function
34
25
18
4/8mA
I/O
GPB[0] General purpose
input/output digital pin
PWMT3 PWM output for timer
3
USB_DET USB detected input
I2C_CLK_ I2C data output
pin, if this pin is select for I2C
function
31
24
17
12/16mA
I/O
GPB[1] General purpose
input/output digital pin
PWMT0 PWM output for timer
0
USB_DET USB detected input
UART0_TXD Data transmitter
output pin for UART0 (High
speed)
30
23
16
12/16mA
I/O
GPB[2] General purpose
input/output digital pin
PWMT1 PWM output for timer
1
USB_DET USB detected input
UART0_RXD Data receiver
input pin for UART0 (High
speed)
29
22
15
12/16mA
I/O
GPB[3] General purpose
input/output digital pin
NUC502
Apr 30, 2015 Page 17 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
PWMT2 PWM output for timer
2 c
USB_DET USB detected input
UART0_CTS Clear to Send
input pin for UART0 (High
speed)
28
21
14
12/16mA
I/O
GPB[4] General purpose
input/output digital pin
PWMT3 PWM output for timer
3
USB_DET USB detected input
UART0_RTS Request to Send
output pin for UART0 (High
speed)
20
16
11
12/16mA
I/O
GPB[5] General purpose
input/output digital pin
TCK - JTAG ICE Test Clock pin
(LQFP48 only)
SPI2_SI_A Serial data input
pin for SPIM1 (master)
18
14
10
12/16mA
I/O
GPB[6] General purpose
input/output digital pin
TMS - JTAG ICE Test Mode
Select pin (LQFP48 only)
SPI2_SO Serial data output
pin for SPIM1 (master)
PWMT2 PWM output for timer
2c
15
12
9
12/16mA
I/O
GPB[7] General purpose
input/output digital pin
TDI JTAG ICE TDO pin
(LQFP48 only)
SPIM1_SCK Serial clock
output pin for SPIM1 (master)
PWMT3 PWM output for timer
3
13
10
8
12/16mA
I/O
GPB[8] General purpose
input/output digital pin
TDO JTAG ICE TDO interface
(LQFP48 only)
USB_DET USB detected input
PWMT0 PWM output for timer
0
10
8
7
4/8mA
I/O
GPB[9] General purpose
input/output digital pin
nTRST JTAG ICE reset pin
(LQFP48 only)
USB_DET USB detected input
PWMT1 PWM output for timer
1
NUC502
Apr 30, 2015 Page 18 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
54
42
4/8mA
I/O
GPC[0] General purpose
input/output digital pin
SPIM1_SO Serial data output
pin for SPIM1 (master)
USB_DET USB detected input
55
43
4/8mA
I/O
GPC[1] General purpose
input/output digital pin
SPIM1_SI Serial data input
pin for SPIM1 (master)
USB_DET USB detected input
56
44
4/8mA
I/O
GPC[2] General purpose
input/output digital pin
SPIM1_SCK Serial clock
output pin for SPIM1 (master)
USB_DET USB detected input
59
47
4/8mA
I/O
GPC[3] General purpose
input/output digital pin
PWMT0 PWM output for timer
0
USB_DET USB detected input
60
48
4/8mA
I/O
GPC[4] General purpose
input/output digital pin
PWMT1 PWM output for timer
1
USB_DET USB detected input
75
58
4/8mA
I/O
GPC[5] General purpose
input/output digital pin
PWMT2 PWM output for timer
2
UART1_TXD Data transmitter
output pin for UART1
76
59
4/8mA
I/O
GPC[6] General purpose
input/output digital pin
PWMT3 PWM output for timer
3
UART1_RXD Data Receiver
input pin for UART1
77
60
4/8mA
I/O
GPC[7] General purpose
input/output digital pin
PWMT0 PWM output for timer
0
UART1_CTS Clear to Send
input pin for UART1
78
61
4/8mA
I/O
GPC[8] General purpose
input/output digital pin
PWMT1 PWM output for timer
1
UART1_RTS Request to Send
output pin for UART1
25
19
4/8mA
GPC[9] General purpose
NUC502
Apr 30, 2015 Page 19 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
I/O
input/output digital pin
PWMT2 PWM output for timer
2
I2C_DATA I2C data
input/output pin, if this pin is
select for I2C function
26
20
4/8mA
I/O
GPC[10] General purpose
input/output digital pin
PWMT3 PWM output for timer
3
I2C_CLK_ I2C data output
pin, if this pin is select for I2C
function
44
34
27
8mA
O
Chip Select pin for SPIM0, the
SPIM0 is used for SPI memory
50
39
32
I/O
USB device signal D+
51
40
33
I/O
USB device signal D-
57
45
35
I
Crystal input pin
58
46
36
O
Crystal output pin
45
35
28
I
RTC 32.768KHz crystal input
pin
46
36
29
O
RTC 32.768KHz crystal output
pin
8
6
6
I
External reset input Low
active, set this pin low reset
the NUC502 to the chip initial
state
19
15
I
JTAG ICE Test Clock pin
17
13
I
JTAG ICE Test Mode Select pin
9
7
I
JTAG ICE Reset pin
12
9
8mA
O
JTAG ICE TDO interface
14
11
I
JTAG ICE TDI interface
70
54
42
AO
Audio DAC output pin
68,6
9
53
41
AI
1.8V power for analog circuit
71
55
43
AO
Analog circuit voltage reference
pin
7,
16,
21,2
2,32,
48,
49,
63,
17, 38,
50
12, 31,
38
I
3.3V power supply for I/O
ports and LDO source for
internal PLL and digital circuit
NUC502
Apr 30, 2015 Page 20 of 266 Rev 1.1
COB
LQFP64
LQFP48
TYPE
Description
64
74
57
45
3.3V power supply for internal
analog circuit
47
37
30
1.8V Power supply for internal
RTC circuit
65,
66
51
39
LDO 1.8V output pin
67
52
40
OTP 6.5V VPP pin. For OTP
write, this pin supply is 6.5V
for read, this pin supply is 1.8V
1,
11,
23,
24,
27,
33,
44,
52,
53,
61,
62
18, 41,
49
13, 34,
37
Ground Pin for digital circuit
73
56
44
Ground Pin for analog circuit
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Nuvoton NUC502BDN User manual

Type
User manual
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