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NXP
S08RN
NXP S08RN Reference guide
Type
Reference guide
Brand
NXP
Size
5.87 MB
Pages
591
Language
English
Table of contents
Power (VDD, VSS)
39
Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)
40
Oscillator (XTAL, EXTAL)
40
External reset pin (RESET)
41
Background/mode select (BKGD/MS)
41
Port A input/output (I/O) pins (PTA7–PTA6 and PTA3–PTA0)
42
Port B input/output (I/O) pins (PTB7–PTB0)
42
Port C input/output (I/O) pins (PTC7–PTC0)
42
Port D input/output (I/O) pins (PTD7–PTD0)
43
Port E input/Output (I/O) pins (PTE–PTE0)
43
True open drain pins (PTA3–PTA2)
43
High current drive pins (PTB4, PTB5, PTD0, PTD1)
43
Peripheral pinouts
44
Run mode
47
Wait mode
48
Stop3 mode
48
Active BDM enabled in stop3 mode
48
LVD enabled in stop mode
49
Power modes behaviors
49
Power-on reset (POR) operation
51
LVD reset operation
51
Low-voltage warning (LVW)
51
PMC
52
PMC_SPMSC1
52
PMC_SPMSC2
54
Overview
68
Function descriptions
70
Modes of operation
70
Wait mode
70
Stop mode
70
Flash and EEPROM memory map
70
Flash and EEPROM initialization after system reset
71
Flash and EEPROM command operations
71
Writing the FCLKDIV register
73
Command write sequence
75
Flash and EEPROM interrupts
77
Description of flash and EEPROM interrupt operation
77
Protection
78
Security
81
Unsecuring the MCU using backdoor key access
81
Unsecuring the MCU using BDM
82
Mode and security effects on flash and EEPROM command availability
83
Flash and EEPROM commands
83
Flash commands
83
EEPROM commands
84
Allowed simultaneous flash and EEPROM operations
84
Flash and EEPROM command summary
85
Erase verify all blocks command
86
Erase verify block command
86
Erase verify flash section command
87
Read once command
88
Program flash command
89
Program once command
90
Erase all blocks command
91
Erase flash block command
92
Erase flash sector command
92
Unsecure flash command
93
Verify backdoor access key command
94
Set user margin level command
95
Erase verify EEPROM section command
96
Program EEPROM command
97
Erase EEPROM sector command
98
NVM
99
NVM_FCLKDIV
99
NVM_FSEC
100
NVM_FCCOBIX
101
NVM_FCNFG
102
NVM_FERCNFG
103
NVM_FSTAT
103
NVM_FERSTAT
104
NVM_FPROT
105
NVM_EEPROT
106
NVM_FCCOBHI
108
NVM_FCCOBLO
108
NVM_FOPT
108
SCI0 pin reassignment
112
SPI0 pin reassignment
112
IIC pins reassignments
112
FTM0 channels pin reassignment
113
FTM2 channels pin reassignment
113
Bus clock output pin enable
113
SCI0 TxD modulation
114
SCI0 RxD capture
115
SCI0 RxD filter
115
FTM2 software synchronization
115
ADC hardware trigger
116
SYS
116
SYS_SRS
117
SYS_SBDFR
119
SYS_SDIDH
119
SYS_SDIDL
120
SYS_SOPT1
120
SYS_SOPT2
122
SYS_SOPT3
123
SYS_SOPT4
124
SYS_ILLAH
124
SYS_ILLAL
125
SYS_UUID1
126
SYS_UUID2
126
SYS_UUID3
127
SYS_UUID4
127
SYS_UUID5
128
SYS_UUID6
128
SYS_UUID7
129
SYS_UUID8
129
PORT
135
PORT_PTAD
136
PORT_PTBD
137
PORT_PTCD
138
PORT_PTDD
138
PORT_PTED
139
PORT_HDRVE
139
PORT_PTAOE
140
PORT_PTBOE
141
PORT_PTCOE
142
PORT_PTDOE
144
PORT_PTEOE
145
PORT_PTAIE
146
PORT_PTBIE
147
PORT_PTCIE
148
PORT_PTDIE
149
PORT_PTEIE
151
PORT_IOFLT0
152
PORT_IOFLT1
153
PORT_IOFLT2
153
PORT_FCLKDIV
154
PORT_PTAPE
155
PORT_PTBPE
156
PORT_PTCPE
157
PORT_PTDPE
159
PORT_PTEPE
160
Function description
165
Bus frequency divider
166
Low power bit usage
166
Internal reference clock (ICSIRCLK)
166
Fixed frequency clock (ICSFFCLK)
167
BDC clock
168
Modes of operation
168
FLL engaged internal (FEI)
169
FLL engaged external (FEE)
169
FLL bypassed internal (FBI)
169
FLL bypassed internal low power (FBILP)
170
FLL bypassed external (FBE)
170
FLL bypassed external low power (FBELP)
171
Stop (STOP)
171
Initializing FEI mode
173
Initializing FBI mode
173
Initializing FEE mode
173
Initializing FBE mode
174
External oscillator (OSC)
174
Bypass mode
175
Low-power configuration
175
High-gain configuration
176
Initializing external oscillator for peripherals
176
ICS
178
ICS_C1
178
ICS_C2
179
ICS_C3
180
ICS_C4
180
ICS_S
181
ICS_OSCSC
182
SCG
183
SCG_C1
184
SCG_C2
185
SCG_C3
186
SCG_C4
187
Central processor unit (CPU)
189
Debug module (DBG)
189
Watchdog (WDOG)
190
Random-access-memory (RAM)
192
Non-volatile memory (NVM)
192
Cyclic redundancy check (CRC)
193
FlexTimer module (FTM)
195
FTM0 interconnection
196
8-bit modulo timer (MTIM)
197
MTIM0 as ADC hardware trigger
198
Real-time counter (RTC)
199
Serial communications interface (SCI)
201
Inter-Integrated Circuit (I2C)
203
Analog-to-digital converter (ADC)
205
ADC channel assignments
206
Alternate clock
207
Hardware trigger
208
Temperature sensor
208
Analog comparator (ACMP)
209
ACMP configuration information
210
ACMP in stop3 mode
211
ACMP for SCI0 RXD filter
211
Keyboard interrupts (KBI)
211
Touch sense input (TSI)
213
TSI channel assignments
214
Hardware trigger
215
Features
217
Accumulator (A)
218
Index Register (H:X)
219
Stack Pointer (SP)
219
Program Counter (PC)
220
Condition Code Register (CCR)
220
Inherent Addressing Mode (INH)
222
Relative Addressing Mode (REL)
222
Immediate Addressing Mode (IMM)
222
Direct Addressing Mode (DIR)
223
Extended Addressing Mode (EXT)
223
Indexed Addressing Mode
224
Indexed, No Offset (IX)
224
Indexed, No Offset with Post Increment (IX+)
224
Indexed, 8-Bit Offset (IX1)
224
Indexed, 8-Bit Offset with Post Increment (IX1+)
225
Indexed, 16-Bit Offset (IX2)
225
SP-Relative, 8-Bit Offset (SP1)
225
SP-Relative, 16-Bit Offset (SP2)
226
Memory to memory Addressing Mode
226
Direct to Direct
226
Immediate to Direct
227
Indexed to Direct, Post Increment
227
Direct to Indexed, Post-Increment
227
Stop mode
227
Wait mode
228
Background mode
228
Security mode
229
Reset Sequence
231
Interrupt Sequence
231
Features
245
Modes of Operation
245
KBI in Wait mode
245
KBI in Stop modes
246
Block Diagram
246
Edge-only sensitivity
250
Edge and level sensitivity
250
KBI Pullup Resistor
250
KBI initialization
250
FlexTimer philosophy
253
Features
254
Modes of operation
255
Block diagram
255
EXTCLK — FTM external clock
258
CHn — FTM channel (n) I/O pin
258
FAULTj — FTM fault input
258
Module memory map
259
Register descriptions
259
Clock Source
289
Counter Clock Source
289
Prescaler
290
Counter
290
Up counting
290
Up-down counting
293
Free running counter
294
Counter reset
295
Input capture mode
295
Filter for input capture mode
296
Output compare mode
297
Edge-aligned PWM (EPWM) mode
299
Center-aligned PWM (CPWM) mode
301
Combine mode
303
Asymmetrical PWM
310
Complementary mode
310
Update of the registers with write buffers
311
CNTINH:L registers
311
MODH:L registers
311
CnVH:L registers
312
PWM synchronization
313
Hardware trigger
313
Software trigger
314
Boundary cycle
315
MODH:L registers synchronization
316
CnVH:L registers synchronization
318
OUTMASK register synchronization
318
FTM counter synchronization
320
Summary of PWM synchronization
322
Deadtime insertion
324
Deadtime insertion corner cases
325
Output mask
327
Fault control
328
Automatic fault clearing
330
Manual fault clearing
331
Polarity control
331
Initialization
332
Features priority
332
Channel trigger output
332
Initialization trigger
333
Capture test mode
335
Dual edge capture mode
336
One-shot capture mode
338
Continuous capture mode
338
Pulse width measurement
339
Period measurement
341
Read coherency mechanism
343
TPM emulation
345
MODH:L and CnVH:L synchronization
345
Free running counter
345
Write to SC
345
Write to CnSC
345
BDM mode
345
Timer overflow interrupt
348
Channel (n) interrupt
348
Fault interrupt
348
MTIM in wait mode
350
MTIM in stop mode
350
MTIM in active background mode
350
MTIM operation example
355
Modes of operation
357
Wait mode
357
Stop modes
358
Block diagram
358
RTC
359
RTC_SC1
359
RTC_SC2
360
RTC_MODH
361
RTC_MODL
361
RTC_CNTH
361
RTC_CNTL
362
RTC operation example
363
Features
367
Modes of operation
367
Block diagram
368
Detailed signal descriptions
370
Baud rate generation
381
Transmitter functional description
382
Send break and queued idle
382
Receiver functional description
383
Data sampling technique
384
Receiver wake-up operation
385
Idle-line wakeup
385
Address-mark wakeup
386
Interrupts and status flags
386
Baud rate tolerance
387
Slow data tolerance
388
Fast data tolerance
389
Additional SCI functions
390
8- and 9-bit data modes
390
Stop mode operation
390
Loop mode
391
Single-wire operation
391
Features
393
Modes of operation
394
Block diagrams
394
SPI system block diagram
395
SPI module block diagram
395
SPSCK — SPI Serial Clock
397
MOSI — Master Data Out, Slave Data In
397
MISO — Master Data In, Slave Data Out
397
SS — Slave Select
397
General
405
Master mode
405
Slave mode
407
SPI clock formats
408
SPI baud rate generation
411
Special features
411
SS Output
411
Bidirectional mode (MOMI or SISO)
412
Error conditions
413
Mode fault error
413
Low-power mode options
414
SPI in Run mode
414
SPI in Wait mode
414
SPI in Stop mode
415
Reset
415
Interrupts
416
MODF
416
SPRF
416
SPTEF
417
SPMF
417
Initialization sequence
417
Pseudo-Code Example
418
Features
421
Modes of operation
422
Block diagram
422
I2C
424
I2C_A1
424
I2C_F
425
I2C_C1
426
I2C_S
427
I2C_D
429
I2C_C2
430
I2C_FLT
431
I2C_RA
431
I2C_SMB
432
I2C_A2
433
I2C_SLTH
434
I2C_SLTL
434
I2C protocol
434
START signal
435
Slave address transmission
436
Data transfers
436
STOP signal
437
Repeated START signal
437
Arbitration procedure
437
Clock synchronization
438
Handshaking
438
Clock stretching
438
I2C divider and hold values
439
10-bit address
440
Master-transmitter addresses a slave-receiver
440
Master-receiver addresses a slave-transmitter
441
Address matching
442
System management bus specification
442
Timeouts
442
SCL low timeout
443
SCL high timeout
443
CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
443
FAST ACK and NACK
444
Resets
445
Interrupts
445
Byte transfer interrupt
446
Address detect interrupt
446
Exit from low-power/stop modes
446
Arbitration lost interrupt
446
Timeout interrupt in SMBus
447
Programmable input glitch filter
447
Address matching wake-up
448
Features
453
Block Diagram
454
Analog Power (VDDA)
455
Analog Ground (VSSA)
455
Voltage Reference High (VREFH)
455
Voltage Reference Low (VREFL)
455
Analog Channel Inputs (ADx)
455
ADC
456
ADC_SC1
456
ADC_SC2
458
ADC_SC3
459
ADC_SC4
460
ADC_RH
461
ADC_RL
462
ADC_CVH
463
ADC_CVL
463
ADC_APCTL1
464
ADC_APCTL2
465
Clock select and divide control
466
Input select and pin control
467
Hardware trigger
467
Conversion control
468
Initiating conversions
468
Completing conversions
468
Aborting conversions
469
Power control
469
Sample time and total conversion time
470
Automatic compare function
471
FIFO operation
472
MCU wait mode operation
475
MCU Stop3 mode operation
476
Stop3 mode with ADACK disabled
476
Stop3 mode with ADACK enabled
476
ADC module initialization example
477
Initialization sequence
477
Pseudo-code example
478
ADC FIFO module initialization example
478
Pseudo-code example
479
External pins and routing
480
Analog supply pins
480
Analog reference pins
480
Analog input pins
481
Sources of error
482
Sampling error
482
Pin leakage error
482
Noise-induced errors
482
Code width and quantization error
483
Linearity errors
484
Code jitter, non-monotonicity, and missing codes
485
Features
487
Modes of operation
487
Operation in Wait mode
488
Operation in Stop3 mode
488
Operation in Debug mode
488
Block diagram
488
ACMP
489
ACMP_CS
489
ACMP_C0
490
ACMP_C1
491
ACMP_C2
492
Features
495
Modes of operation
496
Block diagram
496
TSI[15:0]
497
TSI
497
TSI_CS0
498
TSI_CS1
499
TSI_CS2
501
TSI_CS3
502
TSI_PEN0
502
TSI_PEN1
504
TSI_CNTH
505
TSI_CNTL
505
Capacitance measurement
506
TSI electrode oscillator
506
Electrode oscillator and counter module control
507
TSI reference oscillator
508
TSI measurement result
509
Enable TSI module
509
Software and hardware trigger
509
Scan times
510
Clock setting
510
Reference voltage
510
Current source
511
Pin enable
511
End of scan
511
Noise detection mode
512
CRC
516
CRC_D0
517
CRC_D1
517
CRC_D2
518
CRC_D3
519
CRC_P0
519
CRC_P1
520
CRC_P2
520
CRC_P3
521
CRC_CTRL
521
16-bit CRC calculation
522
32-bit CRC calculation
522
Bit reverse
523
Result complement
523
CCITT compliant CRC example
523
Features
525
Block diagram
526
WDOG
527
WDOG_CS1
527
WDOG_CS2
529
WDOG_CNTH
530
WDOG_CNTL
530
WDOG_TOVALH
531
WDOG_TOVALL
531
WDOG_WINH
532
WDOG_WINL
532
Watchdog refresh mechanism
533
Window mode
534
Refreshing the Watchdog
534
Example code: Refreshing the Watchdog
535
Configuring the Watchdog
535
Reconfiguring the Watchdog
535
Unlocking the Watchdog
536
Example code: Reconfiguring the Watchdog
536
Clock source
536
Using interrupts to delay resets
538
Backup reset
538
Functionality in debug and low-power modes
538
Fast testing of the watchdog
539
Testing each byte of the counter
539
Entering user mode
540
Forcing active background
541
Features
541
BKGD pin description
543
Communication details
544
BDC commands
546
BDC hardware breakpoint
549
Comparators A and B
550
Bus capture information and FIFO operation
550
Change-of-flow information
551
Tag vs. force breakpoints and triggers
552
Trigger modes
553
Hardware breakpoints
554
BDC
555
BDC_SCR
555
BDC_BKPTH
557
BDC_BKPTL
558
BDC_SBDFR
558
Features
561
Modes of operation
562
Block diagram
562
DBG
564
DBG_CAH
564
DBG_CAL
565
DBG_CBH
566
DBG_CBL
566
DBG_CCH
567
DBG_CCL
568
DBG_FH
568
DBG_FL
569
DBG_CAX
570
DBG_CBX
571
DBG_CCX
572
DBG_FX
573
DBG_C
573
DBG_T
574
DBG_S
576
DBG_CNT
577
Comparator
578
RWA and RWAEN in full modes
578
Comparator C in loop1 capture mode
578
Breakpoints
579
Hardware breakpoints
579
Trigger selection
580
Trigger break control (TBC)
580
Begin- and end-trigger
581
Arming the DBG module
581
Trigger modes
582
A only
582
A or B
582
A then B
582
Event only B
582
A then event only B
582
A and B (full mode)
582
A and not B (full mode)
583
View document
NXP S08RN Reference guide
Type
Reference guide
Brand
NXP
Size
6.59 MB
Pages
651
Language
English
Table of contents
Power (VDD, VSS)
42
Analog power supply and reference pins (VDDA/VREFH and VSSA/VREFL)
43
Oscillator (XTAL, EXTAL)
44
External reset pin (RESET)
45
Background/mode select (BKGD/MS)
45
Port A input/output (I/O) pins (PTA7–PTA6 and PTA3–PTA0)
45
Port B input/output (I/O) pins (PTB7–PTB0)
46
Port C input/output (I/O) pins (PTC7–PTC0)
46
Port D input/output (I/O) pins (PTD7–PTD0)
46
Port E input/Output (I/O) pins (PTE7–PTE0)
46
Port F input/output (I/O) pins (PTF7–PTF0)
46
Port G input/output (I/O) pins (PTG3–PTG0)
47
Port H input/output (I/O) pins (PTH7–PTH6, PTH2–PTH0)
47
True open drain pins (PTA3–PTA2)
47
High current drive pins (PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, PTH1)
47
Peripheral pinouts
48
Run mode
51
Wait mode
52
Stop3 mode
52
Active BDM enabled in stop3 mode
52
LVD enabled in stop mode
53
Power modes behaviors
53
Power-on reset (POR) operation
55
LVD reset operation
55
Low-voltage warning (LVW)
55
PMC
56
PMC_SPMSC1
56
PMC_SPMSC2
58
Overview
73
Function descriptions
75
Modes of operation
75
Wait mode
75
Stop mode
75
Flash and EEPROM memory map
75
Flash and EEPROM initialization after system reset
76
Flash and EEPROM command operations
76
Writing the FCLKDIV register
78
Command write sequence
80
Flash and EEPROM interrupts
82
Description of flash and EEPROM interrupt operation
82
Protection
83
Security
87
Unsecuring the MCU using backdoor key access
87
Unsecuring the MCU using BDM
88
Mode and security effects on flash and EEPROM command availability
89
Flash and EEPROM commands
89
Flash commands
89
EEPROM commands
90
Allowed simultaneous flash and EEPROM operations
90
Flash and EEPROM command summary
91
Erase verify all blocks command
92
Erase verify block command
92
Erase verify flash section command
93
Read once command
94
Program flash command
95
Program once command
96
Erase all blocks command
97
Erase flash block command
97
Erase flash sector command
98
Unsecure flash command
99
Verify backdoor access key command
100
Set user margin level command
100
Erase verify EEPROM section command
102
Program EEPROM command
103
Erase EEPROM sector command
104
NVM
105
NVM_FCLKDIV
105
NVM_FSEC
106
NVM_FCCOBIX
107
NVM_FCNFG
107
NVM_FERCNFG
108
NVM_FSTAT
109
NVM_FERSTAT
110
NVM_FPROT
111
NVM_EEPROT
112
NVM_FCCOBHI
114
NVM_FCCOBLO
114
NVM_FOPT
114
SCI0 pin reassignment
118
SPI0 pin reassignment
118
IIC pins reassignments
118
FTM2 channels pin reassignment
119
Bus clock output pin enable
119
ACMP output selection
120
SCI0 TxD modulation
120
SCI0 RxD capture
121
SCI0 RxD filter
121
RTC capture
122
FTM2 software synchronization
122
ADC hardware trigger
122
SYS
123
SYS_SRS
123
SYS_SBDFR
125
SYS_SDIDH
126
SYS_SDIDL
126
SYS_SOPT1
127
SYS_SOPT2
128
SYS_SOPT3
129
SYS_SOPT4
130
SYS_ILLAH
131
SYS_ILLAL
131
SYS_UUID1
132
SYS_UUID2
132
SYS_UUID3
133
SYS_UUID4
133
SYS_UUID5
134
SYS_UUID6
134
SYS_UUID7
135
SYS_UUID8
135
PORT
141
PORT_PTAD
142
PORT_PTBD
144
PORT_PTCD
144
PORT_PTDD
145
PORT_PTED
145
PORT_PTFD
146
PORT_PTGD
146
PORT_PTHD
147
PORT_HDRVE
148
PORT_PTAOE
149
PORT_PTBOE
150
PORT_PTCOE
151
PORT_PTDOE
152
PORT_PTEOE
154
PORT_PTFOE
155
PORT_PTGOE
156
PORT_PTHOE
157
PORT_PTAIE
158
PORT_PTBIE
159
PORT_PTCIE
160
PORT_PTDIE
161
PORT_PTEIE
163
PORT_PTFIE
164
PORT_PTGIE
165
PORT_PTHIE
166
PORT_IOFLT0
167
PORT_IOFLT1
168
PORT_IOFLT2
169
PORT_FCLKDIV
169
PORT_PTAPE
170
PORT_PTBPE
172
PORT_PTCPE
173
PORT_PTDPE
174
PORT_PTEPE
176
PORT_PTFPE
177
PORT_PTGPE
178
PORT_PTHPE
179
Function description
183
Bus frequency divider
184
Low power bit usage
184
Internal reference clock (ICSIRCLK)
184
Fixed frequency clock (ICSFFCLK)
185
BDC clock
186
Modes of operation
186
FLL engaged internal (FEI)
187
FLL engaged external (FEE)
187
FLL bypassed internal (FBI)
187
FLL bypassed internal low power (FBILP)
188
FLL bypassed external (FBE)
188
FLL bypassed external low power (FBELP)
189
Stop (STOP)
189
Initializing FEI mode
191
Initializing FBI mode
191
Initializing FEE mode
191
Initializing FBE mode
192
External oscillator (OSC)
192
Bypass mode
193
Low-power configuration
193
High-gain configuration
194
Initializing external oscillator for peripherals
194
ICS
196
ICS_C1
196
ICS_C2
197
ICS_C3
198
ICS_C4
198
ICS_S
199
ICS_OSCSC
200
SCG
201
SCG_C1
202
SCG_C2
203
SCG_C3
204
SCG_C4
205
Central processor unit (CPU)
207
Debug module (DBG)
207
Watchdog (WDOG)
208
Random-access-memory (RAM)
210
Non-volatile memory (NVM)
210
Cyclic redundancy check (CRC)
211
FlexTimer module (FTM)
213
FTM0 interconnection
214
FTM1 interconnection
215
FTM2 interconnection
215
8-bit modulo timer (MTIM)
215
MTIM0 as ADC hardware trigger
216
Real-time counter (RTC)
217
Serial communications interface (SCI)
219
8-Bit Serial Peripheral Interface (8-bit SPI)
221
16-bit serial peripheral interface (16-bit SPI)
223
Inter-Integrated Circuit (I2C)
225
Analog-to-digital converter (ADC)
227
ADC channel assignments
228
Alternate clock
229
Hardware trigger
230
Temperature sensor
230
Analog comparator (ACMP)
231
ACMP configuration information
232
ACMP in stop3 mode
233
ACMP to FTM configuration information
233
ACMP for SCI0 RXD filter
233
Keyboard interrupts (KBI)
234
Touch sense input (TSI)
236
TSI channel assignments
237
Hardware trigger
238
Features
239
Accumulator (A)
240
Index Register (H:X)
241
Stack Pointer (SP)
241
Program Counter (PC)
242
Condition Code Register (CCR)
242
Inherent Addressing Mode (INH)
244
Relative Addressing Mode (REL)
244
Immediate Addressing Mode (IMM)
244
Direct Addressing Mode (DIR)
245
Extended Addressing Mode (EXT)
245
Indexed Addressing Mode
246
Indexed, No Offset (IX)
246
Indexed, No Offset with Post Increment (IX+)
246
Indexed, 8-Bit Offset (IX1)
246
Indexed, 8-Bit Offset with Post Increment (IX1+)
247
Indexed, 16-Bit Offset (IX2)
247
SP-Relative, 8-Bit Offset (SP1)
247
SP-Relative, 16-Bit Offset (SP2)
248
Memory to memory Addressing Mode
248
Direct to Direct
248
Immediate to Direct
248
Indexed to Direct, Post Increment
248
Direct to Indexed, Post-Increment
249
Stop mode
249
Wait mode
249
Background mode
250
Security mode
251
Reset Sequence
253
Interrupt Sequence
253
Features
267
Modes of Operation
267
KBI in Wait mode
267
KBI in Stop modes
268
Block Diagram
268
Edge-only sensitivity
272
Edge and level sensitivity
272
KBI Pullup Resistor
272
KBI initialization
272
FlexTimer philosophy
275
Features
276
Modes of operation
277
Block diagram
277
EXTCLK — FTM external clock
280
CHn — FTM channel (n) I/O pin
280
FAULTj — FTM fault input
280
Module memory map
281
Register descriptions
281
Clock Source
312
Counter Clock Source
312
Prescaler
313
Counter
313
Up counting
313
Up-down counting
316
Free running counter
317
Counter reset
318
Input capture mode
318
Filter for input capture mode
319
Output compare mode
320
Edge-aligned PWM (EPWM) mode
322
Center-aligned PWM (CPWM) mode
324
Combine mode
326
Asymmetrical PWM
333
Complementary mode
333
Update of the registers with write buffers
334
CNTINH:L registers
334
MODH:L registers
334
CnVH:L registers
335
PWM synchronization
336
Hardware trigger
336
Software trigger
337
Boundary cycle
338
MODH:L registers synchronization
339
CnVH:L registers synchronization
341
OUTMASK register synchronization
341
FTM counter synchronization
343
Summary of PWM synchronization
345
Deadtime insertion
347
Deadtime insertion corner cases
348
Output mask
349
Fault control
350
Automatic fault clearing
352
Manual fault clearing
353
Polarity control
354
Initialization
354
Features priority
355
Channel trigger output
355
Initialization trigger
356
Capture test mode
358
Dual edge capture mode
359
One-shot capture mode
361
Continuous capture mode
361
Pulse width measurement
362
Period measurement
364
Read coherency mechanism
366
TPM emulation
368
MODH:L and CnVH:L synchronization
368
Free running counter
368
Write to SC
368
Write to CnSC
368
BDM mode
368
Timer overflow interrupt
371
Channel (n) interrupt
371
Fault interrupt
371
MTIM in wait mode
374
MTIM in stop mode
374
MTIM in active background mode
374
MTIM operation example
380
Modes of operation
381
Wait mode
381
Stop modes
382
Block diagram
382
RTC
383
RTC_SC1
383
RTC_SC2
384
RTC_MODH
385
RTC_MODL
385
RTC_CNTH
386
RTC_CNTL
386
RTC operation example
388
Features
391
Modes of operation
391
Block diagram
392
Detailed signal descriptions
394
Baud rate generation
405
Transmitter functional description
406
Send break and queued idle
406
Receiver functional description
407
Data sampling technique
408
Receiver wake-up operation
409
Idle-line wakeup
409
Address-mark wakeup
410
Interrupts and status flags
410
Baud rate tolerance
411
Slow data tolerance
412
Fast data tolerance
413
Additional SCI functions
414
8- and 9-bit data modes
414
Stop mode operation
414
Loop mode
415
Single-wire operation
415
Features
417
Modes of Operation
418
Block Diagrams
418
SPI System Block Diagram
419
SPI Module Block Diagram
419
SPSCK — SPI Serial Clock
421
MOSI — Master Data Out, Slave Data In
421
MISO — Master Data In, Slave Data Out
421
SS — Slave Select
421
General
428
Master Mode
429
Slave Mode
430
SPI Clock Formats
432
SPI Baud Rate Generation
435
Special Features
435
SS Output
435
Bidirectional Mode (MOMI or SISO)
436
Error Conditions
437
Mode Fault Error
437
Low Power Mode Options
438
SPI in Run Mode
438
SPI in Wait Mode
438
SPI in Stop Mode
439
Reset
439
Interrupts
440
MODF
440
SPRF
440
SPTEF
441
SPMF
441
Initialization Sequence
441
Pseudo-Code Example
442
Features
445
Modes of operation
446
Block diagrams
447
SPI system block diagram
447
SPI module block diagram
447
SPSCK — SPI Serial Clock
450
MOSI — Master Data Out, Slave Data In
450
MISO — Master Data In, Slave Data Out
450
SS — Slave Select
450
General
464
Master mode
464
Slave mode
465
SPI FIFO Mode
467
Data Transmission Length
468
SPI clock formats
469
SPI baud rate generation
472
Special features
472
SS Output
472
Bidirectional mode (MOMI or SISO)
473
Error conditions
474
Mode fault error
474
Low-power mode options
475
SPI in Run mode
475
SPI in Wait mode
475
SPI in Stop mode
476
Reset
476
Interrupts
477
MODF
477
SPRF
477
SPTEF
478
SPMF
478
TNEAREF
478
RNFULLF
478
Initialization sequence
479
Pseudo-Code Example
479
Features
483
Modes of operation
484
Block diagram
484
I2C
486
I2C_A1
486
I2C_F
486
I2C_C1
488
I2C_S1
489
I2C_D
491
I2C_C2
491
I2C_FLT
492
I2C_RA
493
I2C_SMB
493
I2C_A2
495
I2C_SLTH
495
I2C_SLTL
496
I2C protocol
496
START signal
497
Slave address transmission
497
Data transfers
498
STOP signal
498
Repeated START signal
498
Arbitration procedure
499
Clock synchronization
499
Handshaking
500
Clock stretching
500
I2C divider and hold values
500
10-bit address
501
Master-transmitter addresses a slave-receiver
502
Master-receiver addresses a slave-transmitter
502
Address matching
503
System management bus specification
504
Timeouts
504
SCL low timeout
504
SCL high timeout
504
CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
505
FAST ACK and NACK
506
Resets
506
Interrupts
506
Byte transfer interrupt
507
Address detect interrupt
507
Exit from low-power/stop modes
507
Arbitration lost interrupt
508
Timeout interrupt in SMBus
508
Programmable input glitch filter
509
Address matching wake-up
509
Features
513
Block Diagram
514
Analog Power (VDDA)
515
Analog Ground (VSSA)
515
Voltage Reference High (VREFH)
515
Voltage Reference Low (VREFL)
515
Analog Channel Inputs (ADx)
515
ADC
516
ADC_SC1
516
ADC_SC2
518
ADC_SC3
519
ADC_SC4
520
ADC_RH
521
ADC_RL
522
ADC_CVH
522
ADC_CVL
523
ADC_APCTL1
523
ADC_APCTL2
524
Clock select and divide control
526
Input select and pin control
527
Hardware trigger
527
Conversion control
528
Initiating conversions
528
Completing conversions
528
Aborting conversions
529
Power control
529
Sample time and total conversion time
530
Automatic compare function
531
FIFO operation
532
MCU wait mode operation
535
MCU Stop3 mode operation
536
Stop3 mode with ADACK disabled
536
Stop3 mode with ADACK enabled
536
ADC module initialization example
537
Initialization sequence
537
Pseudo-code example
538
ADC FIFO module initialization example
538
Pseudo-code example
539
External pins and routing
540
Analog supply pins
540
Analog reference pins
540
Analog input pins
541
Sources of error
542
Sampling error
542
Pin leakage error
542
Noise-induced errors
542
Code width and quantization error
543
Linearity errors
544
Code jitter, non-monotonicity, and missing codes
544
Features
547
Modes of operation
547
Operation in Wait mode
548
Operation in Stop3 mode
548
Operation in Debug mode
548
Block diagram
548
ACMP
549
ACMP_CS
549
ACMP_C0
550
ACMP_C1
551
ACMP_C2
552
Features
555
Modes of operation
556
Block diagram
556
TSI[15:0]
557
TSI
557
TSI_CS0
558
TSI_CS1
559
TSI_CS2
561
TSI_CS3
562
TSI_PEN0
562
TSI_PEN1
564
TSI_CNTH
565
TSI_CNTL
565
Capacitance measurement
566
TSI electrode oscillator
566
Electrode oscillator and counter module control
567
TSI reference oscillator
568
TSI measurement result
569
Enable TSI module
569
Software and hardware trigger
569
Scan times
570
Clock setting
570
Reference voltage
570
Current source
571
Pin enable
571
End of scan
571
Noise detection mode
572
CRC
576
CRC_D0
577
CRC_D1
577
CRC_D2
578
CRC_D3
579
CRC_P0
579
CRC_P1
580
CRC_P2
580
CRC_P3
581
CRC_CTRL
581
16-bit CRC calculation
582
32-bit CRC calculation
582
Bit reverse
583
Result complement
583
CCITT compliant CRC example
583
Features
585
Block diagram
586
WDOG
587
WDOG_CS1
587
WDOG_CS2
589
WDOG_CNTH
590
WDOG_CNTL
590
WDOG_TOVALH
591
WDOG_TOVALL
591
WDOG_WINH
592
WDOG_WINL
592
Watchdog refresh mechanism
593
Window mode
594
Refreshing the Watchdog
594
Example code: Refreshing the Watchdog
595
Configuring the Watchdog
595
Reconfiguring the Watchdog
595
Unlocking the Watchdog
596
Example code: Reconfiguring the Watchdog
596
Clock source
596
Using interrupts to delay resets
598
Backup reset
598
Functionality in debug and low-power modes
598
Fast testing of the watchdog
599
Testing each byte of the counter
599
Entering user mode
600
Forcing active background
601
Features
601
BKGD pin description
603
Communication details
604
BDC commands
606
BDC hardware breakpoint
609
Comparators A and B
610
Bus capture information and FIFO operation
610
Change-of-flow information
611
Tag vs. force breakpoints and triggers
612
Trigger modes
613
Hardware breakpoints
614
BDC
615
BDC_SCR
615
BDC_BKPTH
617
BDC_BKPTL
618
BDC_SBDFR
618
Features
621
Modes of operation
622
Block diagram
622
DBG
624
DBG_CAH
624
DBG_CAL
625
DBG_CBH
626
DBG_CBL
626
DBG_CCH
627
DBG_CCL
628
DBG_FH
628
DBG_FL
629
DBG_CAX
630
DBG_CBX
631
DBG_CCX
632
DBG_FX
633
DBG_C
633
DBG_T
634
DBG_S
636
DBG_CNT
637
Comparator
638
RWA and RWAEN in full modes
638
Comparator C in loop1 capture mode
638
Breakpoints
639
Hardware breakpoints
639
Trigger selection
640
Trigger break control (TBC)
640
Begin- and end-trigger
641
Arming the DBG module
641
Trigger modes
642
A only
642
A or B
642
A then B
642
Event only B
642
A then event only B
642
A and B (full mode)
642
A and not B (full mode)
643
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