Intel®
Core
TM
Duo Processor and
Intel®
Core
TM
Solo Processor on
65 nm Process
Specification Update
June 2009
Revision 020
2 Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL
PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY
APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR
DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the
absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The
information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
deviate from published specifications.
Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Intel Core, Pentium, Celeron, Intel Xeon, Intel SpeedStep, MMX and the Intel logo are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2006 – 2009, Intel Corporation. All rights reserved.
Specification Update 3
Contents
Revision History ...................................................................................................................4
Preface ...............................................................................................................................6
Summary Tables of Changes ..................................................................................................8
Identification Information ....................................................................................................16
Errata ...............................................................................................................................19
Specification Changes .........................................................................................................51
Specification Clarifications ...................................................................................................52
Documentation Changes ......................................................................................................53
Revision History
4 Specification Update
Revision History
Document
Number
Revision Description Date
309222 -001 Initial release January 2006
309222 -002 • Updated Processor Identification (Table 1) April 2006
309222 -003 • Added Errata AE35-AE40
• Updated Errata A14 and AE29
• Updated Processor Identification (Table 1)
May 2006
309222 -004 • Added Errata AE41-AE46
• Updated Processor Identification (Table 1)
• Updated Description for Code ‘A’ in Summary Table of
Changes
June 2006
309222 -005 • Added Errata AE47-AE69
• Removed Errata AE3
• Updated Errata AE4,AE6,AE8,AE9,AE11
,AE13,AE14,AE19 and AE29
• Updated Processor Identification (Table 1)
September 2006
309222 -006 • Updated Errata AE1
• Added Errata AE70
October 2006
309222 -007 • Updated Errata AE41 and AE55
• Added Errata AE71,AE72 and AE73
• Updated Processor Identification (Table 1)
November 2006
309222 -008 • Update AE33, AE63, AE73
• Added AE74-AE78
December 2006
309222 -009 • Added Errata AE79 and AE80 January 2007
309222 -010 • Added Errata AE81 March 2007
309222 -011 • Updated Errata AE50
• Updated Summary Table of Changes
April 2007
309222 -012 • Updated Summary Table of Changes
• Updated Hyperlinks for the SDM Collateral under the
“Related Documents” section
July 2007
309222 -013 • Updated Stepping Codes Used in Summary Table
• Updated Erratum AE16
• Added Erratum AE82
September 2007
Revision History
Specification Update 5
309222 -014 • Updated Stepping Codes Used in Summary Table
• Updated Erratum AE34
• Added Erratum AE83
November 2007
309222 -015 • Added Specification Clarification AE2
• Updated Stepping Codes Used in Summary Table
January 2008
309222 -016 • Updated Erratum AE32
• Updated Erratum AE60
February 2008
309222 -017 • Updated Stepping Codes Used in Summary Table July 2008
309222 -018 • Added Erratum AE84
• Updated Stepping Codes Used in Summary Table
October 2008
309222 -019 • Updated Erratum AE64
• Updated Stepping Codes Used in Summary Table
February 2009
309222 -020 • Updated Stepping Codes Used in Summary Table June 2009
§
Preface
6 Specification Update
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents table. It is a compilation of device and document
errata and specification clarifications and changes, and is intended for hardware
system manufacturers and for software developers of applications, operating system,
and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document
Number/Location
The Intel® Core™ Duo Processor and the Intel® Core™ Solo
Processor on 65 nm Process Datasheet
309221-006
Related Documents
Document Title Document
Number/Location
Intel® 64 and IA-32 Architecture Software Developer's Manual
Documentation Changes
252046
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 1: Basic Architecture
253665
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 2A: Instruction Set Reference, A-M
253666
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 2B: Instruction Set Reference, N-Z
253667
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 3A: System Programming Guide
253668
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 3B: System Programming Guide
253669
IA-32 Intel® Architecture Optimization Reference Manual 248966
Preface
Specification Update 7
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (e.g., core speed, L2 cache size, package
type, etc.) as described in the processor identification information table. Care should
be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the Intel® Core™ Duo
processor and the Intel® Core™ Solo processor on 65 nm process behavior to deviate
from published specifications. Hardware and software designed to be used with any
given stepping must assume that all errata documented for that stepping are present
on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§
Summary Tables of Changes
8 Specification Update
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed Processor
steppings. Intel intends to fix some of the errata in a future stepping of the
component, and to account for the other outstanding issues through documentation or
Specification Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that
applies to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Shaded: This item is either new or modified from the previous
version of the document.
Summary Tables of Changes
Specification Update 9
Note: Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M Processor with 2-MB L2 Cache and 400 MHz Front Side
Bus
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel(R) Celeron(R) processor in 478 pin package
AD = Intel(R) Celeron(R) D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™2 Extreme processor X6800Δ and Intel® Core™2 Duo desktop
processor E6000Δ and E4000Δ sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
Summary Tables of Changes
10 Specification Update
AK = Intel® Core™2 Extreme quad-core processor QX6000Δ sequence and Intel®
Core™2 Quad processor Q6000Δ sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad
processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY = Dual-Core Intel® Xeon® Processor 5200 Series
AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB = Dual-Core Intel® Xeon® E3110 Processor
AAC = Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme Processor QX9775Δ
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ Processor 300 series
AAI = Intel® Xeon® Processor 7400 Series
AAJ = Intel® Core™ i7 and Intel® Core™ i7 Extreme Edition
AAL = Intel® Pentium Dual-Core Processor E5000Δ Series
AAM = Intel® Xeon® Processor 3500 Series
Note: Δ Intel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details.
Summary Tables of Changes
Specification Update 11
Stepping Number
C0 D0 Dual Core
Only
Plans ERRATA
AE1 X X No Fix
FST Instruction with Numeric and Null Segment Exceptions May
Take Numeric Exception with Incorrect FPU Operand Pointer
AE2 X X No Fix
Code Segment Limit Violation May Occur on 4-Gbyte Limit
Check
AE3 Errata – Removed
AE4 X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types May
Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
AE5 X X No Fix
Memory Aliasing with Inconsistent A and D Bits May Cause
Processor Deadlock
AE6 X X No Fix
VM Bit Will Be Cleared on a Second Fault Handled by Task
Switch from Virtual-8086 (VM86)
AE7 X X No Fix
Page with PAT (Page Attribute Table) Set to USWC
(Uncacheable Speculative Write Combine) While Associated
MTRR (Memory Type Range Register) Is UC (Uncacheable) May
Consolidate to UC
AE8 X X No Fix
FPU Operand Pointer May Not Be Cleared following
FINIT/FNINIT
AE9 X X No Fix LTR Instruction May Result in Unexpected Behavior
AE10 X X No Fix
Invalid Entries in Page-Directory-Pointer-Table Register
(PDPTR) May Cause General Protection (#GP) Exception If the
Reserved Bits Are Set to One
AE11 X X No Fix
VMCALL When Executed during VMX Root Operation while CPL
> 0 May Not Generate #GP Fault
AE12 X X No Fix FP Inexact-result Exception Flag May Not Be Set
AE13 X X No Fix
A Locked Data Access That Spans across Two Pages
May Cause
the System to Hang
AE14 X X No Fix MOV to/from Debug Registers Causes Debug Exception
AE15 X X No Fix INIT Does Not Clear Global Entries in the TLB
AE16 X X No Fix
Use of Memory Aliasing with Inconsistent Memory Type May
Cause a System Hang or a Machine Check Exception
AE17 X X No Fix
Machine Check Exception May Occur When Interleaving Code
between Different Memory Types
AE18 X Fixed
Processor Digital Thermal Sensor (DTS) Readout Stops
Updating upon Returning from C3/C4 State
AE19 X X X No Fix
Data Prefetch Performance Monitoring Event Can Only Be
Enabled on a Single Core
AE20 X X No Fix
LOCK# Asserted during a Special Cycle Shutdown Transaction
May Unexpectedly Deassert
Summary Tables of Changes
12 Specification Update
Stepping
Number
C0 D0 Dual Core
Only
Plans ERRATA
AE21 X X X No Fix
Disable Execution-Disable Bit (IA32_MISC_ENABLES [34]) Is
Shared between Cores
AE22 X X No Fix
Last Branch Records (LBR) Updates May Be Incorrect after a
Task Switch
AE23 X X No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-Bit L2 ECC Errors May Be Incorrect
AE24 X X No Fix
Disabling of Single-Step On Branch Operation May Be Delayed
following a POPFD Instruction
AE25 X X No Fix
Performance Monitoring Counters That Count External Bus
Events May Report Incorrect Values after Processor Power
State Transitions
AE26 X X No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update
the Last Exception Record (LER) MSR
AE27 X X No Fix
General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AE28 X X No Fix
Performance Monitoring Events for Retired Floating Point
Operations (C1h) May Not Be Accurate
AE29 X X No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
AE30 X X No Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB)
May Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
AE31 X X No Fix
Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost
after Entry into SMM
AE32 X X No Fix
Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions and May Push the
Wrong Address Onto the Stack
AE33 X Fixed
Hardware Prefetch Performance Monitoring Events May Be
Counted Inaccurately
AE34 X X No Fix
Pending x87 FPU Exceptions (#MF) following STI May Be
Serviced before Higher Priority Interrupts
AE35 X X No Fix
Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
AE36 X X Fixed
CPU_CLK_UNHALTED Performance Monitoring Event (3CH)
Counts Clocks When the Processor Is in the C1/C2 Processor
Power States
AE37 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AE38 X X No Fix BTS Message May Be Lost When the STPCLK# Signal Is Active
AE39 X X No Fix
Certain Performance Monitoring Counters Related to Bus, L2
Cache and Power Management Are Inaccurate
Summary Tables of Changes
Specification Update 13
Stepping Number
C0 D0 Dual Core
Only
Plans ERRATA
AE40 X X No Fix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
AE41 X X X No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AE42 X X X No Fix
Simultaneous Access to the Same Page Table Entries by Both
Cores May Lead to Unexpected Processor Behavior
AE43 X X Fixed IO_SMI Indication in SMRAM State Save Area May Be Lost
AE44 X X X No Fix
Logical Processors May Not Detect Write-Back (WB) Memory
Writes
AE45 X X No Fix Last Exception Record (LER) MSRs May Be Incorrectly Updated
AE46 X X No Fix
SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null
Segment Selector” to SS and CS Registers
AE47 X X No Fix
Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
AE48 X X No Fix
Using 2-M/4-M pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AE49 X X X No Fix
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon
(Architectural Performance Monitoring) Specification
AE50 X X No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AE51 X X No Fix
Performance Monitoring Events for Retired Instructions (C0H)
May Not Be Accurate
AE52 X X No Fix
#GP Fault Is Not Generated on Writing IA32_MISC_ENABLE
[34] When Execute Disable Bit Is Not Supported
AE53 X X X No Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without
T
LB Shootdown May Cause Unexpected
Processor Behavior
AE54 X X No Fix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code
(SMC) Event May Cause Unexpected Behavior
AE55 X X X No Fix Shutdown Condition May Disable Non-Bootstrap Processors
AE56 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AE57 X X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a Memory
Ordering Issue
AE58 X X No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect
Data after a Machine Check Exception (MCE)
AE59 X X No Fix
Using Memory Type Aliasing with Memory Types WB/WT May
Lead to Unpredictable Behavior
Summary Tables of Changes
14 Specification Update
Stepping
Number
C0 D0 Dual Core
Only
Plans ERRATA
AE60 X X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by an
Instruction That Signals a Floating Point Exception
AE61 X X No Fix
Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AE62 X X No Fix
Values for LBR/BTS/BTM Will Be Incorrect after an Exit from
SMM
AE63 Erratum Removed
AE64 X X No Fix EFLAGS Discrepancy on Page Faults after a Translation Change
AE65 X X No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
AE66 X X No Fix
A Thermal Interrupt Is Not Generated When the Current
Temperature Is Invalid
AE67 X X No Fix Performance Monitoring Event FP_ASSIST May Not Be Accurate
AE68 X X No Fix
The BS Flag in DR6 May Be Set for Non-Single-Step #DB
Exception
AE69 X X No Fix
BTM/BTS Branch-from Instruction Address May Be Incorrect for
Software Interrupts
AE70 X X No Fix
Store to WT Memory Data May Be
Seen in Wrong Order by Two
Subsequent Loads
AE71 X X No Fix
Single Step Interrupts with Floating Point Exception Pending
May Be Mishandled
AE72 X X No Fix
Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
AE73 X X No Fix
Non-Temporal Data Store May Be Observed in Wrong Program
Order
AE74 X X No Fix
Unaligned Accesses to Paging Structures May Cause the
Processor to Hang
AE75 X X No Fix
Microcode Updates Performed during VMX Non-root Operation
Could Result in Unexpected Behavior
AE76 X X No Fix
INVLPG Operation for Large (2-M/4-M) Pages May Be
Incomplete Under Certain Conditions
AE77 X X No Fix
Page Access Bit May Be Set Prior to Signaling a Code Segment
Limit Fault
AE78 X X No Fix
Performance Monitoring Event for Hardware Prefetch Requests
(4EH) and Hardware Prefetch Request Cache Misses (4FH) May
Not Be Accurate
AE79 X X No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
AE80 X X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP
Summary Tables of Changes
Specification Update 15
Stepping Number
C0 D0 Dual Core
Only
Plans ERRATA
AE81 X X No Fix
Store Ordering May be Incorrect between WC and WP Memory
Types
AE82 X X No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May
Not Count Some Transitions
AE83 X X No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead
to Memory-Ordering Violations
AE84 X X No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
Number SPECIFICATION CHANGES
AE1 Updated Table 27. Stop Grant/Sleep/Deep Sleep AC Specifications
Number SPECIFICATION CLARIFICATIONS
AE1 PROCHOT# Signal Description – Removed, see current EMTS.
AE2 Enhanced Cache Error Reporting on D0 Stepping
Number DOCUMENTATION CHANGES
AE1 Updated Processor Numbers – Removed, see current EMTS
§
Identification Information
16 Specification Update
Identification Information
Component Identification via Programming Interface
The Intel Core Duo processor and Intel Core Solo processor on 65 nm process can be
identified by the following register contents:
Family
1
Model
2
0110 1110
1. The family corresponds to bit [11:8] of the EDX register after RESET, bits [11:8] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the generation field of the Device ID register accessible through Boundary Scan.
2. The family corresponds to bit [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the generation field of the Device ID register accessible through Boundary Scan.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to
the Intel® Processor Identification and the CPUID Instruction Application Note (AP-
485) for further information on the CPUID instruction.
Component Marking Information
Figure 1. Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process
(Micro-FCPGA/FCBGA) S-Spec Markings
Identification Information
Specification Update 17
Table 1. Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process
Identification Information
QDF/S-
SPEC#
Processor #
Package
Stepping
CPUID
FSB(MHz)
Speed
HFM/LFM
(GHz)
Notes
SL9JP T2700 Micro-FCPGA D-0 06ECh 667 2.33/1.00 3
SL9K4 T2700 Micro-FCBGA D-0 06ECh 667 2.33/1.00 3
SL9JN
T2600 Micro-FCPGA D-0 06ECh 667 2.16/1.00 3
SL9K3 T2600 Micro-FCBGA D-0 06ECh 667 2.16/1.00 3
SL9EH T2500 Micro-FCPGA D-0 06ECh 667 2.00/1.00 3
SL9K2 T2500 Micro-FCBGA D-0 06ECh 667 2.00/1.00 3
SL9JM T2400 Micro-FCPGA D-0 06ECh 667 1.83/1.00 3
SL9JZ T2400 Micro-FCBGA D-0 06ECh 667 1.83/1.00 3
SL9JL T2300 Micro-FCPGA D-0 06ECh 667 1.66/1.00 2
SL9JY T2300 Micro-FCBGA D-0 06ECh 667 1.66/1.00 2
SL9JE T2300E Micro-FCPGA D-0 06ECh 667 1.66/1.00 2
SL9JV T2300E Micro-FCBGA D-0 06ECh 667 1.66/1.00 2
SL9L5 T1400 Micro-FCPGA D-0 06ECh 667 1.83/1.00 1,2
SL9LJ T1400 Micro-FCBGA D-0 06ECh 667 1.83/1.00 1,2
SL9L4 T1300 Micro-FCPGA D-0 06ECh 667 1.66/1.00 1,2
SL9LH T1300 Micro-FCBGA D-0 06ECh 667 1.66/1.00 1,2
SL9JU L2500 Micro-FCBGA D-0 06ECh 667 1.83/1.00 7
SL9JT L2400 Micro-FCBGA D-0 06ECh 667 1.66/1.00 6
SL9JS L2300 Micro-FCBGA D-0 06ECh 667 1.5/1.00 6
SL8VN T2600 Micro-FCPGA C-0 06E8h 667 2.16/1.00 3
SL8VS T2600 Micro-FCBGA C-0 06E8h 667 2.16/1.00 3
SL8VP T2500 Micro-FCPGA C-0 06E8h 667 2.00/1.00 3
SL8VT T2500 Micro-FCBGA C-0 06E8h 667 2.00/1.00 3
SL8VQ T2400 Micro-FCPGA C-0 06E8h 667 1.83/1.00 3
SL8VU T2400 Micro-FCBGA C-0 06E8h 667 1.83/1.00 3
SL8VR T2300 Micro-FCPGA C-0 06E8h 667 1.66/1.00 2
SL8VV T2300 Micro-FCBGA C-0 06E8h 667 1.66/1.00 2
SL9DM T2300E Micro-FCPGA C-0 06E8h 667 1.66/1.00 2
SL9DN T2300E Micro-FCBGA C-0 06E8h 667 1.66/1.00 2
SL92V T1400 Micro-FCPGA C-0 06E8h 667 1.83/1.00 1,2
Identification Information
18 Specification Update
QDF/S-
SPEC#
Processor #
Package
Stepping
CPUID
FSB(MHz)
Speed
HFM/LFM
(GHz)
Notes
SL92X T1400 Micro-FCBGA C-0 06E8h 667 1.83/1.00 1,2
SL8VY T1300 Micro-FCPGA C-0 06E8h 667 1.66/1.00 1,2
SL8W3 T1300 Micro-FCBGA C-0 06E8h 667 1.66/1.00 1,2
SL8VW L2400 Micro-FCBGA C-0 06E8h 667 1.66/1.00 6
SL8VX L2300 Micro-FCBGA C-0 06E8h 667 1.50/1.00 6
SL99V U2500 Micro-FCBGA C-0 06E8h 533 1.20/.800 6
SL99W U2400 Micro-FCBGA C-0 06E8H 533 1.06/.800 6
SL8W6 U1400 Micro-FCBGA C-0 06E8h 533 1.2/0.800 5
SL8W7 U1300 Micro-FCBGA C-0 06E8h 533 1.06/.800 5
1. Single-core processor.
2. V
CC_CORE
= 1.300-1.1625/1.000-0.7625 V for HFM/LFM Range; Deeper Sleep OVID
Range = 0.850-0.550 V; Intel® Enhanced Deeper Sleep OVID Range = 0.800-0.500 V.
3. V
CC_CORE
= 1.2625-1.200/0.950 V for HFM Range/LFM; Deeper Sleep OVID Range =
0.800-0.750 V; Intel Enhanced Deeper Sleep OVID Range = 0.750-0.650 V.
4. V
CC_CORE
= 1.2125-1.000/1.000-0.7625 V for HFM/LFM Range; Deeper Sleep OVID
Range = 0.850-0.550 V; Intel Enhanced Deeper Sleep OVID Range = 0.800-0.500 V.
5. V
CC_CORE
= 1.0500-0.950/0.9375 V for HFM range /LFM Range; Deeper Sleep OVID
Range = 0.800-0.750 V; Intel Enhanced Deeper Sleep OVID Range = 0.750-0.650 V.
6. V
CC_CORE
= 1.02500-0.950/0.9375 V for HFM range /LFM Range; Deeper Sleep OVID
Range = 0.85-0.55 V; Intel Enhanced Deeper Sleep OVID Range = 0.800-0.500 V.
7. V
CC_CORE
= 1.000-1.2125/0.95 V for HFM range /LFM Range; Deeper Sleep OVID Range
= 0.85-0.55 V; Intel Enhanced Deeper Sleep OVID Range = 0.800-0.500 V.
§
Errata
Specification Update 19
Errata
AE1. FST Instruction with Numeric and Null Segment Exceptions May Take
Numeric Exception with Incorrect FPU Operand Pointer
Problem: If execution of an FST (Store Floating Point Value) instruction would generate both
numeric and Null segment exceptions, the numeric exceptions may be taken first and
with the Null x87 FPU Instruction Operand (Data) Pointer.
Implication: Due to this erratum, on an FST instruction the processor reports a numeric exception
instead of reporting an exception because of a Null segment. If the numeric exception
handler tries to access the FST data it will get a #GP fault. Intel has not observed this
erratum with any commercially-available software, or system.
Workaround: The numeric exception handler should check the segment, and if it is Null, avoid
further access to the data that caused the fault.
Status: For the steppings affected, see the Summary Tables of Changes
.
AE2. Code Segment Limit Violation May Occur on 4-Gbyte Limit Check
Problem: Code Segment limit violation may occur on 4-Gbyte limit check when the code stream
wraps around in a way that one instruction ends at the last byte of the segment and
the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially-available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes
.
AE3. Errata –Removed
Errata
20 Specification Update
AE4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the IA-32 Intel® Architecture Software
Developers Manual, section titled Out-of-Order Stores for String Operations in
Pentium® 4, Intel® Xeon®, and P6 Family Processors, the processor performs REP
MOVS or REP STOS as fast strings. Due to this erratum, fast string REP MOVS/REP
STOS instructions that cross page boundaries from WB/WC memory types to
UC/WP/WT memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new
page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.
AE5. Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Problem: In the event that software implements memory aliasing by having two Page Directory
Entries (PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty
bits for the two PDEs are allowed to become inconsistent the processor may become
deadlocked.
Implication: This erratum has not been observed with commercially-available software.
Workaround: Software that needs to implement memory aliasing in this way should manage the
consistency of the Accessed and Dirty bits.
Status: For the steppings affected, see the Summary Tables of Changes
.
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
-
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-
34
-
35
-
36
-
37
-
38
-
39
-
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
Ask a question and I''ll find the answer in the document
Finding information in a document is now easier with AI
Related papers
-
Intel LE80537VE001512 Datasheet
-
-
Intel Core 2 Duo E7300 Specification
-
-
-
-
-
-
-
Other documents
-
AMD K User manual
-
-
HP BL20p - ProLiant - G2 Owner's manual
-
Supermicro P4X4-028-512K Datasheet
-
-
Dell Red Hat Enterprise Linux Version 5 Owner's manual
-
Broadcom PEX 87xx Errata User guide
-
-
HP (Hewlett-Packard) 5992-4859 User manual
-