Kingston Technology KHX6400D2K2/1G Datasheet

Category
Memory modules
Type
Datasheet

Kingston Technology KHX6400D2K2/1G consists of two 512MB of DDR2-800 CL5 SDRAM memory modules – each is made up of eight 64M x 8-bit DDR2 FBGA components. It can run at DDR2 800MHz at low latency timing of 5-5-5-15 at 1.95V. SPD is programmed to JEDEC standard latency 667Mhz timing of 5-5-5-15 at 1.8V. It has a total kit capacity of 1GB (1024MB) and requires +1.8V of power. Features include double-data-rate architecture; two data transfers per clock cycle, bidirectional data strobe(DQS), differential clock inputs, programmable read latency 5 (clock), and more.

Kingston Technology KHX6400D2K2/1G consists of two 512MB of DDR2-800 CL5 SDRAM memory modules – each is made up of eight 64M x 8-bit DDR2 FBGA components. It can run at DDR2 800MHz at low latency timing of 5-5-5-15 at 1.95V. SPD is programmed to JEDEC standard latency 667Mhz timing of 5-5-5-15 at 1.8V. It has a total kit capacity of 1GB (1024MB) and requires +1.8V of power. Features include double-data-rate architecture; two data transfers per clock cycle, bidirectional data strobe(DQS), differential clock inputs, programmable read latency 5 (clock), and more.

Memory Module Specification
Document No. 4804266-001.B00
09/13/05
KHX6400D2K2/1G
1GB (512MB 64M x 64-Bit x 2 pcs.)
PC2-6400 CL5 240-Pin DIMM Kit
KEYED
Page 1
DESCRIPTION:
Kingston's KHX6400D2K2/1G is a kit of two 64M x 64-bit (512MB) DDR2-800 CL5 SDRAM
(Synchronous DRAM) memory modules, based on eight 64M x 8-bit DDR2 FBGA components per
module. Total kit capacity is 1GB (1024MB). Each module pair has been tested to run at DDR2
800MHz at low latency timing of 5-5-5-15 at 1.95V. The SPD is programmed to JEDEC standard
latency 667Mhz timing of 5-5-5-15 at 1.8V. Each 240-pin DIMM uses gold contact fingers and
requires +1.8V. The electrical and mechanical specifications are as follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-15 at +1.8V / 5-5-5-15 at +1.95V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.180” (30.00mm), single sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5 3ns (min.) / 8ns (max.)
Row Cycle Time (tRC) 54ns (min.)
Refresh to Active/Refresh Command Time (tRFC) 105ns
Row Active Time (tRAS) 39ns (min.) / 70,000ns (max.)
Single Power Supply of +1.8V (+/- .1V)
Power 1.622 W (operating per module)
UL Rating 94 V - 0
Operating Temperature 0
o
C to 55
o
C
Storage Temperature -55
o
C to +125
o
C
TECHNOLOGY
Kingston Technology
Document No. 4804266-001.B00 Page 2
MODULE DIMENSIONS:
All Kingston products are tested to meet our published specifications. Some motherboards or system configurations may not
operate at the published HyperX memory speeds and timing settings. Kingston does not recommend that any user attempt to
run their computers faster than the published speed. Overclocking or modifying your system timing may result in damage to
computer components.
For more information, go to www.kingston.com
Units: millimeters
1.270 ± 0.10
2.7
2.50
1.00
0.20
2.50±0.20
5.00
4.00
1.50±0.10
0.80±0.05
4.00
3.80
3.00
4.00
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Kingston Technology KHX6400D2K2/1G Datasheet

Category
Memory modules
Type
Datasheet

Kingston Technology KHX6400D2K2/1G consists of two 512MB of DDR2-800 CL5 SDRAM memory modules – each is made up of eight 64M x 8-bit DDR2 FBGA components. It can run at DDR2 800MHz at low latency timing of 5-5-5-15 at 1.95V. SPD is programmed to JEDEC standard latency 667Mhz timing of 5-5-5-15 at 1.8V. It has a total kit capacity of 1GB (1024MB) and requires +1.8V of power. Features include double-data-rate architecture; two data transfers per clock cycle, bidirectional data strobe(DQS), differential clock inputs, programmable read latency 5 (clock), and more.

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