Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-13194 Rev. *A Revised March 26, 2007
CY62138F MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
1
, CE
2,
and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Functional Description
[1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Logic Block Diagram
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
256K x 8
ARRAY
DATA IN DRIVERS
A
10
A
11
A
17
CE
1
CE
2
A
12
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
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Document #: 001-13194 Rev. *A Page 2 of 10
CY62138F MoBL
®
Pin Configuration
[2]
Product Portfolio
Product
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating I
CC
(mA)
Standby I
SB2
(µA)
f = 1MHz f = f
max
Min Typ
[3]
Max Typ
[3]
Max Typ
[3]
Max Typ
[3]
Max
CY62138FLL 4.5V 5.0V 5.5V 45 1.6 2.5 13 18 1 5
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC/TSOP II Pinout
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
CE
2
WE
OE
CE
1
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
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Document #: 001-13194 Rev. *A Page 3 of 10
CY62138F MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.5V to 6.0V (V
CCmax
+ 0.5V)
DC Voltage Applied to Outputs
in High-Z state
[4, 5]
................–0.5V to 6.0V (V
CCmax
+ 0.5V)
DC Input Voltage
[4, 5]
............ –0.5V to 6.0V (V
CCmax
+ 0.5V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[6]
CY62138FLL Industrial –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
45 ns
Unit
Min Typ
[3]
Max
V
OH
Output HIGH Voltage I
OH
= –1.0 mA 2.4 V
V
OL
Output LOW Voltage I
OL
= 2.1 mA 0.4 V
V
IH
Input HIGH Voltage V
CC
= 4.5V to 5.5V 2.2 V
CC
+ 0.5 V
V
IL
Input LOW Voltage V
CC
= 4.5V to 5.5V –0.5 0.8 V
I
IX
Input Leakage Current GND < V
I
< V
CC
–1 +1 µA
I
OZ
Output Leakage Current GND < V
O
< V
CC
, Output Disabled –1 +1 µA
I
CC
V
CC
Operating Supply
Current
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
13 18 mA
f = 1 MHz 1.6 2.5
I
SB2
[7]
Automatic CE Power Down
Current CMOS inputs
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
15µA
Capacitance (For all packages)
[8]
Parameter Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
10 pF
C
OUT
Output capacitance 10 pF
Thermal Resistance
[8]
Parameter Description Test Conditions SOIC TSOP II Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
44.53 44.16 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
24.05 11.97 °C/W
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+0.75V for pulse durations less than 20ns.
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
7. Only chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
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Document #: 001-13194 Rev. *A Page 4 of 10
CY62138F MoBL
®
AC Test Loads and Waveforms
Parameters 5.0V Unit
R1 1800 Ω
R2 990 Ω
R
TH
639 Ω
V
TH
1.77 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
[3]
Max Unit
V
DR
V
CC
for Data Retention 2.0 V
I
CCDR
[7]
Data Retention Current V
CC
= V
DR
, CE
1
> V
CC
− 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
15µA
t
CDR
[8]
Chip Deselect to Data
Retention Time
0ns
t
R
[9]
Operation Recovery Time t
RC
ns
Data Retention Waveform
[10]
3.0V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 2.0V
DATA RETENTION MODE
t
R
V
CC
CE
Notes:
9. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 µs or stable at V
CC(min)
> 100 µs.
10. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
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Document #: 001-13194 Rev. *A Page 5 of 10
CY62138F MoBL
®
Switching Characteristics (Over the Operating Range)
[11]
Parameter Description
45 ns
Unit
Min Max
Read Cycle
t
RC
Read Cycle Time 45 ns
t
AA
Address to Data Valid 45 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
45 ns
t
DOE
OE LOW to Data Valid 22 ns
t
LZOE
OE LOW to Low-Z
[12]
5ns
t
HZOE
OE HIGH to High-Z
[12, 13]
18 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[12]
10 ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High-Z
[12, 13]
18 ns
t
PU
CE
1
LOW and CE
2
HIGH
to power up 0 ns
t
PD
CE
1
HIGH or CE
2
LOW
to power down 45 ns
Write Cycle
[14]
t
WC
Write Cycle Time 45 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 35 ns
t
AW
Address Setup to Write End 35 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 35 ns
t
SD
Data Setup to Write end 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High-Z
[12, 13]
18 ns
t
LZWE
WE HIGH to Low-Z
[12]
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the AC Test Loads and Waveforms on page 4.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
13. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Document #: 001-13194 Rev. *A Page 6 of 10
CY62138F MoBL
®
Switching Waveforms
Read Cycle 1 (Address transition controlled)
[15, 16]
Read Cycle No. 2 (OE controlled)
[10, 16, 17]
Write Cycle No. 1 (WE controlled)
[10, 14, 18, 19]
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
IMPEDANCE
I
CC
I
SB
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
DATA VALID
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
20
Notes:
15. The device is continuously selected. OE
, CE
1
= V
IL
, CE
2
= V
IH
.
16. WE
is HIGH for read cycle.
17. Address valid before or similar to CE
1
transition LOW and CE
2
transition HIGH.
18. Data IO is high impedance if OE
= V
IH
.
19. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
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Document #: 001-13194 Rev. *A Page 7 of 10
CY62138F MoBL
®
Write Cycle No. 2 (CE1 or CE2 controlled)
[10, 14, 18, 19]
Write Cycle No. 3 (WE controlled, OE LOW)
[10, 19]
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power Down Standby (I
SB
)
L H L Data Out Read Active (I
CC
)
L L X Data In Write Active (I
CC
)
L H H High Z Selected, Outputs Disabled Active (I
CC
)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram
Package Type
Operating
Range
45 CY62138FLL-45SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial
CY62138FLL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA IO
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA IO
NOTE
20
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Document #: 001-13194 Rev. *A Page 8 of 10
CY62138F MoBL
®
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING P LANE
116
17 32
0.004[0.102]
51-85081-*B
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Document #: 001-13194 Rev. *A Page 9 of 10
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62138F MoBL
®
Figure 2. 32-Pin TSOP II, 51-85095
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85095-**
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Document #: 001-13194 Rev. *A Page 10 of 10
CY62138F MoBL
®
Document History Page
Document Title: CY62138F MoBL
®
2-Mbit (256K x 8) Static RAM
Document Number: 001-13194
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 797956 See ECN VKN New Data Sheet
*A 940341 See ECN VKN Added footnote #7 related to I
SB2
and
I
CCDR
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