8.18. Power Good ...................................................................................................................................................... 21
8.19. Speaker ............................................................................................................................................................ 21
9. FPGA ........................................................................................................................................................................ 22
9.1. GPIO Signals between FPGA and MCU ............................................................................................................ 22
9.2. LPC Bus Controller ............................................................................................................................................. 22
9.3. Address Map....................................................................................................................................................... 23
9.3.1. I
2
C Controller ............................................................................................................................................. 23
9.3.2. LED Control Register ................................................................................................................................ 24
9.3.3. WDT Control Register ............................................................................................................................... 24
9.3.4. FAN Control Resister ................................................................................................................................ 25
10. VOLTAGE MONITORING SOFTWARE SPECIFICATIONS ................................................................................................ 26
10.1. Description of Operation ................................................................................................................................... 26
10.1.1. Voltage Monitoring Operation ................................................................................................................. 26
10.1.2. Notifying the Bit Error of FPGA Configuration Memory .......................................................................... 26
10.1.3. 10GbEthernet LED Control .................................................................................................................... 26
10.2. Address ............................................................................................................................................................. 27
10.2.1. Address List ............................................................................................................................................ 27
10.2.2. Detailed Description of Bit ....................................................................................................................... 28
11. Connector and Jumper/LED................................................................................................................................. 35
11.1. CPU Module Onboard Component .................................................................................................................. 35
11.1.1. LED1 (General Purpose Status LED) ..................................................................................................... 37
11.2. Setting ............................................................................................................................................................... 37
11.2.1. JP2 (CMOS_CLR Setting Pin) ................................................................................................................ 37
11.2.2. SW1(PCI Express/LAN select switch).................................................................................................... 37
12. Pin Layout .............................................................................................................................................................. 38
12.1. CN1 (COM Express Stacking Connector) ........................................................................................................ 38
12.2. CN7 (Multi ISP Connector) ............................................................................................................................... 40
13. Address Map .......................................................................................................................................................... 41
13.1. IO Space ........................................................................................................................................................... 41
13.2. Memory Space ................................................................................................................................................. 42
13.3. PCI devices....................................................................................................................................................... 43
13.4. SMBus Address Map ........................................................................................................................................ 43
13.5. I
2
C Address Map ............................................................................................................................................... 43
14. BIOS ........................................................................................................................................................................ 44
14.1. Displayed Contents of BIOS Setup Menu ........................................................................................................ 44
14.1.1. BIOS Setup Menu ................................................................................................................................... 45
14.1.2. EDKII Menu ............................................................................................................................................. 46
14.1.3. Boot Manager Menu................................................................................................................................ 78
14.1.4. Boot Maintenance Manager .................................................................................................................... 78
14.2. Recording Method For an error Detected During POST .................................................................................. 81
15. Heat Sink ................................................................................................................................................................ 83
15.1. Passive heat sink (M38001A0) ......................................................................................................................... 83
15.2. Active heat sink (M38001B0)............................................................................................................................ 85
15.3. Active heat sink eTEMP (M38001C0) .............................................................................................................. 87
Notes ............................................................................................................................................................................ 89